bjit: use a bitset for register tracking in the rewriter and use r12, r15, rbx, rbp in PPs and the bjit
Keeping the available registers in a bitset makes it more memory efficient and
also easier and more performant to calculate a subset of the registers.
I will soon implement the 'otherThan' functionality using it which would fix the current problem of only allowing to exclude one register

keep track of which variables are known to be a python bool so that we can remove some of the nonzero() calls

at somepoint we really should split all this common code into a function...

Some SciPy fixing.

This is hacky, but delve into scipy souce code to fix the numerous
implicit function declaration is not make sense for now.

Because scipy rely on NumPy, so add scipy test to numpy_test.py. And
rename it to scipy_test.py. numpy_full_test.py will check numpy test
suite. The scipy_test.py only for check scipy test suite. But scipy test
will take a long time. So disabled it by default.

In PyDict_Next, the 3rd argument `pkey` and 4th argument pvalue could be
NULL. lxml will try to call it by PyDict_Next(kwdict, &pos, &key, 0).
And a check like CPython did.

Cython try to store argcount, nlocals, and varnames through PyCode_New.
But Pyston don't do anything with those or support getting them back
out.

Some scipy fixes

I had spelled the test name wrong

The repro is:
- import a.b, and in a.b do
- import a.b as ab

This will cause an attribute error, since a.b (the name) is successfully importable,
but a.b (the attribute) doesn't exist yet.

VRegSet: use a llvm bitvector as representation

Add missing tp_as_mapping

Support attrwrapper as globals argument to execfile

It keeps timing out

Or rather, have execfile() be more permissive in what it accepts.
It may still abort when we get to pickGlobalsAndLocals() and we
discover that we can't actually execute in that particular attrwrapper.

only lookup __[set/get/del]slice__ for slice AST nodes

Switch almost everything to use vregs when possible

before this change
C()[slice(1,2)] = "a"
would call into `__setslice__` because it got handled as
C()[1,2] = "a"

This commits adds cpythons assign_slice/apply_slice and add rewriter support for them.

The VRegMap doesn't contain explicit "is-set" bits, so I originally
just had iteration return all values.

But all the uses of it ended up needing to have a default value to represent
"not set in map" and then iterating would explicitly check if the value was
that and then would skip it.

Now that behavior is moved into VRegMap itself.

And update sys_test to support apport overriding excepthook

A tricky side-effect I didn't think about is that
block-local vregs can now look "live" at the end of
their block.  When using names, there are no other uses/defs,
but if we reassign the vreg there can be.

ie don't allow calling it for ones where multiple names
will reuse the same vreg

The benefit here is indirect, of letting us get rid of some
of the compatibility shims for moving between vregs and names.