rcw: add commented serdes configuration for serdes 9_4_3

We do not currently have a product for this configuration, it is merely
an example for custom carriers.

patches/rcw-LSDK-21.08/0031-add-lx2160-cex7-configuration-9_4_3.patch

+From 817d0e13ea9fbf2825eb7912b714ac1358107229 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Wed, 27 Sep 2023 12:06:01 +0200
+Subject: [PATCH] add lx2160 cex7 configuration 9_4_3
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_SD1_1.rcwi |  2 ++
+ lx2160acex7/configs/lx2160a_SD1_4.rcwi |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_9.rcwi | 18 ++++++++++++++++++
+ lx2160acex7/configs/lx2160a_SD2_4.rcwi | 19 +++++++++++++++++++
+ 4 files changed, 42 insertions(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_9.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD1_1.rcwi b/lx2160acex7/configs/lx2160a_SD1_1.rcwi
+index 07b8f3d..d633467 100644
+--- a/lx2160acex7/configs/lx2160a_SD1_1.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_1.rcwi
+@@ -3,6 +3,7 @@ SRDS_PRTCL_S1=1
+ 
+ /* Disable Serdes 1 PLLF */
+ SRDS_PLL_PD_PLL1=1
++SRDS_REFCLKF_DIS_S1=1
+ 
+ /* Don't use Serdes 1 PLLF for PLLS */
+ SRDS_INTRA_REF_CLK_S1=0
+@@ -19,3 +20,4 @@ SRDS_PLL_REF_CLK_SEL_S1=0
+ 
+ /* Configure Serdes 1 PCIe frequency divider for max. 5Gbps data rate (gen 1+2) */
+ SRDS_DIV_PEX_S1=2
++;abc=0?
+diff --git a/lx2160acex7/configs/lx2160a_SD1_4.rcwi b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+index dce9c05..f909d4a 100644
+--- a/lx2160acex7/configs/lx2160a_SD1_4.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+@@ -16,3 +16,6 @@ SRDS_PLL_PD_PLL2=0
+  * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+  */
+ SRDS_PLL_REF_CLK_SEL_S1=1
++
++/* Configure Serdes 1 PCIe frequency divider for max. 8Gbps data rate (gen 1+2+3) */
++SRDS_DIV_PEX_S1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD1_9.rcwi b/lx2160acex7/configs/lx2160a_SD1_9.rcwi
+new file mode 100644
+index 0000000..17335ef
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_9.rcwi
+@@ -0,0 +1,18 @@
++/* Serdes 1 Protocol 9: 6x1Gbps + 2xPCI-e-x1 */
++SRDS_PRTCL_S1=9
++
++/* Enable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/* Use Serdes 1 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for pci: Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 100MHz for pci, sgmii: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
+diff --git a/lx2160acex7/configs/lx2160a_SD2_4.rcwi b/lx2160acex7/configs/lx2160a_SD2_4.rcwi
+index a0b4cc7..115bf77 100644
+--- a/lx2160acex7/configs/lx2160a_SD2_4.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD2_4.rcwi
+@@ -1,2 +1,21 @@
++/* Serdes 2 Protocol 4: 1xPCI-e-x4 Gen 2, 1xPCI-e-x2 Gen 2, 2xSATA */
+ SRDS_PRTCL_S2=4
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Don't use Serdes 2 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz (Bit 0)
++ * Select Serdes 2 PLLS frequency 100MHz (Bit 1)
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
+ SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Configure Serdes 2 PCIe frequency divider for max. 5Gbps data rate (gen 1+2) */
++SRDS_DIV_PEX_S2=2
+-- 
+2.35.3
+