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Commit 93536f42 authored by Yazan Shhady's avatar Yazan Shhady
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lx2160a rcw: add SD1 mode 21 RCW 

lx2160acex7: add support for SERDES1 mode 21, wich support 6x 25GB [Lanes 1-4 & Lane 7-8].
Signed-off-by: default avatarYazan Shhady <yazan.shhady@solid-run.com>
parent c59d6f78
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patches/mc-utils/0006-lx2160acex7-add-DPL-DPC-files-for-SD1-protocol-21.patch 0 → 100644
View file @ 93536f42
From ed2ca5304f78d63e431c0558a125728b005f01b7 Mon Sep 17 00:00:00 2001
From: Yazan Shhady <yazan.shhady@solid-run.com>
Date: Sun, 3 Apr 2022 11:14:11 +0300
Subject: [PATCH] lx2160acex7: add DPL/DPC files for SD1 protocol #21
Signed-off-by: Yazan Shhady <yazan.shhady@solid-run.com>
---
config/lx2160a/CEX7/dpc-6x25g.dts | 97 +++++
config/lx2160a/CEX7/dpl-eth.6x25g.21.dts | 510 +++++++++++++++++++++++
2 files changed, 607 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-6x25g.dts
create mode 100644 config/lx2160a/CEX7/dpl-eth.6x25g.21.dts
diff --git a/config/lx2160a/CEX7/dpc-6x25g.dts b/config/lx2160a/CEX7/dpc-6x25g.dts
new file mode 100644
index 0000000..59fddad
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-6x25g.dts
@@ -0,0 +1,97 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@9 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@10 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-eth.6x25g.21.dts b/config/lx2160a/CEX7/dpl-eth.6x25g.21.dts
new file mode 100644
index 0000000..d5e55e7
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-eth.6x25g.21.dts
@@ -0,0 +1,510 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ dpl-version = <0xa>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+ dprc@1 {
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
+ /* ------------ DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0x0>;
+ };
+
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0x9 0xa 0x11>;
+ };
+
+
+ /* ------------ DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0x0 0x1>;
+ };
+
+ /* ------------ DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+
+ /* ------------ DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+
+ /* ------------ DPCON --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ obj@700 {
+ obj_name = "dpseci@0";
+ };
+
+ /* ------------ DPRTC --------------*/
+ obj@800 {
+ obj_name="dprtc@0";
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ /* ------------ DPNI --------------*/
+ dpni@0 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@1 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@2 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@3 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@4 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@5 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@6 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@7 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@8 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+
+ /* ------------ DPMAC ---------- */
+ dpmac@3 {
+ };
+
+ dpmac@4 {
+ };
+
+ dpmac@5 {
+ };
+
+ dpmac@6 {
+ };
+
+ dpmac@9 {
+ };
+
+ dpmac@10 {
+ };
+
+ dpmac@17 {
+ };
+
+ /* ------------ DPBP --------------*/
+ dpbp@0 {
+ };
+
+ dpbp@1 {
+ };
+
+
+ /* ------------ DPIO --------------*/
+ dpio@0 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ /* ------------ DPMCP --------------*/
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+
+ /* ------------ DPCON --------------*/
+ dpcon@0 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ num_priorities = <0x2>;
+ };
+ dpcon@16 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ num_priorities = <0x2>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ dpseci@0 {
+ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
+ options = "DPSECI_OPT_HAS_CG";
+ };
+
+ /* ------------ DPRTC --------------*/
+ dprtc@0 {
+ compatible="fsl,dprtc";
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ connection@1 {
+ endpoint1 = "dpni@0";
+ endpoint2 = "dpmac@17";
+ };
+ };
+};
+
--
2.25.1
patches/rcw-LSDK-21.08/0017-lx2160acex7-add-SD1-mode-21-serdes-configuratin.patch 0 → 100644
View file @ 93536f42
From 35939ae167ea47f49a6efcb115a36269e6ebc0d0 Mon Sep 17 00:00:00 2001
From: Yazan Shhady <yazan.shhady@solid-run.com>
Date: Sun, 3 Apr 2022 11:20:44 +0300
Subject: [PATCH] lx2160acex7: add SD1 mode 21 serdes configuratin
Signed-off-by: Yazan Shhady <yazan.shhady@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_21.rcwi | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_21.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_21.rcwi b/lx2160acex7/configs/lx2160a_SD1_21.rcwi
new file mode 100644
index 0000000..c62c262
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_21.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=21
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
--
2.25.1
runme.sh
View file @ 93536f42
...@@ -92,6 +92,10 @@ case "${SERDES}" in ...@@ -92,6 +92,10 @@ case "${SERDES}" in
DPC=dpc-dual-40g.dtb DPC=dpc-dual-40g.dtb
DPL=dpl-eth.dual-40g.19.dtb DPL=dpl-eth.dual-40g.19.dtb
;; ;;
21_*)
DPC=dpc-6x25g.dtb
DPL=dpl-eth.6x25g.21.dtb
;;
*) *)
echo "Please define SERDES configuration" echo "Please define SERDES configuration"
exit -1 exit -1
......
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