Skip to content

L
lx2160a_build
Commit 980b23ae authored by Josua Mayer's avatar Josua Mayer
Browse files
Options

add configuration for S1 protocol 10 swapped pllf/s, S2 protocol 4 (&0) 

Signed-off-by: default avatarJosua Mayer <josua@solid-run.com>
parent f57e1170
Hide whitespace changes
Inline Side-by-side
Showing with 674 additions and 0 deletions
patches/mc-utils/0009-lx2160acex7-add-configuration-for-Serdes-1-Protocol-.patch 0 → 100644
View file @ 980b23ae
From f2f2b0b5b3920339465bc817338fccd92b0b5e8f Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 21 Aug 2022 12:48:29 +0300
Subject: [PATCH] lx2160acex7: add configuration for Serdes 1 Protocol 10, 2
Protocol 0
6x USXGMII ports: dpmacs 4,5,6,8,9,10
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../CEX7/dpc-S1_10-S2_0-6x_usxgmii.dts | 94 ++++
config/lx2160a/CEX7/dpl-S1_10-S2_0-6x_eth.dts | 481 ++++++++++++++++++
2 files changed, 575 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-S1_10-S2_0-6x_usxgmii.dts
create mode 100644 config/lx2160a/CEX7/dpl-S1_10-S2_0-6x_eth.dts
diff --git a/config/lx2160a/CEX7/dpc-S1_10-S2_0-6x_usxgmii.dts b/config/lx2160a/CEX7/dpc-S1_10-S2_0-6x_usxgmii.dts
new file mode 100644
index 0000000..5124221
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-S1_10-S2_0-6x_usxgmii.dts
@@ -0,0 +1,94 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@8 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@9 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@10 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-S1_10-S2_0-6x_eth.dts b/config/lx2160a/CEX7/dpl-S1_10-S2_0-6x_eth.dts
new file mode 100644
index 0000000..4be49c2
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-S1_10-S2_0-6x_eth.dts
@@ -0,0 +1,481 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ dpl-version = <0xa>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+ dprc@1 {
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
+ /* ------------ DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5>;
+ };
+
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x4 0x5 0x6 0x8 0x9 0xa>;
+ };
+
+
+ /* ------------ DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0x0 0x1>;
+ };
+
+ /* ------------ DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+
+ /* ------------ DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+
+ /* ------------ DPCON --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ obj@700 {
+ obj_name = "dpseci@0";
+ };
+
+ /* ------------ DPRTC --------------*/
+ obj@800 {
+ obj_name="dprtc@0";
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ /* ------------ DPNI --------------*/
+ dpni@0 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@1 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@2 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@3 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@4 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@5 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpmac@4 {
+ };
+ dpmac@5 {
+ };
+ dpmac@6 {
+ };
+ dpmac@8 {
+ };
+ dpmac@9 {
+ };
+ dpmac@10 {
+ };
+
+
+ /* ------------ DPBP --------------*/
+ dpbp@0 {
+ };
+
+ dpbp@1 {
+ };
+
+
+ /* ------------ DPIO --------------*/
+ dpio@0 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ /* ------------ DPMCP --------------*/
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+
+ /* ------------ DPCON --------------*/
+ dpcon@0 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ num_priorities = <0x2>;
+ };
+ dpcon@16 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ num_priorities = <0x2>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ dpseci@0 {
+ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
+ options = "DPSECI_OPT_HAS_CG";
+ };
+
+ /* ------------ DPRTC --------------*/
+ dprtc@0 {
+ compatible="fsl,dprtc";
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ };
+};
--
2.37.2
patches/rcw-LSDK-21.08/0019-lx2160acex7-serdes-protocol-0-explicitly-set-REF_CLK.patch 0 → 100644
View file @ 980b23ae
From 7aaf85062729e4242f7229572fd3b03f8c3d5ae6 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 14 Aug 2022 16:20:21 +0300
Subject: [PATCH 19/20] lx2160acex7: serdes protocol 0: explicitly set
REF_CLK_SEL to 0 as per RM
---
lx2160acex7/configs/lx2160a_SD1_0.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD2_0.rcwi | 1 +
2 files changed, 2 insertions(+)
diff --git a/lx2160acex7/configs/lx2160a_SD1_0.rcwi b/lx2160acex7/configs/lx2160a_SD1_0.rcwi
index 8a2dd84..0037abf 100644
--- a/lx2160acex7/configs/lx2160a_SD1_0.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_0.rcwi
@@ -1,3 +1,4 @@
SRDS_PRTCL_S1=0
SRDS_PLL_PD_PLL1=1
SRDS_PLL_PD_PLL2=1
+SRDS_PLL_REF_CLK_SEL_S1=0
diff --git a/lx2160acex7/configs/lx2160a_SD2_0.rcwi b/lx2160acex7/configs/lx2160a_SD2_0.rcwi
index a1215d2..5de0f65 100644
--- a/lx2160acex7/configs/lx2160a_SD2_0.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD2_0.rcwi
@@ -1,3 +1,4 @@
SRDS_PRTCL_S2=0
SRDS_PLL_PD_PLL3=1
SRDS_PLL_PD_PLL4=1
+SRDS_PLL_REF_CLK_SEL_S2=0
--
2.37.2
patches/rcw-LSDK-21.08/0020-lx2160acex7-add-configuration-for-SD1-10S-SD2-4.patch 0 → 100644
View file @ 980b23ae
From b35087f96d4983d932cd592a80d097ec26d1eb00 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 21 Aug 2022 12:28:41 +0300
Subject: [PATCH 20/20] lx2160acex7: add configuration for SD1: 10S, SD2: 4
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_10S.rcwi | 2 ++
lx2160acex7/configs/lx2160a_SD2_4.rcwi | 2 ++
2 files changed, 4 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_10S.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD2_4.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_10S.rcwi b/lx2160acex7/configs/lx2160a_SD1_10S.rcwi
new file mode 100644
index 0000000..a5a1014
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_10S.rcwi
@@ -0,0 +1,2 @@
+SRDS_PRTCL_S1=10
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_SD2_4.rcwi b/lx2160acex7/configs/lx2160a_SD2_4.rcwi
new file mode 100644
index 0000000..a0b4cc7
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_4.rcwi
@@ -0,0 +1,2 @@
+SRDS_PRTCL_S2=4
+SRDS_PLL_REF_CLK_SEL_S2=0
--
2.37.2
runme.sh
View file @ 980b23ae
...@@ -73,6 +73,10 @@ case "${SERDES}" in ...@@ -73,6 +73,10 @@ case "${SERDES}" in
DPC=dpc-8_x_usxgmii.dtb DPC=dpc-8_x_usxgmii.dtb
DPL=dpl-eth.8x10g.19.dtb DPL=dpl-eth.8x10g.19.dtb
;; ;;
10S_*)
DPC=dpc-S1_10-S2_0-6x_usxgmii.dtb
DPL=dpl-S1_10-S2_0-6x_eth.dtb
;;
13_*) 13_*)
DPC=dpc-dual-100g.dtb DPC=dpc-dual-100g.dtb
DPL=dpl-eth.dual-100g.19.dtb DPL=dpl-eth.dual-100g.19.dtb
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7