Added LSDK-20.12 support and other enhancements / fixes

1. Added support for LSDK-20.12
2. Added initial support for secure boot; there are few atf patches that
will be added later
3. Fixed documentation in README.md withregards SPI flashing to use
cmp.b instead of cmp (the size is given in bytes)
4. Added ATF debug/release build environment variable
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>

README.md

@@ -53,7 +53,7 @@ For SD card bootable images, plug in a micro SD into your machine and run the fo
 
 For SPI boot, boot thru SD card and then load the _xspi_ images to system memory and flash it using the `sf probe` and `sf update` commands. An example below loads the image through TFTP prototocl, flashes and then verifies the image -
 
-`sf probe; setenv ipaddr 192.168.15.223; setenv serverip 192.168.15.3; tftp 0xa0000000 lx2160acex7_xspi_2000_700_2600_8_5_2_xspi.img;sf update 0xa0000000 0 $filesize; sf read 0xa4000000 0 $filesize; cmp 0xa0000000 0xa4000000 $filesize`
+`sf probe; setenv ipaddr 192.168.15.223; setenv serverip 192.168.15.3; tftp 0xa0000000 lx2160acex7_xspi_2000_700_2600_8_5_2_xspi.img;sf update 0xa0000000 0 $filesize; sf read 0xa4000000 0 $filesize; cmp.b 0xa0000000 0xa4000000 $filesize`
 
 And then set boot DIP switch on COM to off/off/off/off from numbers 1 to 4 (dip number 5 is not used. Notice the marking 'ON' on the DIP switch)
 

patches/linux-LSDK-20.12/0001-arm64-dts-lx2160a-add-lx2160acex7-device-tree-build.patch

+From 9adba7be66753c3d8edce52c2d0afb0d6328ec03 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 7 Jan 2021 17:03:59 +0200
+Subject: [PATCH] arm64: dts: lx2160a: add lx2160acex7 device tree build
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index c3880d663..4aed43ff4 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex7.dtb
+ 
+ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \
+ 			  imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0002-arm64-dts-lx2160a-add-lx2160acex7-device-tree.patch

+From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 14:21:06 +0300
+Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
+
+The device tree enables the following features -
+1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
+2. 2x MDIO busses
+3. 2x USB 3.0 controllers
+4. 4x SATA ports
+5. MT35X 512Mb SPI flash
+6. Temperature sensor on i2c0 channel 3
+7. AMC6821 temperature and PWM fan controller
+
+The module supports AMC6821 and EMC2301 PWM controllers where either can
+be assembled, but not both together since the PWM and TACH signals are
+shared between them.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-cex7.dts   | 190 ++++++++++++++++++
+ 1 file changed, 190 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 000000000000..872fcf9e724d
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A-CEx7
++//
++// Copyright 2019 SolidRun ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++	model = "SolidRun LX2160A COM express type 7 module";
++	compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
++
++	aliases {
++		crypto = &crypto;
++		serial0 = &uart0;
++		serial1 = &uart1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	sb_3v3: regulator-sb3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "RT7290";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&crypto {
++	status = "okay";
++};
++
++&esdhc0 {
++	sd-uhs-sdr104;
++	sd-uhs-sdr50;
++	sd-uhs-sdr25;
++	sd-uhs-sdr12;
++	status = "okay";
++};
++
++&esdhc1 {
++	mmc-hs200-1_8v;
++	mmc-hs400-1_8v;
++	bus-width = <8>;
++	status = "okay";
++};
++
++
++/*
++i2c busses are -
++/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
++/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
++/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
++
++I2C switch -
++/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
++/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
++/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
++/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
++/dev/i2c7 - CH4 - SFP #0 I2C
++/dev/i2c8 - CH5 - SFP #1 I2C
++/dev/i2c9 - CH6 - SFP #2 I2C
++/dev/i2c10 - CH7 - SFP #3 I2C
++
++
++*/
++
++
++
++&i2c0 {
++	status = "okay";
++
++	i2c-mux@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@1 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x1>;
++			fan-temperature-ctrlr@18 {
++				compatible = "ti,amc6821";
++				reg = <0x18>;
++				cooling-min-state = <0>;
++				cooling-max-state = <9>;
++				#cooling-cells = <2>;
++			};
++		};
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			temperature-sensor@48 {
++				compatible = "nxp,sa56004";
++				reg = <0x48>;
++				vcc-supply = <&sb_3v3>;
++			};
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++
++	rtc@51 {
++		compatible = "nxp,pcf2129";
++		reg = <0x51>;
++		// IRQ10_B
++		interrupts = <0 150 0x4>;
++	};
++};
++
++&fspi {
++	status = "okay";
++	flash0: mt35xu512aba@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "micron,m25p80";
++		m25p,fast-read;
++		spi-max-frequency = <50000000>;
++		reg = <0>;
++		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++		spi-rx-bus-width = <8>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
++
++&emdio1 {
++	status = "okay";
++	rgmii_phy1: ethernet-phy@1 {
++		/* AR8035 PHY - "compatible" property not strictly needed */
++		compatible = "ethernet-phy-id004d.d072";
++		reg = <0x1>;
++		/* Poll mode - no "interrupts" property defined */
++	};
++};
++
++&emdio2 {
++	status = "okay";
++};
++
++&dpmac17 {
++	phy-handle = <&rgmii_phy1>;
++	phy-connection-type = "rgmii-id";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&sata2 {
++	status = "okay";
++};
++
++&sata3 {
++	status = "okay";
++};
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0005-arm64-dts-lx2160a-cex7-add-ltc3882-support.patch

+From cca2439ac83136b9ed85f8519931018d4f5385e6 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 12 Jan 2020 14:24:47 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add ltc3882 support
+
+ltc3882 is lx2 cortex-a72 core voltage.
+this patch adds it to the device tree support; the driver is in
+drivers/hwmon/pmbus/ltc2978.c
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 872fcf9e724d..1c1a0d47897d 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -94,6 +94,15 @@ I2C switch -
+ 				#cooling-cells = <2>;
+ 			};
+ 		};
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++			ltc3882@5c {
++				compatible = "ltc3882";
++				reg = <0x5c>;
++			};
++		};
+ 		i2c@3 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0006-arm64-dts-lx2160a-cex7-add-on-module-eeproms.patch

+From 05acb6ecc8eb7426c4664a1e8fd22ad69256d541 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 26 Jan 2020 15:36:07 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add on-module eeproms
+
+This patch adds 4 eeprom support on i2c mux channel #0 -
+1. Bootable 512Kbit eeprom at address 0x50.
+2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53.
+3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing
+data.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-cex7.dts   | 22 ++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 1c1a0d47897d..2b8f1118b37a 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -81,7 +81,27 @@ I2C switch -
+ 		reg = <0x77>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-
++		i2c@0 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0>;
++			24aa512@50 {
++				compatible = "atmel,24c512";
++				reg = <0x50>;
++			};
++			spd1@51 {
++				compatible = "atmel,spd";
++				reg = <0x51>;
++			};
++			spd2@53 {
++				compatible = "atmel,spd";
++				reg = <0x53>;
++			};
++			m24c02@57 {
++				compatible = "atmel,24c02";
++				reg = <0x57>;
++			};
++		};
+ 		i2c@1 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0009-usb-dwc3-core-add-support-for-disabling-SS-instances.patch

+From 2ce0d3a0c1e218d6e680115da21a0e9c180db845 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 28 Oct 2020 20:06:16 +0200
+Subject: [PATCH] usb: dwc3: core: add support for disabling SS instances in
+ park mode
+
+This is a backport from mainline -
+commit 7ba6b09fda5e0cb741ee56f3264665e0edc64822
+Author: Neil Armstrong <narmstrong@baylibre.com>
+Date:   Fri Feb 21 10:15:31 2020 +0100
+
+   In certain circumstances, the XHCI SuperSpeed instance in park mode
+    can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high
+    load on the single XHCI SuperSpeed instance, the controller can crash like:
+     xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
+     xhci-hcd xhci-hcd.0.auto: Host halt failed, -110
+     xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead
+     xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
+     hub 2-1.1:1.0: hub_ext_port_status failed (err = -22)
+     xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
+     usb 2-1.1-port1: cannot reset (err = -22)
+
+    Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates
+    the issue. The bit is described as :
+    "When this bit is set to '1' all SS bus instances in park mode are disabled"
+
+    Synopsys explains:
+    The GUCTL1.PARKMODE_DISABLE_SS is only available in
+    dwc_usb3 controller running in host mode.
+    This should not be set for other IPs.
+    This can be disabled by default based on IP, but I recommend to have a
+    property to enable this feature for devices that need this.
+
+    CC: Dongjin Kim <tobetter@gmail.com>
+    Cc: Jianxin Pan <jianxin.pan@amlogic.com>
+    Cc: Thinh Nguyen <thinhn@synopsys.com>
+    Cc: Jun Li <lijun.kernel@gmail.com>
+    Reported-by: Tim <elatllat@gmail.com>
+    Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+    Signed-off-by: Felipe Balbi <balbi@kernel.org>
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
+ drivers/usb/dwc3/core.c                        | 5 +++++
+ drivers/usb/dwc3/core.h                        | 4 ++++
+ 3 files changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+index fe9b8bf4d..201bc2292 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+@@ -994,6 +994,7 @@
+ 			snps,dis_rxdet_inp3_quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ 			snps,host-vbus-glitches;
++			snps,parkmode-disable-ss-quirk;
+ 			dma-coherent;
+ 			status = "disabled";
+ 		};
+@@ -1009,6 +1010,7 @@
+ 			snps,dis_rxdet_inp3_quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ 			snps,host-vbus-glitches;
++			snps,parkmode-disable-ss-quirk;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 5ed5a57f3..870f9cb14 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1064,6 +1064,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
+ 		if (dwc->dis_tx_ipgap_linecheck_quirk)
+ 			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
+ 
++		if (dwc->parkmode_disable_ss_quirk)
++			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
++
+ 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+ 	}
+ 
+@@ -1400,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
+ 				"snps,dis-del-phy-power-chg-quirk");
+ 	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
+ 				"snps,dis-tx-ipgap-linecheck-quirk");
++	dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
++				"snps,parkmode-disable-ss-quirk");
+ 
+ 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
+ 				"snps,tx_de_emphasis_quirk");
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+index 1ea3c50d2..63f0b5fb3 100644
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -266,6 +266,7 @@
+ #define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
+ 
+ /* Global User Control 1 Register */
++#define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
+ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+ #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
+@@ -1041,6 +1042,8 @@ struct dwc3_scratchpad_array {
+  *			change quirk.
+  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
+  *			check during HS transmit.
++ * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
++ *			instances in park mode.
+  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
+  * @tx_de_emphasis: Tx de-emphasis value
+  * 	0	- -6dB de-emphasis
+@@ -1236,6 +1239,7 @@ struct dwc3 {
+ 	unsigned		dis_u2_freeclk_exists_quirk:1;
+ 	unsigned		dis_del_phy_power_chg_quirk:1;
+ 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
++	unsigned		parkmode_disable_ss_quirk:1;
+ 
+ 	unsigned		tx_de_emphasis_quirk:1;
+ 	unsigned		tx_de_emphasis:2;
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0010-arm64-dts-lx2160a-cex7-add-power-button-support.patch

+From b640a74851bf1fdc3abe49860e9efc498e4483a8 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 8 Dec 2020 13:21:03 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add power button support
+
+COM express PWRBTN# signal is connected as a GPIO to the LX2 SoC.
+Translate that power button click as KEY_POWER event.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 2b8f1118b..e2dfe4f67 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -7,6 +7,7 @@
+ /dts-v1/;
+ 
+ #include "fsl-lx2160a.dtsi"
++#include <dt-bindings/input/linux-event-codes.h>
+ 
+ / {
+ 	model = "SolidRun LX2160A COM express type 7 module";
+@@ -30,6 +31,17 @@
+ 		regulator-boot-on;
+ 		regulator-always-on;
+ 	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key {
++			label = "power";
++			linux,can-disable;
++			linux,code = <KEY_POWER>;
++			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
++		};
++	};
+ };
+ 
+ &crypto {
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0011-aarm64-dts-lx2160a-cex7-add-secondary-spi-flash-supp.patch

+From 08ff0cc811d9e4616aad53b39e528544b0979fd7 Mon Sep 17 00:00:00 2001
+From: yazan shhady <yazan.shhady@solid-run.com>
+Date: Sun, 22 Nov 2020 14:44:32 +0200
+Subject: [PATCH] aarm64: dts: lx2160a-cex7: add secondary spi flash support
+
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 2b8f1118b37a..6f031412400a 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -165,6 +165,16 @@ I2C switch -
+ 		spi-rx-bus-width = <8>;
+ 		spi-tx-bus-width = <1>;
+ 	};
++	flash1: w25q32@1 {
++                #address-cells = <1>;
++                #size-cells = <1>;
++                compatible = "st,w25q32";
++                spi-max-frequency = <10000000>;
++                reg = <1>;
++                spi-rx-bus-width = <1>;
++                spi-tx-bus-width = <1>;
++        };
++
+ };
+ 
+ &uart0 {
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0001-lx2160acex7-misc-RCW-files.patch

+From ef5ab1b5a7262a6ef9caf334b0c772b0ebf00fdf Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 14:43:06 +0300
+Subject: [PATCH] lx2160acex7 misc RCW files
+
+This patch adds support for lx2160a rcw project.
+In general RCW has lots of redundent files and can be restructured
+better as in this patch.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/Makefile                          |  2 +
+ lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig  | 61 +++++++++++++++++++
+ .../rcw_1900_600_2600_17_4_2.rcw              |  4 ++
+ .../rcw_1900_600_2600_17_4_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_2400_13_5_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_2400_20_5_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_2400_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2000_700_2600_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2000_700_2900_17_4_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_2900_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2000_700_3200_17_4_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_3200_20_5_2_sd.rcw           |  4 ++
+ .../rcw_2000_700_3200_8_5_0_sd.rcw            |  4 ++
+ .../rcw_2000_700_3200_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2000_700_3200_8_5_2_xspi.rcw          |  4 ++
+ .../rcw_2400_700_3200_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2500_700_3200_8_5_2_sd.rcw            |  4 ++
+ .../rcw_2600_700_3200_8_5_2_sd.rcw            |  4 ++
+ .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw   |  4 ++
+ lx2160acex7/configs/lx2160a_13_5_2.rcwi       |  3 +
+ lx2160acex7/configs/lx2160a_17_4_2.rcwi       |  7 +++
+ .../configs/lx2160a_1900_600_2600.rcwi        | 12 ++++
+ .../configs/lx2160a_2000_700_2400.rcwi        | 12 ++++
+ .../configs/lx2160a_2000_700_2600.rcwi        | 12 ++++
+ .../configs/lx2160a_2000_700_2900.rcwi        | 12 ++++
+ .../configs/lx2160a_2000_700_3200.rcwi        | 12 ++++
+ lx2160acex7/configs/lx2160a_20_5_2.rcwi       |  7 +++
+ .../configs/lx2160a_2400_700_3200.rcwi        | 12 ++++
+ .../configs/lx2160a_2500_700_3200.rcwi        | 12 ++++
+ .../configs/lx2160a_2600_700_3200.rcwi        | 12 ++++
+ lx2160acex7/configs/lx2160a_8_5_0.rcwi        |  7 +++
+ lx2160acex7/configs/lx2160a_8_5_2.rcwi        |  7 +++
+ lx2160acex7/configs/lx2160a_defaults.rcwi     | 19 ++++++
+ lx2160acex7/configs/lx2160a_sdboot.rcwi       | 20 ++++++
+ lx2160acex7/configs/lx2160a_test.rcwi         | 20 ++++++
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi     | 17 ++++++
+ 36 files changed, 334 insertions(+)
+ create mode 100644 lx2160acex7/Makefile
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+ create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+ create mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_20_5_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_8_5_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_defaults.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_sdboot.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_test.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_xspiboot.rcwi
+
+diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile
+new file mode 100644
+index 0000000..d7e9447
+--- /dev/null
++++ b/lx2160acex7/Makefile
+@@ -0,0 +1,2 @@
++include ../Makefile.inc
++
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+new file mode 100644
+index 0000000..cdb6446
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+@@ -0,0 +1,61 @@
++/*
++ * SerDes Protocol 1 -  19
++ * SerDes Protocol 2 -  5
++ * SerDes Protocol 3 -  2
++ *
++ * Frequencies:
++ * Core     -- 1900 MHz
++ * Platform -- 600  MHz
++ * DDR      -- 2600 MT/s
++ */
++
++#include <../lx2160asi/lx2160a.rcwi>
++
++SYS_PLL_RAT=12
++MEM_PLL_CFG=3
++MEM_PLL_RAT=26
++MEM2_PLL_CFG=3
++MEM2_PLL_RAT=26
++CGA_PLL1_RAT=19
++CGA_PLL2_RAT=19
++CGB_PLL1_RAT=19
++CGB_PLL2_RAT=9
++C5_PLL_SEL=0
++C6_PLL_SEL=0
++C7_PLL_SEL=0
++C8_PLL_SEL=0
++HWA_CGA_M1_CLK_SEL=1
++HWA_CGB_M1_CLK_SEL=7
++BOOT_LOC=26
++SYSCLK_FREQ=600
++IIC2_PMUX=6
++IIC3_PMUX=2
++IIC4_PMUX=2
++USB3_CLK_FSEL=39
++SRDS_PRTCL_S1=19
++SRDS_PRTCL_S2=5
++SRDS_PRTCL_S3=2
++SRDS_PLL_REF_CLK_SEL_S1=2
++SRDS_DIV_PEX_S1=1
++SRDS_DIV_PEX_S2=3
++SRDS_DIV_PEX_S3=1
++
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* Copy SPL Uboot to Ocram */
++.pbi
++blockcopy 0x08,0x00100000,0x1800a000,0x00020000
++.end
++
++/* Boot Location Pointer */
++#include <../lx2160asi/bootlocptr_sd.rcw>
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_24.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+new file mode 100644
+index 0000000..13ab0b9
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_1900_600_2600.rcwi>
++#include <configs/lx2160a_17_4_2.rcwi>
++#include <configs/lx2160a_xspiboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+new file mode 100644
+index 0000000..14fae8c
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_1900_600_2600.rcwi>
++#include <configs/lx2160a_17_4_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+new file mode 100644
+index 0000000..2dae5a2
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2400.rcwi>
++#include <configs/lx2160a_13_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+new file mode 100644
+index 0000000..5335072
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2400.rcwi>
++#include <configs/lx2160a_20_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..e2a5bd3
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2400.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..a330bfe
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2600.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+new file mode 100644
+index 0000000..8535dbd
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2900.rcwi>
++#include <configs/lx2160a_17_4_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..698be01
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_2900.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+new file mode 100644
+index 0000000..780d8c3
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_3200.rcwi>
++#include <configs/lx2160a_17_4_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+new file mode 100644
+index 0000000..eb9d240
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_3200.rcwi>
++#include <configs/lx2160a_20_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+new file mode 100644
+index 0000000..ceb53a3
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_3200.rcwi>
++#include <configs/lx2160a_8_5_0.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..a220e98
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_3200.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..1eabd7d
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2000_700_3200.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_xspiboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..2ac59b1
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2400_700_3200.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..e7c08df
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2500_700_3200.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+new file mode 100644
+index 0000000..1e7a8f7
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_2600_700_3200.rcwi>
++#include <configs/lx2160a_8_5_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+new file mode 100644
+index 0000000..86f12f8
+--- /dev/null
++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+@@ -0,0 +1,4 @@
++#include <configs/lx2160a_defaults.rcwi>
++#include <configs/lx2160a_test.rcwi>
++#include <configs/lx2160a_17_4_2.rcwi>
++#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+new file mode 100644
+index 0000000..76f44bc
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=13
++SRDS_PRTCL_S2=5
++SRDS_PRTCL_S3=2
+diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+new file mode 100644
+index 0000000..358972d
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+@@ -0,0 +1,7 @@
++SRDS_PRTCL_S1=17
++SRDS_PRTCL_S2=4
++SRDS_PRTCL_S3=2
++
++/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
++/*SRDS_PLL_REF_CLK_SEL_S1=2*/
++
+diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+new file mode 100644
+index 0000000..8b61021
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=19
++CGA_PLL2_RAT=19
++CGB_PLL1_RAT=19
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=12
++
++MEM_PLL_RAT=26
++MEM2_PLL_RAT=26
++
++/* Modify FlexSPI Clock Divisor value */
++/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+new file mode 100644
+index 0000000..6b0b150
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=24
++MEM2_PLL_RAT=24
++
++/* Modify FlexSPI Clock Divisor value */
++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+new file mode 100644
+index 0000000..21dce67
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=26
++MEM2_PLL_RAT=26
++
++/* Modify FlexSPI Clock Divisor value */
++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+new file mode 100644
+index 0000000..e6a8e30
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=29
++MEM2_PLL_RAT=29
++
++/* Modify FlexSPI Clock Divisor value */
++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+new file mode 100644
+index 0000000..27ee377
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_20_5_2.rcwi
+new file mode 100644
+index 0000000..c2c7bea
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_20_5_2.rcwi
+@@ -0,0 +1,7 @@
++SRDS_PRTCL_S1=20
++SRDS_PRTCL_S2=5
++SRDS_PRTCL_S3=2
++
++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
++SRDS_PLL_REF_CLK_SEL_S1=2
++SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+new file mode 100644
+index 0000000..fc0fd6c
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=24
++CGA_PLL2_RAT=24
++CGB_PLL1_RAT=24
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+new file mode 100644
+index 0000000..62d9069
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=25
++CGA_PLL2_RAT=25
++CGB_PLL1_RAT=25
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+new file mode 100644
+index 0000000..e244917
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+@@ -0,0 +1,12 @@
++CGA_PLL1_RAT=26
++CGA_PLL2_RAT=26
++CGB_PLL1_RAT=26
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=14
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+new file mode 100644
+index 0000000..62ff153
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+@@ -0,0 +1,7 @@
++SRDS_PRTCL_S1=8 /* should be 8 */
++SRDS_PRTCL_S2=5
++SRDS_PRTCL_S3=0
++
++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
++SRDS_PLL_REF_CLK_SEL_S1=2
++SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_8_5_2.rcwi
+new file mode 100644
+index 0000000..d7d707a
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_8_5_2.rcwi
+@@ -0,0 +1,7 @@
++SRDS_PRTCL_S1=8 /* should be 8 */
++SRDS_PRTCL_S2=5
++SRDS_PRTCL_S3=2
++
++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
++SRDS_PLL_REF_CLK_SEL_S1=2
++SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+new file mode 100644
+index 0000000..6fd65ec
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -0,0 +1,19 @@
++#include <../lx2160asi/lx2160a.rcwi>
++MEM_PLL_CFG=3
++MEM2_PLL_CFG=3
++C5_PLL_SEL=0
++C6_PLL_SEL=0
++C7_PLL_SEL=0
++C8_PLL_SEL=0
++HWA_CGA_M1_CLK_SEL=1
++HWA_CGB_M1_CLK_SEL=7
++BOOT_LOC=26
++SYSCLK_FREQ=600
++IIC2_PMUX=6
++IIC3_PMUX=0
++IIC4_PMUX=2
++USB3_CLK_FSEL=39
++SRDS_DIV_PEX_S1=1
++SRDS_DIV_PEX_S2=3
++SRDS_DIV_PEX_S3=1
++
+diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+new file mode 100644
+index 0000000..d537ea5
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+@@ -0,0 +1,20 @@
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* Copy SPL Uboot to Ocram */
++.pbi
++blockcopy 0x08,0x00100000,0x1800a000,0x00020000
++.end
++
++/* Boot Location Pointer */
++#include <../lx2160asi/bootlocptr_sd.rcw>
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++/* Errata for PCIe controller */
++#include <../lx2160asi/a011270.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
+diff --git a/lx2160acex7/configs/lx2160a_test.rcwi b/lx2160acex7/configs/lx2160a_test.rcwi
+new file mode 100644
+index 0000000..a223be1
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_test.rcwi
+@@ -0,0 +1,20 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=8
++
++SYS_PLL_RAT=12
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
++
++/* Modify FlexSPI Clock Divisor value */
++/* #include <../lx2160asi/flexspi_divisor_24.rcw> */
++
++SRDS_PLL_PD_PLL1=1
++SRDS_PLL_PD_PLL2=1
++SRDS_PLL_PD_PLL3=1
++SRDS_PLL_PD_PLL4=1
++SRDS_PLL_PD_PLL5=1
++SRDS_PLL_PD_PLL6=1
++
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+new file mode 100644
+index 0000000..eecc314
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -0,0 +1,17 @@
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* Boot Location Pointer */
++#include <../lx2160asi/bootlocptr_nor.rcw>
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++/* Errata for PCIe controller */
++#include <../lx2160asi/a011270.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
++/* Modify FlexSPI Clock Divisor value */
++#include <../lx2160asi/flexspi_divisor_24.rcw>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0002-Set-io-pads-as-GPIO.patch

+From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 30 Oct 2019 11:43:37 +0200
+Subject: [PATCH 2/2] Set io pads as GPIO
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 6fd65ec..dbc843f 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+ SYSCLK_FREQ=600
+-IIC2_PMUX=6
++IIC2_PMUX=1
+ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+ SRDS_DIV_PEX_S1=1
+ SRDS_DIV_PEX_S2=3
+ SRDS_DIV_PEX_S3=1
+-
++SDHC1_DIR_PMUX=1
++IRQ03_00_PMUX=1
++IRQ07_04_PMUX=1
++IRQ11_08_PMUX=1
++EVT20_PMUX=1
++EVT43_PMUX=1
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch

+From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 5 Nov 2019 10:35:32 +0200
+Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28
+
+Serdes group 2 enable PCIe gen 3
+XSPI increase divisor to 28 - this fixes UEFI SPI flash detection.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index dbc843f..3ea7683 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -14,7 +14,7 @@ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+ SRDS_DIV_PEX_S1=1
+-SRDS_DIV_PEX_S2=3
++SRDS_DIV_PEX_S2=1
+ SRDS_DIV_PEX_S3=1
+ SDHC1_DIR_PMUX=1
+ IRQ03_00_PMUX=1
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index eecc314..28310c9 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -14,4 +14,4 @@
+ #include <../lx2160asi/common.rcw>
+ 
+ /* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_24.rcw>
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0004-refactor-a009531-a008851-and-a011270.patch

+From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:16:13 +0200
+Subject: [PATCH 4/4] refactor a009531, a008851 and a011270
+
+1. Add 'load conditional', 'jump condidional' and 'jump' to PBI
+instructions.
+2. Use SVR register to execute the PCIe workarounds on the relevant rev
+of the device.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++
+ lx2160asi/a011270.rcw         |  6 +++
+ rcw.py                        | 28 ++++++++++
+ 3 files changed, 130 insertions(+)
+ create mode 100644 lx2160asi/a009531_a008851.rcw
+
+diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw
+new file mode 100644
+index 0000000..0eb7051
+--- /dev/null
++++ b/lx2160asi/a009531_a008851.rcw
+@@ -0,0 +1,96 @@
++/*
++ * Work-around for erratum A-009531
++ *
++ * Description:
++ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO)
++ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer
++ * is permitted to set IDO only if the IDO Completion Enable bit in the Device
++ * Control 2 Register is set. It is not required to copy the value of IDO from
++ * the Request into the Completion(s) for that Request".
++ *
++ * However, the PCI Express controller as the completer sets the IDO bit in the
++ * completion packet header, in response to non-posted requests (memory read) with
++ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the
++ * Device Control 2 Register is not set.
++ *
++ * Impact:
++ * The PCI Express controller as the completer sends completion packets with IDO
++ * bit set in packet header even when the IDO Completion Enable bit is cleared in
++ * the controller’s Device Control 2 Register.
++ * Applicable for SNP PCIe controller
++ */
++
++/*
++ * Work-around for erratum A-008851
++ *
++ * Invalid transmitter/receiver preset values are used in Gen3 equalization
++ * phases during link training for RC mode
++ * This errata is valid only for PCI gen3.
++ * Workaround:
++ *  write 0x00000001 to MISC_CONTROL_1_OFF
++ *  write 0x4747 to Lane Equalization Control register for each lane
++ * Applicable for SNP PCIe controller
++ */
++
++.pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++
++/* If it is rev 2, skip the following jump command */
++jumpc 0x00000014,0x00000020
++
++/* Jump all the below instructions */
++jump 0x190 /* All instruction below including the jump are 0x190 bytes */
++
++loadc 0x01ea1080,0x70000000
++jumpc 0x00000034,0x00000000 
++write 0x03400098,0x00000000
++write 0x034008bc,0x00000001
++write 0x03400154,0x47474747
++write 0x03400158,0x47474747
++write 0x034008bc,0x00000000
++
++loadc 0x01ea1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03500098,0x00000000
++write 0x035008bc,0x00000001
++write 0x03500154,0x47474747
++write 0x03500158,0x47474747
++write 0x035008bc,0x00000000
++
++loadc 0x01eb1080,0x70000000
++jumpc 0x00000044,0x00000000 
++write 0x03600098,0x00000000
++write 0x036008bc,0x00000001
++write 0x03600164,0x47474747
++write 0x03600168,0x47474747
++write 0x0360016c,0x47474747
++write 0x03600170,0x47474747
++write 0x036008bc,0x00000000
++
++loadc 0x01eb1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03700098,0x00000000
++write 0x037008bc,0x00000001
++write 0x03700154,0x47474747
++write 0x03700158,0x47474747
++write 0x037008bc,0x00000000
++
++loadc 0x01ec1080,0x70000000
++jumpc 0x00000044,0x00000000 
++write 0x03800098,0x00000000
++write 0x038008bc,0x00000001
++write 0x03800164,0x47474747
++write 0x03800168,0x47474747
++write 0x0380016c,0x47474747
++write 0x03800170,0x47474747
++write 0x038008bc,0x00000000
++
++loadc 0x01ec1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03900098,0x00000000
++write 0x039008bc,0x00000001
++write 0x03900154,0x47474747
++write 0x03900158,0x47474747
++write 0x039008bc,0x00000000
++.end
+diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw
+index 0dc774d..5bd5558 100644
+--- a/lx2160asi/a011270.rcw
++++ b/lx2160asi/a011270.rcw
+@@ -4,6 +4,12 @@
+  */
+ 
+ .pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++/* If it is rev 1, skip the following jump command */
++jumpc 0x00000014,0x00000010
++/* Skip the following instructions by jumping to the end */
++jump  0x38
+ write 0x03400688,0x00000001
+ write 0x03500688,0x00000001
+ write 0x03600688,0x00000001
+diff --git a/rcw.py b/rcw.py
+index 863f755..c2d06f6 100755
+--- a/rcw.py
++++ b/rcw.py
+@@ -328,6 +328,34 @@ def build_pbi(lines):
+             v2 = struct.pack(endianess + 'L', p2)
+             subsection += v1
+             subsection += v2
++        elif op == 'loadc':
++            if p1 == None or p2 == None:
++                print('Error: "loadc" instruction requires two parameters')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80140000)
++            v2 = struct.pack(endianess + 'L', p1)
++            v3 = struct.pack(endianess + 'L', p2)
++            subsection += v1
++            subsection += v2
++            subsection += v3
++        elif op == 'jumpc':
++            if p1 == None or p2 == None:
++                print('Error: "jumpc" instruction requires two parameters')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80850000)
++            v2 = struct.pack(endianess + 'L', p1)
++            v3 = struct.pack(endianess + 'L', p2)
++            subsection += v1
++            subsection += v2
++            subsection += v3
++        elif op == 'jump':
++            if p1 == None:
++                print('Error: "jump" instruction requires a parameter')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80840000)
++            v2 = struct.pack(endianess + 'L', p1)
++            subsection += v1
++            subsection += v2
+         elif op == 'awrite':
+             if p1 == None or p2 == None:
+                 print('Error: "awrite" instruction requires two parameters')
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch

+From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:35:04 +0200
+Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160asi/a050234.rcw | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw
+index 72a40e4..2130709 100644
+--- a/lx2160asi/a050234.rcw
++++ b/lx2160asi/a050234.rcw
+@@ -4,6 +4,12 @@
+  */
+ 
+ .pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++/* If it is rev 1, skip the following jump command */
++jumpc 0x00000014,0x00000010
++/* Skip the following instructions by jumping to the end */
++jump  0xc8
+ write 0x1ea1200,0x20081004
+ write 0x1ea1240,0x20081004
+ write 0x1ea1280,0x20081004
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch

+From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:36:20 +0200
+Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed
+
+1. Moves calling the workarounds to the _defaults.rcwi
+2. Toggle fan-full-speed GPIO. The fan controller starts throttling when
+a driver exists (i.e. kernel); in order to avoid overheating until then
+enable full speed.
+3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox
+ConnectX-5 NICs
+4. Run a009531 and a00885 on rev2.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++----
+ lx2160acex7/configs/lx2160a_sdboot.rcwi   |  6 ------
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi |  6 ------
+ 3 files changed, 17 insertions(+), 16 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 3ea7683..7af1f5b 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -1,10 +1,6 @@
+ #include <../lx2160asi/lx2160a.rcwi>
+ MEM_PLL_CFG=3
+ MEM2_PLL_CFG=3
+-C5_PLL_SEL=0
+-C6_PLL_SEL=0
+-C7_PLL_SEL=0
+-C8_PLL_SEL=0
+ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1
+ IRQ11_08_PMUX=1
+ EVT20_PMUX=1
+ EVT43_PMUX=1
++
++/* Drive the fan full speed pin */
++.pbi
++write 0x2320000,0x20000000
++.end
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++/* Errata for rev 1 PCIe controller */
++#include <../lx2160asi/a011270.rcw>
++
++/* Errata a050234 - fix elastic buffer threshold in rev 1 */
++#include <../lx2160asi/a050234.rcw>
++
++/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
++#include <../lx2160asi/a009531_a008851.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+index d537ea5..9086ffc 100644
+--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+ /* Boot Location Pointer */
+ #include <../lx2160asi/bootlocptr_sd.rcw>
+ 
+-/* Errata for SATA controller */
+-#include <../lx2160asi/a010554.rcw>
+-
+-/* Errata for PCIe controller */
+-#include <../lx2160asi/a011270.rcw>
+-
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index 28310c9..fa092c9 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -4,12 +4,6 @@
+ /* Boot Location Pointer */
+ #include <../lx2160asi/bootlocptr_nor.rcw>
+ 
+-/* Errata for SATA controller */
+-#include <../lx2160asi/a010554.rcw>
+-
+-/* Errata for PCIe controller */
+-#include <../lx2160asi/a011270.rcw>
+-
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0008-lx2160a-add-generic-bootloc-section.patch

+From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 24 Mar 2020 03:42:14 +0200
+Subject: [PATCH 8/8] lx2160a: add generic bootloc section
+
+The generic bootloc section does conditional blockcopy from SD/eMMC and
+SPI with some predefined addresses.
+Later on if ATF is used; those addresses are modified with ATF's
+create_pbl.c
+
+With this method a single boot image is unified for all the 3 different
+boot methods.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++
+ lx2160asi/bootlocptr.rcw                  | 62 +++++++++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 lx2160asi/bootlocptr.rcw
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 7af1f5b..7997d49 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -35,3 +35,15 @@ write 0x2320000,0x20000000
+ 
+ /* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
+ #include <../lx2160asi/a009531_a008851.rcw>
++
++/* Unified boot location copy */
++#include <../lx2160asi/bootlocptr.rcw>
++
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
++/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw
+new file mode 100644
+index 0000000..645182f
+--- /dev/null
++++ b/lx2160asi/bootlocptr.rcw
+@@ -0,0 +1,62 @@
++/*
++ * Generic code for auto booting.
++ * For each section blockcopy followed by write to bootlocl then bootloch must
++ * be followed in each section since when using ATF with create_pbl script in
++ * auto mode; it counts on the sequence of to be in that order.
++ */
++
++/* Boot from SD - copy SPL Uboot to Ocram */
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0x8 << 23 then skip the following jump command */
++jumpc 0x00000014,0x04000000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 40 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x08,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x1800a000
++write 0x01e00404,0x00000000
++.end
++
++/* Boot from eMMC - copy SPL Uboot to Ocram */
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0x9 << 23 then skip the following jump command */
++jumpc 0x00000014,0x04800000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 40 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x09,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x1800a000
++write 0x01e00404,0x00000000
++.end
++
++/* XSPI boot Location Pointer */
++/*
++ * Set the boot location pointer to the NOR flash boot area.
++ */
++
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0xf << 23 then skip the following jump command */
++jumpc 0x00000014,0x07800000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 0x190 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x0f,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x20100000
++write 0x01e00404,0x00000000
++.end
++
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0009-lx2160acex7-remove-all-predefined-RCW-files.patch

+From 151f650f383fc5ddd9c405cf96bc189c2eaf13bd Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 24 Mar 2020 03:51:28 +0200
+Subject: [PATCH 9/9] lx2160acex7: remove all predefined RCW files
+
+Remove all predefined RCW files and use on-the-fly created RCW from
+external script.
+For instance when using lx2160a_build repo; the runme.sh file creates
+lx2160acex7/RCW/template.rcw file the gets compiled.
+The creation is done using a simple bash script -
+
+cd $ROOTDIR/build/rcw/lx2160acex7
+mkdir -p RCW
+echo "#include <configs/lx2160a_defaults.rcwi>" > RCW/template.rcw
+echo "#include <configs/lx2160a_${SPEED}.rcwi>" >> RCW/template.rcw
+echo "#include <configs/lx2160a_${SERDES}.rcwi>" >> RCW/template.rcw
+make clean
+make -j${PARALLEL}
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig  | 61 -------------------
+ .../rcw_1900_600_2600_17_4_2.rcw              |  4 --
+ .../rcw_1900_600_2600_17_4_2_sd.rcw           |  4 --
+ .../rcw_2000_700_2400_13_5_2_sd.rcw           |  4 --
+ .../rcw_2000_700_2400_20_5_2_sd.rcw           |  4 --
+ .../rcw_2000_700_2400_8_5_2_sd.rcw            |  4 --
+ .../rcw_2000_700_2600_8_5_2_sd.rcw            |  4 --
+ .../rcw_2000_700_2900_17_4_2_sd.rcw           |  4 --
+ .../rcw_2000_700_2900_8_5_2_sd.rcw            |  4 --
+ .../rcw_2000_700_3200_17_4_2_sd.rcw           |  4 --
+ .../rcw_2000_700_3200_20_5_2_sd.rcw           |  4 --
+ .../rcw_2000_700_3200_8_5_0_sd.rcw            |  4 --
+ .../rcw_2000_700_3200_8_5_2_sd.rcw            |  4 --
+ .../rcw_2000_700_3200_8_5_2_xspi.rcw          |  4 --
+ .../rcw_2400_700_3200_8_5_2_sd.rcw            |  4 --
+ .../rcw_2500_700_3200_8_5_2_sd.rcw            |  4 --
+ .../rcw_2600_700_3200_8_5_2_sd.rcw            |  4 --
+ .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw   |  4 --
+ 18 files changed, 129 deletions(-)
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+ delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+deleted file mode 100644
+index cdb6446..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
++++ /dev/null
+@@ -1,61 +0,0 @@
+-/*
+- * SerDes Protocol 1 -  19
+- * SerDes Protocol 2 -  5
+- * SerDes Protocol 3 -  2
+- *
+- * Frequencies:
+- * Core     -- 1900 MHz
+- * Platform -- 600  MHz
+- * DDR      -- 2600 MT/s
+- */
+-
+-#include <../lx2160asi/lx2160a.rcwi>
+-
+-SYS_PLL_RAT=12
+-MEM_PLL_CFG=3
+-MEM_PLL_RAT=26
+-MEM2_PLL_CFG=3
+-MEM2_PLL_RAT=26
+-CGA_PLL1_RAT=19
+-CGA_PLL2_RAT=19
+-CGB_PLL1_RAT=19
+-CGB_PLL2_RAT=9
+-C5_PLL_SEL=0
+-C6_PLL_SEL=0
+-C7_PLL_SEL=0
+-C8_PLL_SEL=0
+-HWA_CGA_M1_CLK_SEL=1
+-HWA_CGB_M1_CLK_SEL=7
+-BOOT_LOC=26
+-SYSCLK_FREQ=600
+-IIC2_PMUX=6
+-IIC3_PMUX=2
+-IIC4_PMUX=2
+-USB3_CLK_FSEL=39
+-SRDS_PRTCL_S1=19
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+-SRDS_PLL_REF_CLK_SEL_S1=2
+-SRDS_DIV_PEX_S1=1
+-SRDS_DIV_PEX_S2=3
+-SRDS_DIV_PEX_S3=1
+-
+-/* Errata to write on scratch reg for validation */
+-#include <../lx2160asi/scratchrw1.rcw>
+-
+-/* Copy SPL Uboot to Ocram */
+-.pbi
+-blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+-.end
+-
+-/* Boot Location Pointer */
+-#include <../lx2160asi/bootlocptr_sd.rcw>
+-
+-/* Errata for SATA controller */
+-#include <../lx2160asi/a010554.rcw>
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_24.rcw>
+-
+-/* common PBI commands */
+-#include <../lx2160asi/common.rcw>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+deleted file mode 100644
+index 13ab0b9..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_1900_600_2600.rcwi>
+-#include <configs/lx2160a_17_4_2.rcwi>
+-#include <configs/lx2160a_xspiboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+deleted file mode 100644
+index 14fae8c..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_1900_600_2600.rcwi>
+-#include <configs/lx2160a_17_4_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+deleted file mode 100644
+index 2dae5a2..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2400.rcwi>
+-#include <configs/lx2160a_13_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+deleted file mode 100644
+index 5335072..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2400.rcwi>
+-#include <configs/lx2160a_20_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+deleted file mode 100644
+index e2a5bd3..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2400.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+deleted file mode 100644
+index a330bfe..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2600.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+deleted file mode 100644
+index 8535dbd..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2900.rcwi>
+-#include <configs/lx2160a_17_4_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+deleted file mode 100644
+index 698be01..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_2900.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+deleted file mode 100644
+index 780d8c3..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_3200.rcwi>
+-#include <configs/lx2160a_17_4_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+deleted file mode 100644
+index eb9d240..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_3200.rcwi>
+-#include <configs/lx2160a_20_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+deleted file mode 100644
+index ceb53a3..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_0.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+deleted file mode 100644
+index a220e98..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+deleted file mode 100644
+index 1eabd7d..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2000_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_xspiboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+deleted file mode 100644
+index 2ac59b1..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2400_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+deleted file mode 100644
+index e7c08df..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2500_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+deleted file mode 100644
+index 1e7a8f7..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_2600_700_3200.rcwi>
+-#include <configs/lx2160a_8_5_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+deleted file mode 100644
+index 86f12f8..0000000
+--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
++++ /dev/null
+@@ -1,4 +0,0 @@
+-#include <configs/lx2160a_defaults.rcwi>
+-#include <configs/lx2160a_test.rcwi>
+-#include <configs/lx2160a_17_4_2.rcwi>
+-#include <configs/lx2160a_sdboot.rcwi>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0010-lx2160acex7-remove-flexspi-divisor-optimization.patch

+From 4f1f779e2d0757ab1d328761c06dc09b9c6a3544 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 1 Sep 2020 12:39:31 +0300
+Subject: [PATCH 10/10] lx2160acex7: remove flexspi divisor optimization
+
+Keep the flexspi divisor as default; which is 17MHz when the fabric at
+700MHz.
+The HoneyComb / ClearFog CX carrier boards holds an SPI flash that it's
+MUX is limited to 20MHz.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_1900_600_2600.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2400.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2600.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2900.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2400_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2500_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2600_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_defaults.rcwi      | 10 ++++++++--
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi      |  3 ---
+ 10 files changed, 8 insertions(+), 29 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+index 8b61021..a3b7b29 100644
+--- a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
++++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=12
+ 
+ MEM_PLL_RAT=26
+ MEM2_PLL_RAT=26
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+index 6b0b150..4cb3abf 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=24
+ MEM2_PLL_RAT=24
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+index 21dce67..a5c436c 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=26
+ MEM2_PLL_RAT=26
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+index e6a8e30..d1db3fb 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=29
+ MEM2_PLL_RAT=29
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+index 27ee377..22fcadf 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+index fc0fd6c..8f74ff0 100644
+--- a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+index 62d9069..2dc1460 100644
+--- a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+index e244917..d9fd795 100644
+--- a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 7997d49..359e86c 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -45,5 +45,11 @@ write 0x2320000,0x20000000
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+-/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
++/*
++ * Do not modify the FlexSPI clock divisor value when using HoneyComb / ClearFog CX
++ * as carrier boards. The reason is that the analog mux used on the carrier board
++ * can't accomodate more than 20MHz SPI frequency. So keep the value default 0x14
++ * which indicates divide by 80. In 700MHz fabric clock this is around 17MHz SPI
++ * clock.
++ */
++/*#include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index fa092c9..21782ec 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -6,6 +6,3 @@
+ 
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0011-lx210acex7-25Gbps-retimer-and-restructure-config.patch

+From d4a721d712d8fd9f03be2965e0b37bcd33148bdc Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 28 Oct 2020 16:44:35 +0200
+Subject: [PATCH] lx210acex7: 25Gbps retimer and restructure config
+
+1. Split SERDES configuration files that each SERDES block from the
+available 3 can be separately configured.
+2. Added SD1 lanes e,f,g,h include files that configures the SERDES
+lanes to suppoer 25Gbps rate with external retimer (using ClearFog CX
+revision 1.3 and newer).
+3. Added bus speeds 750 and 800MHz which are required to get wire speed
+DPDK performance on a 100Gbps link.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_13_5_2.rcwi       |  3 ---
+ lx2160acex7/configs/lx2160a_17_4_2.rcwi       |  7 ------
+ .../configs/lx2160a_2000_750_3200.rcwi        |  9 +++++++
+ .../configs/lx2160a_2000_800_3200.rcwi        |  9 +++++++
+ lx2160acex7/configs/lx2160a_8_5_0.rcwi        |  7 ------
+ lx2160acex7/configs/lx2160a_SD1_13.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_14.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_17.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_2.rcwi        |  4 +++
+ ...x2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} |  2 --
+ ...{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} |  3 ---
+ lx2160acex7/configs/lx2160a_SD2_5.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_0.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_2.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_3.rcwi        |  1 +
+ .../lx2160a_cex7_hc_sd1_lanes_e_f.rcwi        | 24 ++++++++++++++++++
+ .../lx2160a_cex7_hc_sd1_lanes_g_h.rcwi        | 25 +++++++++++++++++++
+ 17 files changed, 84 insertions(+), 22 deletions(-)
+ delete mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
+ delete mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+ delete mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_13.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_14.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_17.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_2.rcwi
+ rename lx2160acex7/configs/{lx2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} (78%)
+ rename lx2160acex7/configs/{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} (79%)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD2_5.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_0.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_3.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+deleted file mode 100644
+index 76f44bc..0000000
+--- a/lx2160acex7/configs/lx2160a_13_5_2.rcwi
++++ /dev/null
+@@ -1,3 +0,0 @@
+-SRDS_PRTCL_S1=13
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+deleted file mode 100644
+index 358972d..0000000
+--- a/lx2160acex7/configs/lx2160a_17_4_2.rcwi
++++ /dev/null
+@@ -1,7 +0,0 @@
+-SRDS_PRTCL_S1=17
+-SRDS_PRTCL_S2=4
+-SRDS_PRTCL_S3=2
+-
+-/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
+-/*SRDS_PLL_REF_CLK_SEL_S1=2*/
+-
+diff --git a/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+new file mode 100644
+index 0000000..84d544d
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+@@ -0,0 +1,9 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=15
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
+diff --git a/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+new file mode 100644
+index 0000000..31d7cfd
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+@@ -0,0 +1,9 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=16
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
+diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+deleted file mode 100644
+index 62ff153..0000000
+--- a/lx2160acex7/configs/lx2160a_8_5_0.rcwi
++++ /dev/null
+@@ -1,7 +0,0 @@
+-SRDS_PRTCL_S1=8 /* should be 8 */
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=0
+-
+-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+-SRDS_PLL_REF_CLK_SEL_S1=2
+-SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD1_13.rcwi b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
+new file mode 100644
+index 0000000..61b1eea
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=13
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_14.rcwi b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
+new file mode 100644
+index 0000000..75e3fab
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=14
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_17.rcwi b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
+new file mode 100644
+index 0000000..5504271
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=17
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
+new file mode 100644
+index 0000000..0f013e6
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
+@@ -0,0 +1,4 @@
++SRDS_PRTCL_S1=2
++
++SRDS_PLL_REF_CLK_SEL_S1=0
++SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+similarity index 78%
+rename from lx2160acex7/configs/lx2160a_20_5_2.rcwi
+rename to lx2160acex7/configs/lx2160a_SD1_20.rcwi
+index c2c7bea..053aee7 100644
+--- a/lx2160acex7/configs/lx2160a_20_5_2.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+@@ -1,6 +1,4 @@
+ SRDS_PRTCL_S1=20
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+ 
+ SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+ SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
+similarity index 79%
+rename from lx2160acex7/configs/lx2160a_8_5_2.rcwi
+rename to lx2160acex7/configs/lx2160a_SD1_8.rcwi
+index d7d707a..abd6dfd 100644
+--- a/lx2160acex7/configs/lx2160a_8_5_2.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
+@@ -1,7 +1,4 @@
+ SRDS_PRTCL_S1=8 /* should be 8 */
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+-
+ SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+ SRDS_PLL_REF_CLK_SEL_S1=2
+ SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD2_5.rcwi b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
+new file mode 100644
+index 0000000..559a90c
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S2=5
+diff --git a/lx2160acex7/configs/lx2160a_SD3_0.rcwi b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
+new file mode 100644
+index 0000000..1904856
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=0
+diff --git a/lx2160acex7/configs/lx2160a_SD3_2.rcwi b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
+new file mode 100644
+index 0000000..b9c3e6f
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=2
+diff --git a/lx2160acex7/configs/lx2160a_SD3_3.rcwi b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+new file mode 100644
+index 0000000..4695755
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=3
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+new file mode 100644
+index 0000000..d870a4b
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * SERDES tuning based on the following hardware -
++ * - SolidRun COM express type 7 revision 1.7 and newer
++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
++ */
++
++.pbi
++/* Lane E (SD1 TX/RX 3) */
++write 0x01EA0C28,0x00000000
++write 0x01EA0C30,0x20868120
++write 0x01EA0C34,0x23000000
++write 0x01EA0C68,0x80000000
++write 0x01EA0C74,0x00002020
++write 0x01EA0C80,0x00008000
++
++/* Lane F (SD1 TX/RX 2)*/
++write 0x01EA0D28,0x00000000
++write 0x01EA0D30,0x20868120
++write 0x01EA0D34,0x23000000
++write 0x01EA0D68,0x80000000
++write 0x01EA0D74,0x00002020
++write 0x01EA0D80,0x00008000
++.end
++
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+new file mode 100644
+index 0000000..4097b77
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+@@ -0,0 +1,25 @@
++/*
++ * SERDES tuning based on the following hardware -
++ * - SolidRun COM express type 7 revision 1.7 and newer
++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
++ */
++
++.pbi
++/* Lane G (SD1 TX/RX 1)*/
++write 0x01EA0E28,0x00000000
++write 0x01EA0E30,0x20818120
++write 0x01EA0E34,0x23000000
++write 0x01EA0E68,0x80000000
++write 0x01EA0E74,0x00002020
++write 0x01EA0E80,0x00008000
++
++/* Lane H (SD1 TX/RX 0)*/
++write 0x01EA0F28,0x00000000
++write 0x01EA0F30,0x20818120
++write 0x01EA0F34,0x23000000
++write 0x01EA0F68,0x80000000
++write 0x01EA0F74,0x00002020
++write 0x01EA0F80,0x00008000
++
++.end
++
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0012-lx2160acex7-adjust-lanes-e-and-f-for-25g-links.patch

+From 08fedde7e5422756a898dd389250aa1a30c97c7d Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 29 Oct 2020 17:42:50 +0200
+Subject: [PATCH] lx2160acex7: adjust lanes e and f for 25g links
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+index d870a4b..bd35bdc 100644
+--- a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+@@ -7,7 +7,7 @@
+ .pbi
+ /* Lane E (SD1 TX/RX 3) */
+ write 0x01EA0C28,0x00000000
+-write 0x01EA0C30,0x20868120
++write 0x01EA0C30,0x20818120
+ write 0x01EA0C34,0x23000000
+ write 0x01EA0C68,0x80000000
+ write 0x01EA0C74,0x00002020
+@@ -15,7 +15,7 @@ write 0x01EA0C80,0x00008000
+ 
+ /* Lane F (SD1 TX/RX 2)*/
+ write 0x01EA0D28,0x00000000
+-write 0x01EA0D30,0x20868120
++write 0x01EA0D30,0x20818120
+ write 0x01EA0D34,0x23000000
+ write 0x01EA0D68,0x80000000
+ write 0x01EA0D74,0x00002020
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0013-lx2160acex7-added-SERDES-bank-2-with-pcie-x8.patch

+From 30614556e914de366769e6d1bd235d9caa3c6528 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 3 Nov 2020 15:34:34 +0200
+Subject: [PATCH] lx2160acex7: added SERDES bank 2 with pcie x8
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_SD2_2.rcwi | 1 +
+ 1 file changed, 1 insertion(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD2_2.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD2_2.rcwi b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
+new file mode 100644
+index 0000000..daeeb5e
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S2=2
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0014-lx2160acex7-set-correctly-sdcard-card-detect-and-wri.patch

+From ec8c382532d01a3e26491dbcfe2ad854a164006f Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 3 Dec 2020 19:55:07 +0200
+Subject: [PATCH] lx2160acex7: set correctly sdcard card detect and write
+ protect pmux
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 359e86c..30e0399 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -5,7 +5,7 @@ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+ SYSCLK_FREQ=600
+-IIC2_PMUX=1
++IIC2_PMUX=6
+ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/9999-lx2160acex7-add-SD1-mode-4-serdes-configuration.patch

+From 2ae3b51f85375e32b818cb64fbe42750d1d6254f Mon Sep 17 00:00:00 2001
+From: Russell King <rmk@armlinux.org.uk>
+Date: Thu, 23 Jan 2020 15:53:30 +0000
+Subject: [PATCH] lx2160acex7: add SD1 mode 4 serdes configuration
+
+Add mode 4 serdes configuration for SGMII and 1000BASE-X on serdes 1.
+
+Signed-off-by: Russell King <rmk@armlinux.org.uk>
+---
+ lx2160acex7/configs/lx2160a_SD1_4.rcwi | 4 ++++
+ 1 file changed, 4 insertions(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_4.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD1_4.rcwi b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+new file mode 100644
+index 000000000000..ec8ca959b59b
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+@@ -0,0 +1,4 @@
++SRDS_PRTCL_S1=4
++/* SRDS_INTRA_REF_CLK_S1 = 1 PLLF used for PLLS */
++SRDS_PLL_REF_CLK_SEL_S1=0
++SRDS_PLL_PD_PLL1=1
+-- 
+2.20.1
+

patches/u-boot-LSDK-20.12/0001-armv8-add-lx2160acex7-build-inclusion.patch

+From 79520a7c7c201ca1f75ee01bd8b4d6b6a1257d59 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 12 Jan 2021 11:42:10 +0200
+Subject: [PATCH] armv8: add lx2160acex7 build inclusion
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/Kconfig           | 13 +++++++++++++
+ arch/arm/cpu/armv8/Kconfig |  1 +
+ arch/arm/dts/Makefile      |  3 ++-
+ 3 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 01fb4089dc..9005935dd9 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1231,6 +1231,18 @@ config TARGET_LX2160ARDB
+ 	  is a high-performance development platform that supports the
+ 	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+ 
++config TARGET_LX2160ACEX7
++	bool "Support lx2160acex7"
++	select ARCH_LX2160A
++	select ARCH_MISC_INIT
++	select ARM64
++	select ARMV8_MULTIENTRY
++	select BOARD_LATE_INIT
++	help
++	  Support for SolidRun LX2160A based com express type 7 module and
++	  platform. The lx2160acex7 high-performance platform that supports the
++	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
++
+ config TARGET_LX2160AQDS
+ 	bool "Support lx2160aqds"
+ 	select ARCH_LX2160A
+@@ -1863,6 +1875,7 @@ source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/ls1012ardb/Kconfig"
+ source "board/freescale/ls1012afrdm/Kconfig"
+ source "board/freescale/lx2160a/Kconfig"
++source "board/solidrun/lx2160a/Kconfig"
+ source "board/freescale/mx35pdk/Kconfig"
+ source "board/freescale/s32v234evb/Kconfig"
+ source "board/grinn/chiliboard/Kconfig"
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index a4fec595fa..7fffca107f 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -110,6 +110,7 @@ config PSCI_RESET
+ 		   !TARGET_LS1046AFRWY && \
+ 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
+ 		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
++		   !TARGET_LX2160ACEX7 && \
+ 		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
+ 	help
+ 	  Most armv8 systems have PSCI support enabled in EL3, either through
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 72466c73f3..2dda738e59 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -376,7 +376,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ 	fsl-ls1028a-qds-lpuart.dtb \
+ 	fsl-lx2160a-rdb.dtb \
+ 	fsl-lx2160a-qds.dtb \
+-	fsl-lx2162a-qds.dtb
++	fsl-lx2162a-qds.dtb \
++	fsl-lx2160a-cex7.dtb
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ 	fsl-ls1043a-qds-lpuart.dtb \
+ 	fsl-ls1043a-rdb.dtb \
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch

+From 62af256d25d61136913a739b14452b6d35eff3dc Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:29:31 +0300
+Subject: [PATCH 3/6] armv8: lx2160acex7: defconfig and main platform include
+
+This patch add lx2160acex7 main defconfig and main include file.
+Notice that the defconfig doesn't support the secured boot mode where a
+follow up patch will cover this.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++
+ include/configs/lx2160acex7.h     | 85 +++++++++++++++++++++++++++++++
+ 2 files changed, 158 insertions(+)
+ create mode 100644 configs/lx2160acex7_tfa_defconfig
+ create mode 100644 include/configs/lx2160acex7.h
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+new file mode 100644
+index 0000000000..d59de7d054
+--- /dev/null
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -0,0 +1,73 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_SYS_TEXT_BASE=0x82000000
++CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_EMC2301=y
++CONFIG_TFABOOT=y
++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
++CONFIG_AHCI=y
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_FIT_VERBOSE=y
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_OF_BOARD_FIXUP=y
++CONFIG_OF_STDOUT_VIA_ALIAS=y
++CONFIG_BOOTDELAY=10
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_CMD_GREPENV=y
++CONFIG_CMD_EEPROM=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_CACHE=y
++CONFIG_MP=y
++CONFIG_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_DM=y
++CONFIG_SATA_CEVA=y
++CONFIG_FSL_CAAM=y
++CONFIG_DM_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_MICRON=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_PHYLIB=y
++CONFIG_NETDEVICES=y
++CONFIG_PHY_GIGE=y
++CONFIG_CMD_NET=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_EXT2=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_DM_PCI_COMPAT=y
++CONFIG_PCIE_LAYERSCAPE_GEN4=y
++CONFIG_PHY_ATHEROS=y
++CONFIG_E1000=y
++CONFIG_DM_SCSI=y
++CONFIG_DM_SERIAL=y
++CONFIG_SERIAL_PROBE_ALL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_NXP_FSPI=y
++# CONFIG_SYS_NXP_FSPI_AHB=y
++CONFIG_USB=y
++CONFIG_DM_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+new file mode 100644
+index 0000000000..478cd8242f
+--- /dev/null
++++ b/include/configs/lx2160acex7.h
+@@ -0,0 +1,85 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#ifndef __LX2_CEX7_H
++#define __LX2_CEX7_H
++
++#include "lx2160a_common.h"
++
++/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
++/* VID */
++
++#define I2C_MUX_CH_VOL_MONITOR		0x2
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR		0x5c
++#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
++#define CONFIG_VID_FLS_ENV		"lx2160acex7_vdd_mv"
++#define CONFIG_VID
++
++/* The lowest and highest voltage allowed*/
++#define VDD_MV_MIN			700
++#define VDD_MV_MAX			855
++
++/* PM Bus commands code for LTC3882*/
++#define PMBUS_CMD_PAGE                  0x0
++#define PMBUS_CMD_READ_VOUT             0x8B
++#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
++#define PMBUS_CMD_VOUT_COMMAND          0x21
++#define PWM_CHANNEL0                    0x0
++
++#define CONFIG_VOL_MONITOR_LTC3882_SET
++#define CONFIG_VOL_MONITOR_LTC3882_READ
++
++/* RTC */
++#define CONFIG_SYS_RTC_BUS_NUM		4
++
++/* MAC/PHY configuration */
++#if defined(CONFIG_FSL_MC_ENET)
++#define CONFIG_MII
++#define CONFIG_ETHPRIME		"DPMAC17@rgmii-id"
++
++#define RGMII_PHY_ADDR1		0x01
++
++#endif
++
++/* EMC2301 */
++#define I2C_MUX_CH_EMC2301	0x01
++#define I2C_EMC2301_ADDR	0x2f
++#define I2C_EMC2301_CMD		0x40
++#define I2C_EMC2301_PWM		0x80
++
++/* EEPROM */
++#undef CONFIG_ID_EEPROM /* Fixme */
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM	           0
++#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS		\
++	EXTRA_ENV_SETTINGS			\
++	"lx2160acex7_vdd_mv=800\0"		\
++	"BOARD=lx2160acex7\0"			\
++	"xspi_bootcmd=echo Trying load from flexspi..;"		\
++		"sf probe 0:0 && sf read $load_addr "		\
++		"$kernel_start $kernel_size ; env exists secureboot &&"	\
++		"sf read $kernelheader_addr_r $kernelheader_start "	\
++		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
++		" bootm $load_addr#$BOARD\0"			\
++	"sd_bootcmd=echo Trying load from sd card..;"		\
++		"mmcinfo; mmc read $load_addr "			\
++		"$kernel_addr_sd $kernel_size_sd ;"		\
++		"env exists secureboot && mmc read $kernelheader_addr_r "\
++		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
++		" && esbc_validate ${kernelheader_addr_r};"	\
++		"bootm $load_addr#$BOARD\0"
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __LX2_CEX7_H */
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0004-armv8-lx2160acex7-common-files-for-platform-support.patch

+From 7aae154166d92aa59c8b097b4dd076d969e0e12b Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 12 Jan 2021 11:51:37 +0200
+Subject: [PATCH 4/4] armv8: lx2160acex7: common files for platform support
+
+The patch copies and modifies NXP's common platform resources that adds
+support to the following -
+1. Secureboot
+2. Analog devices DC-DC controller
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/common/Makefile             |   5 +
+ board/solidrun/common/cmd_esbc_validate.c  |  85 ++
+ board/solidrun/common/fsl_chain_of_trust.c | 164 ++++
+ board/solidrun/common/fsl_validate.c       | 962 +++++++++++++++++++++
+ board/solidrun/common/vid.c                | 330 +++++++
+ board/solidrun/common/vid.h                |  23 +
+ 6 files changed, 1571 insertions(+)
+ create mode 100644 board/solidrun/common/cmd_esbc_validate.c
+ create mode 100644 board/solidrun/common/fsl_chain_of_trust.c
+ create mode 100644 board/solidrun/common/fsl_validate.c
+ create mode 100644 board/solidrun/common/vid.c
+ create mode 100644 board/solidrun/common/vid.h
+
+diff --git a/board/solidrun/common/Makefile b/board/solidrun/common/Makefile
+index a72ac1b7b9..77b0d798da 100644
+--- a/board/solidrun/common/Makefile
++++ b/board/solidrun/common/Makefile
+@@ -3,3 +3,8 @@
+ # Copyright (C) SolidRun
+ 
+ obj-$(CONFIG_TARGET_CLEARFOG) += tlv_data.o
++obj-$(CONFIG_VID)		+= vid.o
++ifdef CONFIG_SECURE_BOOT
++obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
++endif
++obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
+diff --git a/board/solidrun/common/cmd_esbc_validate.c b/board/solidrun/common/cmd_esbc_validate.c
+new file mode 100644
+index 0000000000..b06235f291
+--- /dev/null
++++ b/board/solidrun/common/cmd_esbc_validate.c
+@@ -0,0 +1,85 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <common.h>
++#include <command.h>
++#include <fsl_validate.h>
++
++int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
++				char * const argv[])
++{
++	if (fsl_check_boot_mode_secure() == 0) {
++		printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
++		return 0;
++	}
++
++	printf("Core is entering spin loop.\n");
++loop:
++	goto loop;
++
++	return 0;
++}
++
++#ifndef CONFIG_SPL_BUILD
++static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
++				char * const argv[])
++{
++	char *hash_str = NULL;
++	uintptr_t haddr;
++	int ret;
++	uintptr_t img_addr = 0;
++	char buf[20];
++
++	if (argc < 2)
++		return cmd_usage(cmdtp);
++	else if (argc > 2)
++		/* Second arg - Optional - Hash Str*/
++		hash_str = argv[2];
++
++	/* First argument - header address -32/64bit */
++	haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16);
++
++	/* With esbc_validate command, Image address must be
++	 * part of header. So, the function is called
++	 * by passing this argument as 0.
++	 */
++	ret = fsl_secboot_validate(haddr, hash_str, &img_addr);
++
++	/* Need to set "img_addr" even if validation failure.
++	 * Required when SB_EN in RCW set and non-fatal error
++	 * to continue U-Boot
++	 */
++	sprintf(buf, "%lx", img_addr);
++	env_set("img_addr", buf);
++
++	if (ret)
++		return 1;
++
++	printf("esbc_validate command successful\n");
++	return 0;
++}
++
++/***************************************************/
++static char esbc_validate_help_text[] =
++	"esbc_validate hdr_addr <hash_val> - Validates signature using\n"
++	"                          RSA verification\n"
++	"                          $hdr_addr Address of header of the image\n"
++	"                          to be validated.\n"
++	"                          $hash_val -Optional\n"
++	"                          It provides Hash of public/srk key to be\n"
++	"                          used to verify signature.\n";
++
++U_BOOT_CMD(
++	esbc_validate,	3,	0,	do_esbc_validate,
++	"Validates signature on a given image using RSA verification",
++	esbc_validate_help_text
++);
++
++U_BOOT_CMD(
++	esbc_halt,	1,	0,	do_esbc_halt,
++	"Put the core in spin loop (Secure Boot Only)",
++	""
++);
++#endif
+diff --git a/board/solidrun/common/fsl_chain_of_trust.c b/board/solidrun/common/fsl_chain_of_trust.c
+new file mode 100644
+index 0000000000..dddfd26a13
+--- /dev/null
++++ b/board/solidrun/common/fsl_chain_of_trust.c
+@@ -0,0 +1,164 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <common.h>
++#include <dm.h>
++#include <fsl_validate.h>
++#include <fsl_secboot_err.h>
++#include <fsl_sfp.h>
++#include <dm/root.h>
++
++#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
++#include <spl.h>
++#endif
++
++#ifdef CONFIG_ADDR_MAP
++#include <asm/mmu.h>
++#endif
++
++#ifdef CONFIG_FSL_CORENET
++#include <asm/fsl_pamu.h>
++#endif
++
++#ifdef CONFIG_ARCH_LS1021A
++#include <asm/arch/immap_ls102xa.h>
++#endif
++
++#if defined(CONFIG_MPC85xx)
++#define CONFIG_DCFG_ADDR	CONFIG_SYS_MPC85xx_GUTS_ADDR
++#else
++#define CONFIG_DCFG_ADDR	CONFIG_SYS_FSL_GUTS_ADDR
++#endif
++
++#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
++#define gur_in32(a)       in_le32(a)
++#else
++#define gur_in32(a)       in_be32(a)
++#endif
++
++/* Check the Boot Mode. If Secure, return 1 else return 0 */
++int fsl_check_boot_mode_secure(void)
++{
++	uint32_t val;
++	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
++	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
++
++	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
++	if (val == ITS_MASK)
++		return 1;
++
++#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
++	/* For PBL based platforms check the SB_EN bit in RCWSR */
++	val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
++	if (val == RCW_SB_EN_MASK)
++		return 1;
++#endif
++
++#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
++	/* For Non-PBL Platforms, check the Device Status register 2*/
++	val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
++	if (val != MPC85xx_PORDEVSR2_SBC_MASK)
++		return 1;
++
++#endif
++	return 0;
++}
++
++#ifndef CONFIG_SPL_BUILD
++int fsl_setenv_chain_of_trust(void)
++{
++	/* Check Boot Mode
++	 * If Boot Mode is Non-Secure, no changes are required
++	 */
++	if (fsl_check_boot_mode_secure() == 0)
++		return 0;
++
++	/* If Boot mode is Secure, set the environment variables
++	 * bootdelay = 0 (To disable Boot Prompt)
++	 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
++	 */
++	env_set("bootdelay", "-2");
++
++#ifdef CONFIG_ARM
++	env_set("secureboot", "y");
++#else
++	env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
++#endif
++
++	return 0;
++}
++#endif
++
++#ifdef CONFIG_SPL_BUILD
++void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
++{
++	int res;
++
++	/*
++	 * Check Boot Mode
++	 * If Boot Mode is Non-Secure, skip validation
++	 */
++	if (fsl_check_boot_mode_secure() == 0)
++		return;
++
++	printf("SPL: Validating U-Boot image\n");
++
++#ifdef CONFIG_ADDR_MAP
++	init_addr_map();
++#endif
++
++#ifdef CONFIG_FSL_CORENET
++	if (pamu_init() < 0)
++		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
++#endif
++
++#ifdef CONFIG_FSL_CAAM
++	if (sec_init() < 0)
++		fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
++#endif
++
++/*
++ * dm_init_and_scan() is called as part of common SPL framework, so no
++ * need to call it again but in case of powerpc platforms which currently
++ * do not use common SPL framework, so need to call this function here.
++ */
++#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
++	dm_init_and_scan(true);
++#endif
++	res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
++				   &img_addr);
++
++	if (res == 0)
++		printf("SPL: Validation of U-boot successful\n");
++}
++
++#ifdef CONFIG_SPL_FRAMEWORK
++/* Override weak funtion defined in SPL framework to enable validation
++ * of main u-boot image before jumping to u-boot image.
++ */
++void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
++{
++	typedef void __noreturn (*image_entry_noargs_t)(void);
++	uint32_t hdr_addr;
++
++	image_entry_noargs_t image_entry =
++		(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
++
++	hdr_addr = (spl_image->entry_point + spl_image->size -
++			CONFIG_U_BOOT_HDR_SIZE);
++	spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
++	/*
++	 * In case of failure in validation, spl_validate_uboot would
++	 * not return back in case of Production environment with ITS=1.
++	 * Thus U-Boot will not start.
++	 * In Development environment (ITS=0 and SB_EN=1), the function
++	 * may return back in case of non-fatal failures.
++	 */
++
++	debug("image entry point: 0x%lX\n", spl_image->entry_point);
++	image_entry();
++}
++#endif /* ifdef CONFIG_SPL_FRAMEWORK */
++#endif /* ifdef CONFIG_SPL_BUILD */
+diff --git a/board/solidrun/common/fsl_validate.c b/board/solidrun/common/fsl_validate.c
+new file mode 100644
+index 0000000000..2bf9d58746
+--- /dev/null
++++ b/board/solidrun/common/fsl_validate.c
+@@ -0,0 +1,962 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <common.h>
++#include <dm.h>
++#include <fsl_validate.h>
++#include <fsl_secboot_err.h>
++#include <fsl_sfp.h>
++#include <fsl_sec.h>
++#include <command.h>
++#include <malloc.h>
++#include <u-boot/rsa-mod-exp.h>
++#include <hash.h>
++#include <fsl_secboot_err.h>
++#ifdef CONFIG_ARCH_LS1021A
++#include <asm/arch/immap_ls102xa.h>
++#endif
++
++#define SHA256_BITS	256
++#define SHA256_BYTES	(256/8)
++#define SHA256_NIBBLES	(256/4)
++#define NUM_HEX_CHARS	(sizeof(ulong) * 2)
++
++#define CHECK_KEY_LEN(key_len)	(((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
++				 ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
++				 ((key_len) == 2 * KEY_SIZE_BYTES))
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++/* Global data structure */
++static struct fsl_secboot_glb glb;
++#endif
++
++/* This array contains DER value for SHA-256 */
++static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
++		0x86, 0x48, 0x01, 0x65,	0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
++		0x04, 0x20
++		};
++
++static u8 hash_val[SHA256_BYTES];
++
++#ifdef CONFIG_ESBC_HDR_LS
++/* New Barker Code for LS ESBC Header */
++static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
++#else
++static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
++#endif
++
++void branch_to_self(void) __attribute__ ((noreturn));
++
++/*
++ * This function will put core in infinite loop.
++ * This will be called when the ESBC can not proceed further due
++ * to some unknown errors.
++ */
++void branch_to_self(void)
++{
++	printf("Core is in infinite loop due to errors.\n");
++self:
++	goto self;
++}
++
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++static u32 check_ie(struct fsl_secboot_img_priv *img)
++{
++	if (img->hdr.ie_flag & IE_FLAG_MASK)
++		return 1;
++
++	return 0;
++}
++
++/* This function returns the CSF Header Address of uboot
++ * For MPC85xx based platforms, the LAW mapping for NOR
++ * flash changes in uboot code. Hence the offset needs
++ * to be calculated and added to the new NOR flash base
++ * address
++ */
++#if defined(CONFIG_MPC85xx)
++int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
++{
++	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
++	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
++	u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
++	u32 flash_addr, addr;
++	int found = 0;
++	int i = 0;
++
++	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
++		flash_addr = flash_info[i].start[0];
++		addr = flash_info[i].start[0] + csf_flash_offset;
++		if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
++			debug("Barker found on addr %x\n", addr);
++			found = 1;
++			break;
++		}
++	}
++
++	if (!found)
++		return -1;
++
++	*csf_addr = addr;
++	*flash_base_addr = flash_addr;
++
++	return 0;
++}
++#else
++/* For platforms like LS1020, correct flash address is present in
++ * the header. So the function reqturns flash base address as 0
++ */
++int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
++{
++	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
++
++	if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
++		   barker_code, ESBC_BARKER_LEN))
++		return -1;
++
++	*csf_addr = csf_hdr_addr;
++	*flash_base_addr = 0;
++	return 0;
++}
++#endif
++
++#if defined(CONFIG_ESBC_HDR_LS)
++static int get_ie_info_addr(uintptr_t *ie_addr)
++{
++	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++	/* For LS-CH3, the address of IE Table is
++	 * stated in Scratch13 and scratch14 of DCFG.
++	 * Bootrom validates this table while validating uboot.
++	 * DCFG is LE*/
++	*ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
++	*ie_addr = *ie_addr << 32;
++	*ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
++	return 0;
++}
++#else /* CONFIG_ESBC_HDR_LS */
++static int get_ie_info_addr(uintptr_t *ie_addr)
++{
++	struct fsl_secboot_img_hdr *hdr;
++	struct fsl_secboot_sg_table *sg_tbl;
++	u32 flash_base_addr, csf_addr;
++
++	if (get_csf_base_addr(&csf_addr, &flash_base_addr))
++		return -1;
++
++	hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
++
++	/* For SoC's with Trust Architecture v1 with corenet bus
++	 * the sg table field in CSF header has absolute address
++	 * for sg table in memory. In other Trust Architecture,
++	 * this field specifies the offset of sg table from the
++	 * base address of CSF Header
++	 */
++#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
++	sg_tbl = (struct fsl_secboot_sg_table *)
++		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
++		  flash_base_addr);
++#else
++	sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
++						 (u32)hdr->psgtable);
++#endif
++
++	/* IE Key Table is the first entry in the SG Table */
++#if defined(CONFIG_MPC85xx)
++	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
++			~(CONFIG_SYS_PBI_FLASH_BASE)) +
++			flash_base_addr);
++#else
++	*ie_addr = (uintptr_t)sg_tbl->src_addr;
++#endif
++
++	debug("IE Table address is %lx\n", *ie_addr);
++	return 0;
++}
++#endif /* CONFIG_ESBC_HDR_LS */
++#endif
++
++#ifdef CONFIG_KEY_REVOCATION
++/* This function checks srk_table_flag in header and set/reset srk_flag.*/
++static u32 check_srk(struct fsl_secboot_img_priv *img)
++{
++#ifdef CONFIG_ESBC_HDR_LS
++	/* In LS, No SRK Flag as SRK is always present if IE not present*/
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	return !check_ie(img);
++#endif
++	return 1;
++#else
++	if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
++		return 1;
++
++	return 0;
++#endif
++}
++
++/* This function returns ospr's key_revoc values.*/
++static u32 get_key_revoc(void)
++{
++	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
++	return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
++		OSPR_KEY_REVOC_SHIFT;
++}
++
++/* This function checks if selected key is revoked or not.*/
++static u32 is_key_revoked(u32 keynum, u32 rev_flag)
++{
++	if (keynum == UNREVOCABLE_KEY)
++		return 0;
++
++	if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag)
++		return 1;
++
++	return 0;
++}
++
++/* It read validates srk_table key lengths.*/
++static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img)
++{
++	int i = 0;
++	u32 ret, key_num, key_revoc_flag, size;
++	struct fsl_secboot_img_hdr *hdr = &img->hdr;
++	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
++
++	if ((hdr->len_kr.num_srk == 0) ||
++	    (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
++		return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
++
++	key_num = hdr->len_kr.srk_sel;
++	if (key_num == 0 || key_num > hdr->len_kr.num_srk)
++		return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
++
++	/* Get revoc key from sfp */
++	key_revoc_flag = get_key_revoc();
++	ret = is_key_revoked(key_num, key_revoc_flag);
++	if (ret)
++		return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
++
++	size = hdr->len_kr.num_srk * sizeof(struct srk_table);
++
++	memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
++
++	for (i = 0; i < hdr->len_kr.num_srk; i++) {
++		if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len))
++			return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
++	}
++
++	img->key_len = img->srk_tbl[key_num - 1].key_len;
++
++	memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
++	       img->key_len);
++
++	return 0;
++}
++#endif
++
++#ifndef CONFIG_ESBC_HDR_LS
++static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
++{
++	struct fsl_secboot_img_hdr *hdr = &img->hdr;
++	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
++
++	/* check key length */
++	if (!CHECK_KEY_LEN(hdr->key_len))
++		return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
++
++	memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
++
++	img->key_len = hdr->key_len;
++
++	return 0;
++}
++#endif /* CONFIG_ESBC_HDR_LS */
++
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++
++static void install_ie_tbl(uintptr_t ie_tbl_addr,
++		struct fsl_secboot_img_priv *img)
++{
++	/* Copy IE tbl to Global Data */
++	memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
++	img->ie_addr = (uintptr_t)&glb.ie_tbl;
++	glb.ie_addr = img->ie_addr;
++}
++
++static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
++{
++	struct fsl_secboot_img_hdr *hdr = &img->hdr;
++	u32 ie_key_len, ie_revoc_flag, ie_num;
++	struct ie_key_info *ie_info;
++
++	if (!img->ie_addr) {
++		if (get_ie_info_addr(&img->ie_addr))
++			return ERROR_IE_TABLE_NOT_FOUND;
++		else
++			install_ie_tbl(img->ie_addr, img);
++		}
++
++	ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
++	if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
++		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
++
++	ie_num = hdr->ie_key_sel;
++	if (ie_num == 0 || ie_num > ie_info->num_keys)
++		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
++
++	ie_revoc_flag = ie_info->key_revok;
++	if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
++		return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
++
++	ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
++
++	if (!CHECK_KEY_LEN(ie_key_len))
++		return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
++
++	memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
++	       ie_key_len);
++
++	img->key_len = ie_key_len;
++	return 0;
++}
++#endif
++
++
++/* This function return length of public key.*/
++static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
++{
++	return img->key_len;
++}
++
++/*
++ * Handles the ESBC uboot client header verification failure.
++ * This  function  handles all the errors which might occur in the
++ * parsing and checking of ESBC uboot client header. It will also
++ * set the error bits in the SEC_MON.
++ */
++static void fsl_secboot_header_verification_failure(void)
++{
++	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
++
++	/* 29th bit of OSPR is ITS */
++	u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
++
++	if (its == 1)
++		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
++	else
++		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
++
++	printf("Generating reset request\n");
++	do_reset(NULL, 0, 0, NULL);
++	/* If reset doesn't coocur, halt execution */
++	do_esbc_halt(NULL, 0, 0, NULL);
++}
++
++/*
++ * Handles the ESBC uboot client image verification failure.
++ * This  function  handles all the errors which might occur in the
++ * public key hash comparison and signature verification of
++ * ESBC uboot client image. It will also
++ * set the error bits in the SEC_MON.
++ */
++static void fsl_secboot_image_verification_failure(void)
++{
++	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
++
++	u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
++
++	if (its == 1) {
++		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
++
++		printf("Generating reset request\n");
++		do_reset(NULL, 0, 0, NULL);
++		/* If reset doesn't coocur, halt execution */
++		do_esbc_halt(NULL, 0, 0, NULL);
++
++	} else {
++		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
++	}
++}
++
++static void fsl_secboot_bootscript_parse_failure(void)
++{
++	fsl_secboot_header_verification_failure();
++}
++
++/*
++ * Handles the errors in esbc boot.
++ * This  function  handles all the errors which might occur in the
++ * esbc boot phase. It will call the appropriate api to log the
++ * errors and set the error bits in the SEC_MON.
++ */
++void fsl_secboot_handle_error(int error)
++{
++#ifndef CONFIG_SPL_BUILD
++	const struct fsl_secboot_errcode *e;
++
++	for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
++		e++) {
++		if (e->errcode == error)
++			printf("ERROR :: %x :: %s\n", error, e->name);
++	}
++#else
++	printf("ERROR :: %x\n", error);
++#endif
++
++	/* If Boot Mode is secure, transition the SNVS state and issue
++	 * reset based on type of failure and ITS setting.
++	 * If Boot mode is non-secure, return from this function.
++	 */
++	if (fsl_check_boot_mode_secure() == 0)
++		return;
++
++	switch (error) {
++	case ERROR_ESBC_CLIENT_HEADER_BARKER:
++	case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
++	case ERROR_ESBC_CLIENT_HEADER_KEY_LEN:
++	case ERROR_ESBC_CLIENT_HEADER_SIG_LEN:
++	case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN:
++	case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1:
++	case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2:
++	case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
++	case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
++	case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
++	case ERROR_KEY_TABLE_NOT_FOUND:
++#ifdef CONFIG_KEY_REVOCATION
++	case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
++	case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
++	case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
++	case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
++#endif
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	/*@fallthrough@*/
++	case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
++	case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
++	case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM:
++	case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN:
++	case ERROR_IE_TABLE_NOT_FOUND:
++#endif
++		fsl_secboot_header_verification_failure();
++		break;
++	case ERROR_ESBC_SEC_RESET:
++	case ERROR_ESBC_SEC_DEQ:
++	case ERROR_ESBC_SEC_ENQ:
++	case ERROR_ESBC_SEC_DEQ_TO:
++	case ERROR_ESBC_SEC_JOBQ_STATUS:
++	case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY:
++	case ERROR_ESBC_CLIENT_HASH_COMPARE_EM:
++		fsl_secboot_image_verification_failure();
++		break;
++	case ERROR_ESBC_MISSING_BOOTM:
++		fsl_secboot_bootscript_parse_failure();
++		break;
++	case ERROR_ESBC_WRONG_CMD:
++	default:
++		branch_to_self();
++		break;
++	}
++}
++
++static void fsl_secblk_handle_error(int error)
++{
++	switch (error) {
++	case ERROR_ESBC_SEC_ENQ:
++		fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ);
++		break;
++	case ERROR_ESBC_SEC_DEQ:
++		fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ);
++		break;
++	case ERROR_ESBC_SEC_DEQ_TO:
++		fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO);
++		break;
++	default:
++		printf("Job Queue Output status %x\n", error);
++		fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS);
++		break;
++	}
++}
++
++/*
++ * Calculate hash of key obtained via offset present in ESBC uboot
++ * client hdr. This function calculates the hash of key which is obtained
++ * through offset present in ESBC uboot client header.
++ */
++static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
++{
++	struct hash_algo *algo;
++	void *ctx;
++	int i, srk = 0;
++	int ret = 0;
++	const char *algo_name = "sha256";
++
++	/* Calculate hash of the esbc key */
++	ret = hash_progressive_lookup_algo(algo_name, &algo);
++	if (ret)
++		return ret;
++
++	ret = algo->hash_init(algo, &ctx);
++	if (ret)
++		return ret;
++
++	/* Update hash for ESBC key */
++#ifdef CONFIG_KEY_REVOCATION
++	if (check_srk(img)) {
++		ret = algo->hash_update(algo, ctx,
++		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
++		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
++		srk = 1;
++	}
++#endif
++	if (!srk)
++		ret = algo->hash_update(algo, ctx,
++			img->img_key, img->key_len, 1);
++	if (ret)
++		return ret;
++
++	/* Copy hash at destination buffer */
++	ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < SHA256_BYTES; i++)
++		img->img_key_hash[i] = hash_val[i];
++
++	return 0;
++}
++
++/*
++ * Calculate hash of ESBC hdr and ESBC. This function calculates the
++ * single hash of ESBC header and ESBC image. If SG flag is on, all
++ * SG entries are also hashed alongwith the complete SG table.
++ */
++static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
++{
++	struct hash_algo *algo;
++	void *ctx;
++	int ret = 0;
++	int key_hash = 0;
++	const char *algo_name = "sha256";
++
++	/* Calculate the hash of the ESBC */
++	ret = hash_progressive_lookup_algo(algo_name, &algo);
++	if (ret)
++		return ret;
++
++	ret = algo->hash_init(algo, &ctx);
++	/* Copy hash at destination buffer */
++	if (ret)
++		return ret;
++
++	/* Update hash for CSF Header */
++	ret = algo->hash_update(algo, ctx,
++		(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
++	if (ret)
++		return ret;
++
++	/* Update the hash with that of srk table if srk flag is 1
++	 * If IE Table is selected, key is not added in the hash
++	 * If neither srk table nor IE key table available, add key
++	 * from header in the hash calculation
++	 */
++#ifdef CONFIG_KEY_REVOCATION
++	if (check_srk(img)) {
++		ret = algo->hash_update(algo, ctx,
++		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
++		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
++		key_hash = 1;
++	}
++#endif
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	if (!key_hash && check_ie(img))
++		key_hash = 1;
++#endif
++#ifndef CONFIG_ESBC_HDR_LS
++/* No single key support in LS ESBC header */
++	if (!key_hash) {
++		ret = algo->hash_update(algo, ctx,
++			img->img_key, img->hdr.key_len, 0);
++		key_hash = 1;
++	}
++#endif
++	if (ret)
++		return ret;
++	if (!key_hash)
++		return ERROR_KEY_TABLE_NOT_FOUND;
++
++	/* Update hash for actual Image */
++	ret = algo->hash_update(algo, ctx,
++		(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
++	if (ret)
++		return ret;
++
++	/* Copy hash at destination buffer */
++	ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++/*
++ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
++ * pointers for padding, DER value and hash. And finally, constructs EM'
++ * which includes hash of complete CSF header and ESBC image. If SG flag
++ * is on, hash of SG table and entries is also included.
++ */
++static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img)
++{
++	/*
++	 * RSA PKCSv1.5 encoding format for encoded message is below
++	 * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
++	 * PS is Padding String
++	 * DER is DER value for SHA-256
++	 * Hash is SHA-256 hash
++	 * *********************************************************
++	 * representative points to first byte of EM initially and is
++	 * filled with 0x0
++	 * representative is incremented by 1 and second byte is filled
++	 * with 0x1
++	 * padding points to third byte of EM
++	 * digest points to full length of EM - 32 bytes
++	 * hash_id (DER value) points to 19 bytes before pDigest
++	 * separator is one byte which separates padding and DER
++	 */
++
++	size_t len;
++	u8 *representative;
++	u8 *padding, *digest;
++	u8 *hash_id, *separator;
++	int i;
++
++	len = (get_key_len(img) / 2) - 1;
++	representative = img->img_encoded_hash_second;
++	representative[0] = 0;
++	representative[1] = 1;  /* block type 1 */
++
++	padding = &representative[2];
++	digest = &representative[1] + len - 32;
++	hash_id = digest - sizeof(hash_identifier);
++	separator = hash_id - 1;
++
++	/* fill padding area pointed by padding with 0xff */
++	memset(padding, 0xff, separator - padding);
++
++	/* fill byte pointed by separator */
++	*separator = 0;
++
++	/* fill SHA-256 DER value  pointed by HashId */
++	memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
++
++	/* fill hash pointed by Digest */
++	for (i = 0; i < SHA256_BYTES; i++)
++		digest[i] = hash_val[i];
++}
++
++/*
++ * Reads and validates the ESBC client header.
++ * This function reads key and signature from the ESBC client header.
++ * If Scatter/Gather flag is on, lengths and offsets of images
++ * present as SG entries are also read. This function also checks
++ * whether the header is valid or not.
++ */
++static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
++{
++	struct fsl_secboot_img_hdr *hdr = &img->hdr;
++	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
++	u8 *k, *s;
++	u32 ret = 0;
++
++	int  key_found = 0;
++
++	/* check barker code */
++	if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
++		return ERROR_ESBC_CLIENT_HEADER_BARKER;
++
++	/* If Image Address is not passed as argument to function,
++	 * then Address and Size must be read from the Header.
++	 */
++	if (*(img->img_addr_ptr) == 0) {
++	#ifdef CONFIG_ESBC_ADDR_64BIT
++		*(img->img_addr_ptr) = hdr->pimg64;
++	#else
++		*(img->img_addr_ptr) = hdr->pimg;
++	#endif
++	}
++
++	if (!hdr->img_size)
++		return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
++
++	img->img_size = hdr->img_size;
++
++	/* Key checking*/
++#ifdef CONFIG_KEY_REVOCATION
++	if (check_srk(img)) {
++		ret = read_validate_srk_tbl(img);
++		if (ret != 0)
++			return ret;
++		key_found = 1;
++	}
++#endif
++
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	if (!key_found && check_ie(img)) {
++		ret = read_validate_ie_tbl(img);
++		if (ret != 0)
++			return ret;
++		key_found = 1;
++	}
++#endif
++#ifndef CONFIG_ESBC_HDR_LS
++/* Single Key Feature not available in LS ESBC Header */
++	if (key_found == 0) {
++		ret = read_validate_single_key(img);
++		if (ret != 0)
++			return ret;
++		key_found = 1;
++	}
++#endif
++	if (!key_found)
++		return ERROR_KEY_TABLE_NOT_FOUND;
++
++	/* check signaure */
++	if (get_key_len(img) == 2 * hdr->sign_len) {
++		/* check signature length */
++		if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) ||
++		      (hdr->sign_len == KEY_SIZE_BYTES / 2) ||
++		      (hdr->sign_len == KEY_SIZE_BYTES)))
++			return ERROR_ESBC_CLIENT_HEADER_SIG_LEN;
++	} else {
++		return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN;
++	}
++
++	memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
++/* No SG support in LS-CH3 */
++#ifndef CONFIG_ESBC_HDR_LS
++	/* No SG support */
++	if (hdr->sg_flag)
++		return ERROR_ESBC_CLIENT_HEADER_SG;
++#endif
++
++	/* modulus most significant bit should be set */
++	k = (u8 *)&img->img_key;
++
++	if ((k[0] & 0x80) == 0)
++		return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1;
++
++	/* modulus value should be odd */
++	if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0)
++		return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2;
++
++	/* Check signature value < modulus value */
++	s = (u8 *)&img->img_sign;
++
++	if (!(memcmp(s, k, hdr->sign_len) < 0))
++		return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD;
++
++	return ESBC_VALID_HDR;
++}
++
++static inline int str2longbe(const char *p, ulong *num)
++{
++	char *endptr;
++	ulong tmp;
++
++	if (!p) {
++		return 0;
++	} else {
++		tmp = simple_strtoul(p, &endptr, 16);
++		if (sizeof(ulong) == 4)
++			*num = cpu_to_be32(tmp);
++		else
++			*num = cpu_to_be64(tmp);
++	}
++
++	return *p != '\0' && *endptr == '\0';
++}
++/* Function to calculate the ESBC Image Hash
++ * and hash from Digital signature.
++ * The Two hash's are compared to yield the
++ * result of signature validation.
++ */
++static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
++{
++	int ret;
++	uint32_t key_len;
++	struct key_prop prop;
++#if !defined(USE_HOSTCC)
++	struct udevice *mod_exp_dev;
++#endif
++	ret = calc_esbchdr_esbc_hash(img);
++	if (ret)
++		return ret;
++
++	/* Construct encoded hash EM' wrt PKCSv1.5 */
++	construct_img_encoded_hash_second(img);
++
++	/* Fill prop structure for public key */
++	memset(&prop, 0, sizeof(struct key_prop));
++	key_len = get_key_len(img) / 2;
++	prop.modulus = img->img_key;
++	prop.public_exponent = img->img_key + key_len;
++	prop.num_bits = key_len * 8;
++	prop.exp_len = key_len;
++
++	ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
++	if (ret) {
++		printf("RSA: Can't find Modular Exp implementation\n");
++		return -EINVAL;
++	}
++
++	ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
++			  &prop, img->img_encoded_hash);
++	if (ret)
++		return ret;
++
++	/*
++	 * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
++	 * memcmp returns zero on success
++	 * memcmp returns non-zero on failure
++	 */
++	ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
++		img->hdr.sign_len);
++
++	if (ret)
++		return ERROR_ESBC_CLIENT_HASH_COMPARE_EM;
++
++	return 0;
++}
++/* Function to initialize img priv and global data structure
++ */
++static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
++{
++	*img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
++
++	struct fsl_secboot_img_priv *img = *img_ptr;
++
++	if (!img)
++		return -ENOMEM;
++	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
++
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	if (glb.ie_addr)
++		img->ie_addr = glb.ie_addr;
++#endif
++	return 0;
++}
++
++
++/* haddr - Address of the header of image to be validated.
++ * arg_hash_str - Option hash string. If provided, this
++ * overrides the key hash in the SFP fuses.
++ * img_addr_ptr - Optional pointer to address of image to be validated.
++ * If non zero addr, this overrides the addr of image in header,
++ * otherwise updated to image addr in header.
++ * Acts as both input and output of function.
++ * This pointer shouldn't be NULL.
++ */
++int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
++			uintptr_t *img_addr_ptr)
++{
++	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
++	ulong hash[SHA256_BYTES/sizeof(ulong)];
++	char hash_str[NUM_HEX_CHARS + 1];
++	struct fsl_secboot_img_priv *img;
++	struct fsl_secboot_img_hdr *hdr;
++	void *esbc;
++	int ret, i, hash_cmd = 0;
++	u32 srk_hash[8];
++
++	if (arg_hash_str != NULL) {
++		const char *cp = arg_hash_str;
++		int i = 0;
++
++		if (*cp == '0' && *(cp + 1) == 'x')
++			cp += 2;
++
++		/* The input string expected is in hex, where
++		 * each 4 bits would be represented by a hex
++		 * sha256 hash is 256 bits long, which would mean
++		 * num of characters = 256 / 4
++		 */
++		if (strlen(cp) != SHA256_NIBBLES) {
++			printf("%s is not a 256 bits hex string as expected\n",
++			       arg_hash_str);
++			return -1;
++		}
++
++		for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) {
++			strncpy(hash_str, cp + (i * NUM_HEX_CHARS),
++				NUM_HEX_CHARS);
++			hash_str[NUM_HEX_CHARS] = '\0';
++			if (!str2longbe(hash_str, &hash[i])) {
++				printf("%s is not a 256 bits hex string ",
++				       arg_hash_str);
++				return -1;
++			}
++		}
++
++		hash_cmd = 1;
++	}
++
++	ret = secboot_init(&img);
++	if (ret)
++		goto exit;
++
++	/* Update the information in Private Struct */
++	hdr = &img->hdr;
++	img->ehdrloc = haddr;
++	img->img_addr_ptr = img_addr_ptr;
++	esbc = (u8 *)img->ehdrloc;
++
++	memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
++
++	/* read and validate esbc header */
++	ret = read_validate_esbc_client_header(img);
++
++	if (ret != ESBC_VALID_HDR) {
++		fsl_secboot_handle_error(ret);
++		goto exit;
++	}
++
++	/* SRKH present in SFP */
++	for (i = 0; i < NUM_SRKH_REGS; i++)
++		srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]);
++
++	/*
++	 * Calculate hash of key obtained via offset present in
++	 * ESBC uboot client hdr
++	 */
++	ret = calc_img_key_hash(img);
++	if (ret) {
++		fsl_secblk_handle_error(ret);
++		goto exit;
++	}
++
++	/* Compare hash obtained above with SRK hash present in SFP */
++	if (hash_cmd)
++		ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES);
++	else
++		ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
++
++#if defined(CONFIG_FSL_ISBC_KEY_EXT)
++	if (!hash_cmd && check_ie(img))
++		ret = 0;
++#endif
++
++	if (ret != 0) {
++		fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY);
++		goto exit;
++	}
++
++	ret = calculate_cmp_img_sig(img);
++	if (ret) {
++		fsl_secboot_handle_error(ret);
++		goto exit;
++	}
++
++exit:
++	/* Free Img as it was malloc'ed*/
++	free(img);
++	return ret;
++}
+diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
+new file mode 100644
+index 0000000000..cc81e80c37
+--- /dev/null
++++ b/board/solidrun/common/vid.c
+@@ -0,0 +1,330 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ * Copyright 2018 NXP
++ */
++#include <common.h>
++#include <command.h>
++#include <i2c.h>
++#include <asm/io.h>
++#ifdef CONFIG_FSL_LSCH2
++#include <asm/arch/immap_lsch2.h>
++#elif defined(CONFIG_FSL_LSCH3)
++#include <asm/arch/immap_lsch3.h>
++#else
++#include <asm/immap_85xx.h>
++#endif
++#include "vid.h"
++
++int __weak i2c_multiplexer_select_vid_channel(u8 channel)
++{
++	return 0;
++}
++
++/*
++ * Compensate for a board specific voltage drop between regulator and SoC
++ * return a value in mV
++ */
++int __weak board_vdd_drop_compensation(void)
++{
++	return 0;
++}
++
++/*
++ * Board specific settings for specific voltage value
++ */
++int __weak board_adjust_vdd(int vdd)
++{
++	return 0;
++}
++
++/* Maximum loop count waiting for new voltage to take effect */
++#define MAX_LOOP_WAIT_NEW_VOL		100
++/* Maximum loop count waiting for the voltage to be stable */
++#define MAX_LOOP_WAIT_VOL_STABLE	100
++/*
++ * read_voltage from sensor on I2C bus
++ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
++ * another reading
++ */
++#define NUM_READINGS    4       /* prefer to be power of 2 for efficiency */
++
++/* If an INA220 chip is available, we can use it to read back the voltage
++ * as it may have a higher accuracy than the IR chip for the same purpose
++ */
++#ifdef CONFIG_VOL_MONITOR_INA220
++#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
++#define ADC_MIN_ACCURACY	4
++#else
++#define WAIT_FOR_ADC	138	/* wait for 138 microseconds for ADC */
++#define ADC_MIN_ACCURACY	4
++#endif
++
++/* read the current value of the LTC Regulator Voltage */
++static int read_voltage_from_LTC(int i2caddress)
++{
++	int  ret, vcode = 0;
++	u8 chan = PWM_CHANNEL0;
++
++	/* select the PAGE 0 using PMBus commands PAGE for VDD*/
++	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
++			PMBUS_CMD_PAGE, 1, &chan, 1);
++	if (ret) {
++		printf("VID: failed to select VDD Page 0\n");
++		return ret;
++	}
++
++	/*read the output voltage using PMBus command READ_VOUT*/
++	ret = i2c_read(I2C_VOL_MONITOR_ADDR,
++		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
++	if (ret) {
++		printf("VID: failed to read the volatge\n");
++		return ret;
++	}
++
++	/* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
++	vcode = DIV_ROUND_UP(vcode * 1000, 4096);
++
++	return vcode;
++}
++
++static int read_voltage(int i2caddress)
++{
++	int voltage_read;
++	voltage_read = read_voltage_from_LTC(i2caddress);
++	return voltage_read;
++}
++
++/* this function sets the VDD and returns the value set */
++static int set_voltage_to_LTC(int i2caddress, int vdd)
++{
++	int ret, vdd_last, vdd_target = vdd;
++	int count = 100, temp = 0;
++
++	/* Scale up to the LTC resolution is 1/4096V */
++	vdd = (vdd * 4096) / 1000;
++
++	/* 5-byte buffer which needs to be sent following the
++	 * PMBus command PAGE_PLUS_WRITE.
++	 */
++	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
++			vdd & 0xFF, (vdd & 0xFF00) >> 8};
++
++	/* Write the desired voltage code to the regulator */
++	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
++			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
++	if (ret) {
++		printf("VID: I2C failed to write to the volatge regulator\n");
++		return -1;
++	}
++
++	/* Wait for the volatge to get to the desired value */
++	do {
++		vdd_last = read_voltage_from_LTC(i2caddress);
++		if (vdd_last < 0) {
++			printf("VID: Couldn't read sensor abort VID adjust\n");
++			return -1;
++		}
++		count--;
++		temp = vdd_last - vdd_target;
++	} while ((abs(temp) > 2)  && (count > 0));
++
++	return vdd_last;
++}
++
++static int set_voltage(int i2caddress, int vdd)
++{
++	int vdd_last = -1;
++
++	vdd_last = set_voltage_to_LTC(i2caddress, vdd);
++	return vdd_last;
++}
++
++int adjust_vdd(ulong vdd_override)
++{
++	int re_enable = disable_interrupts();
++	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++	u32 fusesr;
++	u8 vid;
++	int vdd_target, vdd_current, vdd_last;
++	int ret, i2caddress;
++	unsigned long vdd_string_override;
++	char *vdd_string;
++	static const u16 vdd[32] = {
++		8250,
++		7875,
++		7750,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		8000,
++		8125,
++		8250,
++		0,      /* reserved */
++		8500,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++	};
++	struct vdd_drive {
++		u8 vid;
++		unsigned voltage;
++	};
++	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
++	if (ret) {
++		debug("VID: I2C failed to switch channel\n");
++		ret = -1;
++		goto exit;
++	}
++	/* get the voltage ID from fuse status register */
++	fusesr = in_le32(&gur->dcfg_fusesr);
++	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
++		FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
++	if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
++		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
++			FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
++	}
++	vdd_target = vdd[vid];
++	printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target);
++
++	/* check override variable for overriding VDD */
++	vdd_string = env_get(CONFIG_VID_FLS_ENV);
++	if (vdd_override == 0 && vdd_string &&
++	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
++		vdd_override = vdd_string_override;
++
++	if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
++		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
++		debug("VDD override is %lu\n", vdd_override);
++	} else if (vdd_override != 0) {
++		printf("Invalid value.\n");
++	}
++
++	/* divide and round up by 10 to get a value in mV */
++	vdd_target = DIV_ROUND_UP(vdd_target, 10);
++	if (vdd_target == 0) {
++		debug("VID: VID not used\n");
++		ret = 0;
++		goto exit;
++	} else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
++		/* Check vdd_target is in valid range */
++		printf("VID: Target VID %d mV is not in range.\n",
++		       vdd_target);
++		ret = -1;
++		goto exit;
++	} else {
++		debug("VID: vid = %d mV\n", vdd_target);
++	}
++
++	/*
++	 * Read voltage monitor to check real voltage.
++	 */
++	vdd_last = read_voltage(i2caddress);
++	if (vdd_last < 0) {
++		printf("VID: Couldn't read sensor abort VID adjustment\n");
++		ret = -1;
++		goto exit;
++	}
++	vdd_current = vdd_last;
++	debug("VID: Core voltage is currently at %d mV\n", vdd_last);
++
++	/* Set the target voltage */
++	vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
++	if (board_adjust_vdd(vdd_target) < 0) {
++		ret = -1;
++		goto exit;
++	}
++
++	if (vdd_last > 0)
++		printf("VID: Core voltage after adjustment is at %d mV\n",
++		       vdd_last);
++	else
++		ret = -1;
++exit:
++	if (re_enable)
++		enable_interrupts();
++	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
++	return ret;
++}
++
++static int print_vdd(void)
++{
++	int vdd_last, ret, i2caddress;
++
++	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
++	if (ret) {
++		debug("VID : I2c failed to switch channel\n");
++		return -1;
++	}
++	/*
++	 * Read voltage monitor to check real voltage.
++	 */
++	vdd_last = read_voltage(i2caddress);
++	if (vdd_last < 0) {
++		printf("VID: Couldn't read sensor abort VID adjustment\n");
++		goto exit;
++	}
++	printf("VID: Core voltage is at %d mV\n", vdd_last);
++exit:
++	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
++
++	return ret < 0 ? -1 : 0;
++
++}
++
++static int do_vdd_override(cmd_tbl_t *cmdtp,
++			   int flag, int argc,
++			   char * const argv[])
++{
++	ulong override;
++
++	if (argc < 2)
++		return CMD_RET_USAGE;
++
++	if (!strict_strtoul(argv[1], 10, &override))
++		adjust_vdd(override);   /* the value is checked by callee */
++	else
++		return CMD_RET_USAGE;
++	return 0;
++}
++
++static int do_vdd_read(cmd_tbl_t *cmdtp,
++			 int flag, int argc,
++			 char * const argv[])
++{
++	if (argc < 1)
++		return CMD_RET_USAGE;
++	print_vdd();
++
++	return 0;
++}
++
++U_BOOT_CMD(
++	vdd_override, 2, 0, do_vdd_override,
++	"override VDD",
++	" - override with the voltage specified in mV, eg. 1050"
++);
++
++U_BOOT_CMD(
++	vdd_read, 1, 0, do_vdd_read,
++	"read VDD",
++	" - Read the voltage specified in mV"
++)
+diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
+new file mode 100644
+index 0000000000..99778e9a93
+--- /dev/null
++++ b/board/solidrun/common/vid.h
+@@ -0,0 +1,23 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ */
++
++#ifndef __VID_H_
++#define __VID_H_
++
++#define IR36021_LOOP1_MANUAL_ID_OFFSET	0x6A
++#define IR36021_LOOP1_VOUT_OFFSET	0x9A
++#define IR36021_MFR_ID_OFFSET		0x92
++#define IR36021_MFR_ID			0x43
++#define IR36021_INTEL_MODE_OOFSET	0x14
++#define IR36021_MODE_MASK		0x20
++#define IR36021_INTEL_MODE		0x00
++#define IR36021_AMD_MODE		0x20
++
++/* step the IR regulator in 5mV increments */
++#define IR_VDD_STEP_DOWN		5
++#define IR_VDD_STEP_UP			5
++int adjust_vdd(ulong vdd_override);
++
++#endif  /* __VID_H_ */
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch

+From f8ac0b82bf2af732251419f05b9058e78ca2dbec Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:37:22 +0300
+Subject: [PATCH 5/6] armv8: lx2160acex7: lx2160acex device tree
+
+Based on NXP's LX2160ARDB device tree; it defines -
+1. MX35X based SPI flash
+2. SDHC0 (SD card) and SDHC1 (eMMC)
+3. 4 SATA ports that depending on SERDES configuration they can get
+connected to external SATA drives
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 0000000000..4fbcaafb0e
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,63 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * SolidRun LX2160ACEX7 device tree source
++ *
++ * Author:	Rabeeh Khoury <rabeeh@solid-run.com>
++ *
++ * Copyright 2019 SolidRun ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++	model = "SolidRun LX2160ACEX7 COM express type 7 based board";
++	compatible = "fsl,lx2160acex7", "fsl,lx2160a";
++
++	aliases {
++		spi0 = &fspi;
++	};
++};
++
++&fspi {
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: MT35XU512ABA1G12@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spi-flash";
++		spi-max-frequency = <50000000>;
++		reg = <0>;
++		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++		fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
++		fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
++	};
++
++};
++
++&esdhc0 {
++	status = "okay";
++};
++
++&esdhc1 {
++	status = "okay";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&sata2 {
++	status = "okay";
++};
++
++&sata3 {
++	status = "okay";
++};
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0006-armv8-lx2160acex7-board-support-files.patch

+From 462ecf12a531de55b68fd846c10aa5487934479b Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:45:24 +0300
+Subject: [PATCH 6/6] armv8: lx2160acex7: board support files
+
+The lx2160acex7 board support files does the following -
+1. Initializes 1GBps PHY address according to SERDES1 block config.
+2. Sets uart0 as the console
+3. Sets EMC2301 PWM fan controller to it's default value
+4. Misc FDT fixups prior to booting Linux
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/Kconfig           |  22 ++
+ board/solidrun/lx2160a/MAINTAINERS       |   8 +
+ board/solidrun/lx2160a/Makefile          |   9 +
+ board/solidrun/lx2160a/ddr.c             |  20 ++
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 104 ++++++++
+ board/solidrun/lx2160a/lx2160a.c         | 288 +++++++++++++++++++++++
+ 6 files changed, 451 insertions(+)
+ create mode 100644 board/solidrun/lx2160a/Kconfig
+ create mode 100644 board/solidrun/lx2160a/MAINTAINERS
+ create mode 100644 board/solidrun/lx2160a/Makefile
+ create mode 100644 board/solidrun/lx2160a/ddr.c
+ create mode 100644 board/solidrun/lx2160a/eth_lx2160acex7.c
+ create mode 100644 board/solidrun/lx2160a/lx2160a.c
+
+diff --git a/board/solidrun/lx2160a/Kconfig b/board/solidrun/lx2160a/Kconfig
+new file mode 100644
+index 0000000000..85abac9bfc
+--- /dev/null
++++ b/board/solidrun/lx2160a/Kconfig
+@@ -0,0 +1,22 @@
++if TARGET_LX2160ACEX7
++
++config SYS_BOARD
++	default "lx2160a"
++
++config SYS_VENDOR
++	default "solidrun"
++
++config SYS_SOC
++	default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++	default "lx2160acex7"
++
++config EMC2301
++	bool "Fan controller"
++	help
++	 Enable the EMC2301 fan controller for configuration of fan
++	 speed.
++
++source "board/freescale/common/Kconfig"
++endif
+diff --git a/board/solidrun/lx2160a/MAINTAINERS b/board/solidrun/lx2160a/MAINTAINERS
+new file mode 100644
+index 0000000000..688ff66afa
+--- /dev/null
++++ b/board/solidrun/lx2160a/MAINTAINERS
+@@ -0,0 +1,8 @@
++LX2160ACEX7 BOARD
++M:	Rabeeh Khoury <rabeeh@solid-run.com>
++S:	Maintained
++F:	board/solidrun/lx2160a/
++F:	include/configs/lx2160a_common.h
++F:	include/configs/lx2160acex7.h
++F:	configs/lx2160acex7_tfa_defconfig
++F:	arch/arm/dts/fsl-lx2160a-cex7.dts
+diff --git a/board/solidrun/lx2160a/Makefile b/board/solidrun/lx2160a/Makefile
+new file mode 100644
+index 0000000000..c92266f322
+--- /dev/null
++++ b/board/solidrun/lx2160a/Makefile
+@@ -0,0 +1,9 @@
++#
++# Copyright 2019 SolidRun ltd.
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++obj-y += lx2160a.o
++obj-y += ddr.o
++obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o
+diff --git a/board/solidrun/lx2160a/ddr.c b/board/solidrun/lx2160a/ddr.c
+new file mode 100644
+index 0000000000..9c7bd10475
+--- /dev/null
++++ b/board/solidrun/lx2160a/ddr.c
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#include <common.h>
++#include <fsl_ddr_sdram.h>
++#include <fsl_ddr_dimm_params.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int fsl_initdram(void)
++{
++	gd->ram_size = tfa_get_dram_size();
++
++	if (!gd->ram_size)
++		gd->ram_size = fsl_ddr_sdram_size();
++
++	return 0;
++}
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+new file mode 100644
+index 0000000000..97e414838f
+--- /dev/null
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -0,0 +1,104 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ *
++ */
++
++#include <common.h>
++#include <command.h>
++#include <netdev.h>
++#include <malloc.h>
++#include <fsl_mdio.h>
++#include <miiphy.h>
++#include <phy.h>
++#include <fm_eth.h>
++#include <asm/io.h>
++#include <exports.h>
++#include <asm/arch/fsl_serdes.h>
++#include <fsl-mc/fsl_mc.h>
++#include <fsl-mc/ldpaa_wriop.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_eth_init(bd_t *bis)
++{
++#if defined(CONFIG_FSL_MC_ENET)
++	struct memac_mdio_info mdio_info;
++	struct memac_mdio_controller *reg;
++	int i, interface;
++	struct mii_dev *dev;
++	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++	u32 srds_s1;
++
++	srds_s1 = in_le32(&gur->rcwsr[28]) &
++				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
++	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
++
++	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
++	mdio_info.regs = reg;
++	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
++
++	/* Register the EMI 1 */
++	fm_memac_mdio_init(bis, &mdio_info);
++
++	wriop_set_phy_address(WRIOP1_DPMAC17, 0,
++			      RGMII_PHY_ADDR1);
++	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
++	switch (srds_s1) {
++	case 3:
++	case 5:
++	case 8:
++	case 13:
++	case 14:
++	case 15:
++	case 17:
++	case 20:
++	case 23:
++		wriop_set_phy_address(WRIOP1_DPMAC17, 0,
++				      RGMII_PHY_ADDR1);
++		break;
++
++	default:
++		printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
++		       srds_s1);
++		goto next;
++	}
++	for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
++		interface = wriop_get_enet_if(i);
++		switch (interface) {
++		case PHY_INTERFACE_MODE_RGMII:
++		case PHY_INTERFACE_MODE_RGMII_ID:
++			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
++			wriop_set_mdio(i, dev);
++			break;
++		default:
++			break;
++		}
++	}
++
++next:
++	cpu_eth_init(bis);
++#endif /* CONFIG_FSL_MC_ENET */
++
++	return pci_eth_init(bis);
++}
++
++#if defined(CONFIG_RESET_PHY_R)
++void reset_phy(void)
++{
++#if defined(CONFIG_FSL_MC_ENET)
++	mc_env_boot();
++#endif
++}
++#endif /* CONFIG_RESET_PHY_R */
++
++int fdt_fixup_board_phy(void *fdt)
++{
++	int mdio_offset;
++	int ret;
++	struct mii_dev *dev;
++
++	ret = 0;
++
++	return ret;
++}
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+new file mode 100644
+index 0000000000..b0d9f1012e
+--- /dev/null
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -0,0 +1,288 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#include <common.h>
++#include <dm.h>
++#include <dm/platform_data/serial_pl01x.h>
++#include <i2c.h>
++#include <malloc.h>
++#include <errno.h>
++#include <netdev.h>
++#include <fsl_ddr.h>
++#include <fsl_sec.h>
++#include <asm/io.h>
++#include <fdt_support.h>
++#include <linux/libfdt.h>
++#include <fsl-mc/fsl_mc.h>
++#include <environment.h>
++#include <efi_loader.h>
++#include <asm/arch/mmu.h>
++#include <hwconfig.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/soc.h>
++#include "../../freescale/common/vid.h"
++#include <fsl_immap.h>
++
++#ifdef CONFIG_EMC2301
++#include "../common/emc2301.h"
++#endif
++
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static struct pl01x_serial_platdata serial0 = {
++#if CONFIG_CONS_INDEX == 0
++	.base = CONFIG_SYS_SERIAL0,
++#elif CONFIG_CONS_INDEX == 1
++	.base = CONFIG_SYS_SERIAL1,
++#else
++#error "Unsupported console index value."
++#endif
++	.type = TYPE_PL011,
++};
++
++U_BOOT_DEVICE(nxp_serial0) = {
++	.name = "serial_pl01x",
++	.platdata = &serial0,
++};
++
++static struct pl01x_serial_platdata serial1 = {
++	.base = CONFIG_SYS_SERIAL1,
++	.type = TYPE_PL011,
++};
++
++U_BOOT_DEVICE(nxp_serial1) = {
++	.name = "serial_pl01x",
++	.platdata = &serial1,
++};
++
++int select_i2c_ch_pca9547(u8 ch)
++{
++	int ret;
++
++	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++	if (ret) {
++		puts("PCA: failed to select proper channel\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void uart_get_clock(void)
++{
++	serial0.clock = get_serial_clock();
++	serial1.clock = get_serial_clock();
++}
++
++int board_early_init_f(void)
++{
++#ifdef CONFIG_SYS_I2C_EARLY_INIT
++	i2c_early_init_f();
++#endif
++	/* get required clock for UART IP */
++	uart_get_clock();
++
++#ifdef CONFIG_EMC2301
++	select_i2c_ch_pca9547(I2C_MUX_CH_EMC2301);
++	emc2301_init();
++	set_fan_speed(I2C_EMC2301_PWM);
++	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++#endif
++	fsl_lsch3_early_init_f();
++	return 0;
++}
++
++#ifdef CONFIG_OF_BOARD_FIXUP
++int board_fix_fdt(void *fdt)
++{
++	return 0;
++}
++#endif
++
++int esdhc_status_fixup(void *blob, const char *compat)
++{
++	/* Enable both esdhc DT nodes for LX2160ARDB */
++	do_fixup_by_compat(blob, compat, "status", "okay",
++			   sizeof("okay"), 1);
++	return 0;
++}
++
++#if defined(CONFIG_VID)
++int i2c_multiplexer_select_vid_channel(u8 channel)
++{
++	return select_i2c_ch_pca9547(channel);
++}
++
++#endif
++
++int checkboard(void)
++{
++	enum boot_src src = get_boot_src();
++	char buf[64];
++	cpu_name(buf);
++	printf("Board: %s-CEX7, ", buf);
++
++	if (src == BOOT_SOURCE_SD_MMC) {
++		puts("SD\n");
++	}
++	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
++	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
++	puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
++	return 0;
++}
++
++int config_board_mux(void)
++{
++	return 0;
++}
++
++unsigned long get_board_sys_clk(void)
++{
++	return 100000000;
++}
++
++unsigned long get_board_ddr_clk(void)
++{
++	return 100000000;
++}
++
++int board_init(void)
++{
++#ifdef CONFIG_ENV_IS_NOWHERE
++	gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++
++#ifdef CONFIG_FSL_CAAM
++	sec_init();
++#endif
++
++	return 0;
++}
++
++void detail_board_ddr_info(void)
++{
++	int i;
++	u64 ddr_size = 0;
++
++	puts("\nDDR    ");
++	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
++		ddr_size += gd->bd->bi_dram[i].size;
++	print_size(ddr_size, "");
++	print_ddr_info(0);
++}
++
++#if defined(CONFIG_ARCH_MISC_INIT)
++int arch_misc_init(void)
++{
++	config_board_mux();
++
++	return 0;
++}
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++extern int fdt_fixup_board_phy(void *fdt);
++
++void fdt_fixup_board_enet(void *fdt)
++{
++	int offset;
++
++	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
++
++	if (offset < 0)
++		offset = fdt_path_offset(fdt, "/fsl-mc");
++
++	if (offset < 0) {
++		printf("%s: fsl-mc node not found in device tree (error %d)\n",
++		       __func__, offset);
++		return;
++	}
++
++	if (get_mc_boot_status() == 0 &&
++	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
++		fdt_status_okay(fdt, offset);
++		fdt_fixup_board_phy(fdt);
++	} else {
++		fdt_status_fail(fdt, offset);
++	}
++}
++
++void board_quiesce_devices(void)
++{
++	fsl_mc_ldpaa_exit(gd->bd);
++}
++#endif
++
++#ifdef CONFIG_OF_BOARD_SETUP
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++	int i;
++	bool mc_memory_bank = false;
++
++	u64 *base;
++	u64 *size;
++	u64 mc_memory_base = 0;
++	u64 mc_memory_size = 0;
++	u16 total_memory_banks;
++
++	ft_cpu_setup(blob, bd);
++
++	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
++
++	if (mc_memory_base != 0)
++		mc_memory_bank = true;
++
++	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
++
++	base = calloc(total_memory_banks, sizeof(u64));
++	size = calloc(total_memory_banks, sizeof(u64));
++
++	/* fixup DT for the three GPP DDR banks */
++	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
++		base[i] = gd->bd->bi_dram[i].start;
++		size[i] = gd->bd->bi_dram[i].size;
++	}
++
++#ifdef CONFIG_RESV_RAM
++	/* reduce size if reserved memory is within this bank */
++	if (gd->arch.resv_ram >= base[0] &&
++	    gd->arch.resv_ram < base[0] + size[0])
++		size[0] = gd->arch.resv_ram - base[0];
++	else if (gd->arch.resv_ram >= base[1] &&
++		 gd->arch.resv_ram < base[1] + size[1])
++		size[1] = gd->arch.resv_ram - base[1];
++	else if (gd->arch.resv_ram >= base[2] &&
++		 gd->arch.resv_ram < base[2] + size[2])
++		size[2] = gd->arch.resv_ram - base[2];
++#endif
++
++	if (mc_memory_base != 0) {
++		for (i = 0; i <= total_memory_banks; i++) {
++			if (base[i] == 0 && size[i] == 0) {
++				base[i] = mc_memory_base;
++				size[i] = mc_memory_size;
++				break;
++			}
++		}
++	}
++
++	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
++
++#ifdef CONFIG_USB
++	fsl_fdt_fixup_dr_usb(blob, bd);
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++	fdt_fsl_mc_fixup_iommu_map_entry(blob);
++	fdt_fixup_board_enet(blob);
++#endif
++
++	return 0;
++}
++#endif
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0008-uboot-add-nvme-commands-and-for-distroboot.patch

+From a1fddcaae71a95bd4b9963c9000b9c88b6d152d5 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 11 Nov 2019 23:45:31 +0200
+Subject: [PATCH] uboot - add nvme commands and for distroboot
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 2 ++
+ include/configs/lx2160a_common.h  | 3 ++-
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index d59de7d054..3891d2a7c4 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_CACHE=y
++CONFIG_CMD_NVME=y
++CONFIG_NVME=y
+ CONFIG_MP=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 34cc29685d..7c2d749a9e 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -306,6 +306,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	func(MMC, mmc, 0) \
+ 	func(MMC, mmc, 1) \
+ 	func(SCSI, scsi, 0) \
++	func(NVME, nvme, 0) \
+ 	func(DHCP, dhcp, na)
+ #include <config_distro_bootcmd.h>
+ 
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch

+From 4a5e1552f13acc1e8ee91b456ea37e9d39bdae01 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 13:32:09 +0200
+Subject: [PATCH] armv8: lx2160acex7: Fix booting from NVMe drives
+
+Currently NVMe is not initialized so u-boot fails to read kernel from
+NVMe drive. This patch modifies default environment so it initializes
+NVMe as part of default startup script...
+
+Credit to Damjan Marion <dmarion@me.com> on fixing that on LSDK-19.09.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index bacad51bfb..cee462ef63 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -248,6 +248,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	BOOTENV					\
+ 	"mcmemsize=0x70000000\0"		\
+ 	XSPI_MC_INIT_CMD				\
++	"nvme_need_init=true\0" \
+ 	"scan_dev_for_boot_part="		\
+ 		"part list ${devtype} ${devnum} devplist; "	\
+ 		"env exists devplist || setenv devplist 1; "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0011-lx2160acex7-common-update-vid-to-LSDK-20.12.patch

+From 6f3137459f4093e70cfac8d1b51806f5a111cd52 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 12 Jan 2021 12:10:05 +0200
+Subject: [PATCH 2/2] lx2160acex7: common: update vid to LSDK-20.12
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/common/vid.c | 692 +++++++++++++++++++++++++++++++++++-
+ board/solidrun/common/vid.h |  20 ++
+ 2 files changed, 703 insertions(+), 9 deletions(-)
+
+diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
+index cc81e80c37..0256d035eb 100644
+--- a/board/solidrun/common/vid.c
++++ b/board/solidrun/common/vid.c
+@@ -1,11 +1,14 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2014 Freescale Semiconductor, Inc.
+- * Copyright 2018 NXP
++ * Copyright 2020 NXP
+  */
++
+ #include <common.h>
+ #include <command.h>
++#include <env.h>
+ #include <i2c.h>
++#include <irq_func.h>
+ #include <asm/io.h>
+ #ifdef CONFIG_FSL_LSCH2
+ #include <asm/arch/immap_lsch2.h>
+@@ -38,6 +41,52 @@ int __weak board_adjust_vdd(int vdd)
+ 	return 0;
+ }
+ 
++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
++	defined(CONFIG_VOL_MONITOR_IR36021_READ)
++/*
++ * Get the i2c address configuration for the IR regulator chip
++ *
++ * There are some variance in the RDB HW regarding the I2C address configuration
++ * for the IR regulator chip, which is likely a problem of external resistor
++ * accuracy. So we just check each address in a hopefully non-intrusive mode
++ * and use the first one that seems to work
++ *
++ * The IR chip can show up under the following addresses:
++ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
++ * 0x09 (Verified on T1040RDB-PA)
++ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
++ */
++static int find_ir_chip_on_i2c(void)
++{
++	int i2caddress;
++	int ret;
++	u8 byte;
++	int i;
++	const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
++#ifdef CONFIG_DM_I2C
++	struct udevice *dev;
++#endif
++
++	/* Check all the address */
++	for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
++		i2caddress = ir_i2c_addr[i];
++#ifndef CONFIG_DM_I2C
++		ret = i2c_read(i2caddress,
++			       IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
++			       sizeof(byte));
++#else
++		ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
++		if (!ret)
++			ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
++					  (void *)&byte, sizeof(byte));
++#endif
++		if ((ret >= 0) && (byte == IR36021_MFR_ID))
++			return i2caddress;
++	}
++	return -1;
++}
++#endif
++
+ /* Maximum loop count waiting for new voltage to take effect */
+ #define MAX_LOOP_WAIT_NEW_VOL		100
+ /* Maximum loop count waiting for the voltage to be stable */
+@@ -60,23 +109,135 @@ int __weak board_adjust_vdd(int vdd)
+ #define ADC_MIN_ACCURACY	4
+ #endif
+ 
++#ifdef CONFIG_VOL_MONITOR_INA220
++static int read_voltage_from_INA220(int i2caddress)
++{
++	int i, ret, voltage_read = 0;
++	u16 vol_mon;
++	u8 buf[2];
++#ifdef CONFIG_DM_I2C
++	struct udevice *dev;
++#endif
++
++	for (i = 0; i < NUM_READINGS; i++) {
++#ifndef CONFIG_DM_I2C
++		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
++			       I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
++			       (void *)&buf, 2);
++#else
++		ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
++		if (!ret)
++			ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
++					  (void *)&buf, 2);
++#endif
++		if (ret) {
++			printf("VID: failed to read core voltage\n");
++			return ret;
++		}
++		vol_mon = (buf[0] << 8) | buf[1];
++		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
++			printf("VID: Core voltage sensor error\n");
++			return -1;
++		}
++		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
++		/* LSB = 4mv */
++		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
++		udelay(WAIT_FOR_ADC);
++	}
++	/* calculate the average */
++	voltage_read /= NUM_READINGS;
++
++	return voltage_read;
++}
++#endif
++
++/* read voltage from IR */
++#ifdef CONFIG_VOL_MONITOR_IR36021_READ
++static int read_voltage_from_IR(int i2caddress)
++{
++	int i, ret, voltage_read = 0;
++	u16 vol_mon;
++	u8 buf;
++#ifdef CONFIG_DM_I2C
++	struct udevice *dev;
++#endif
++
++	for (i = 0; i < NUM_READINGS; i++) {
++#ifndef CONFIG_DM_I2C
++		ret = i2c_read(i2caddress,
++			       IR36021_LOOP1_VOUT_OFFSET,
++			       1, (void *)&buf, 1);
++#else
++		ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
++		if (!ret)
++			ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
++					  (void *)&buf, 1);
++#endif
++		if (ret) {
++			printf("VID: failed to read vcpu\n");
++			return ret;
++		}
++		vol_mon = buf;
++		if (!vol_mon) {
++			printf("VID: Core voltage sensor error\n");
++			return -1;
++		}
++		debug("VID: bus voltage reads 0x%02x\n", vol_mon);
++		/* Resolution is 1/128V. We scale up here to get 1/128mV
++		 * and divide at the end
++		 */
++		voltage_read += vol_mon * 1000;
++		udelay(WAIT_FOR_ADC);
++	}
++	/* Scale down to the real mV as IR resolution is 1/128V, rounding up */
++	voltage_read = DIV_ROUND_UP(voltage_read, 128);
++
++	/* calculate the average */
++	voltage_read /= NUM_READINGS;
++
++	/* Compensate for a board specific voltage drop between regulator and
++	 * SoC before converting into an IR VID value
++	 */
++	voltage_read -= board_vdd_drop_compensation();
++
++	return voltage_read;
++}
++#endif
++
++#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
+ /* read the current value of the LTC Regulator Voltage */
+ static int read_voltage_from_LTC(int i2caddress)
+ {
+ 	int  ret, vcode = 0;
+ 	u8 chan = PWM_CHANNEL0;
+ 
++#ifndef CONFIG_DM_I2C
+ 	/* select the PAGE 0 using PMBus commands PAGE for VDD*/
+ 	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ 			PMBUS_CMD_PAGE, 1, &chan, 1);
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
++#endif
+ 	if (ret) {
+ 		printf("VID: failed to select VDD Page 0\n");
+ 		return ret;
+ 	}
+ 
++#ifndef CONFIG_DM_I2C
+ 	/*read the output voltage using PMBus command READ_VOUT*/
+ 	ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
++#else
++	ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
++	if (ret) {
++		printf("VID: failed to read the volatge\n");
++		return ret;
++	}
++#endif
+ 	if (ret) {
+ 		printf("VID: failed to read the volatge\n");
+ 		return ret;
+@@ -87,19 +248,137 @@ static int read_voltage_from_LTC(int i2caddress)
+ 
+ 	return vcode;
+ }
++#endif
+ 
+ static int read_voltage(int i2caddress)
+ {
+ 	int voltage_read;
++#ifdef CONFIG_VOL_MONITOR_INA220
++	voltage_read = read_voltage_from_INA220(i2caddress);
++#elif defined CONFIG_VOL_MONITOR_IR36021_READ
++	voltage_read = read_voltage_from_IR(i2caddress);
++#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
+ 	voltage_read = read_voltage_from_LTC(i2caddress);
++#else
++	return -1;
++#endif
+ 	return voltage_read;
+ }
+ 
++#ifdef CONFIG_VOL_MONITOR_IR36021_SET
++/*
++ * We need to calculate how long before the voltage stops to drop
++ * or increase. It returns with the loop count. Each loop takes
++ * several readings (WAIT_FOR_ADC)
++ */
++static int wait_for_new_voltage(int vdd, int i2caddress)
++{
++	int timeout, vdd_current;
++
++	vdd_current = read_voltage(i2caddress);
++	/* wait until voltage starts to reach the target. Voltage slew
++	 * rates by typical regulators will always lead to stable readings
++	 * within each fairly long ADC interval in comparison to the
++	 * intended voltage delta change until the target voltage is
++	 * reached. The fairly small voltage delta change to any target
++	 * VID voltage also means that this function will always complete
++	 * within few iterations. If the timeout was ever reached, it would
++	 * point to a serious failure in the regulator system.
++	 */
++	for (timeout = 0;
++	     abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
++	     timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
++		vdd_current = read_voltage(i2caddress);
++	}
++	if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
++		printf("VID: Voltage adjustment timeout\n");
++		return -1;
++	}
++	return timeout;
++}
++
++/*
++ * this function keeps reading the voltage until it is stable or until the
++ * timeout expires
++ */
++static int wait_for_voltage_stable(int i2caddress)
++{
++	int timeout, vdd_current, vdd;
++
++	vdd = read_voltage(i2caddress);
++	udelay(NUM_READINGS * WAIT_FOR_ADC);
++
++	/* wait until voltage is stable */
++	vdd_current = read_voltage(i2caddress);
++	/* The maximum timeout is
++	 * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
++	 */
++	for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
++	     abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
++	     timeout > 0; timeout--) {
++		vdd = vdd_current;
++		udelay(NUM_READINGS * WAIT_FOR_ADC);
++		vdd_current = read_voltage(i2caddress);
++	}
++	if (timeout == 0)
++		return -1;
++	return vdd_current;
++}
++
++/* Set the voltage to the IR chip */
++static int set_voltage_to_IR(int i2caddress, int vdd)
++{
++	int wait, vdd_last;
++	int ret;
++	u8 vid;
++
++	/* Compensate for a board specific voltage drop between regulator and
++	 * SoC before converting into an IR VID value
++	 */
++	vdd += board_vdd_drop_compensation();
++#ifdef CONFIG_FSL_LSCH2
++	vid = DIV_ROUND_UP(vdd - 265, 5);
++#else
++	vid = DIV_ROUND_UP(vdd - 245, 5);
++#endif
++
++#ifndef CONFIG_DM_I2C
++	ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
++			1, (void *)&vid, sizeof(vid));
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
++				   (void *)&vid, sizeof(vid));
++
++#endif
++	if (ret) {
++		printf("VID: failed to write VID\n");
++		return -1;
++	}
++	wait = wait_for_new_voltage(vdd, i2caddress);
++	if (wait < 0)
++		return -1;
++	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
++
++	vdd_last = wait_for_voltage_stable(i2caddress);
++	if (vdd_last < 0)
++		return -1;
++	debug("VID: Current voltage is %d mV\n", vdd_last);
++	return vdd_last;
++}
++
++#endif
++
++#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+ /* this function sets the VDD and returns the value set */
+ static int set_voltage_to_LTC(int i2caddress, int vdd)
+ {
+ 	int ret, vdd_last, vdd_target = vdd;
+ 	int count = 100, temp = 0;
++	unsigned char value;
+ 
+ 	/* Scale up to the LTC resolution is 1/4096V */
+ 	vdd = (vdd * 4096) / 1000;
+@@ -111,8 +390,52 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
+ 			vdd & 0xFF, (vdd & 0xFF00) >> 8};
+ 
+ 	/* Write the desired voltage code to the regulator */
++#ifndef CONFIG_DM_I2C
++	/* Check write protect state */
++	ret = i2c_read(I2C_VOL_MONITOR_ADDR,
++		       PMBUS_CMD_WRITE_PROTECT, 1,
++		       (void *)&value, sizeof(value));
++	if (ret)
++		goto exit;
++
++	if (value != EN_WRITE_ALL_CMD) {
++		value = EN_WRITE_ALL_CMD;
++		ret = i2c_write(I2C_VOL_MONITOR_ADDR,
++				PMBUS_CMD_WRITE_PROTECT, 1,
++				(void *)&value, sizeof(value));
++		if (ret)
++			goto exit;
++	}
++
+ 	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+-			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
++			PMBUS_CMD_PAGE_PLUS_WRITE, 1,
++			(void *)&buff, sizeof(buff));
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
++	if (!ret) {
++		/* Check write protect state */
++		ret = dm_i2c_read(dev,
++				  PMBUS_CMD_WRITE_PROTECT,
++				  (void *)&value, sizeof(value));
++		if (ret)
++			goto exit;
++
++		if (value != EN_WRITE_ALL_CMD) {
++			value = EN_WRITE_ALL_CMD;
++			ret = dm_i2c_write(dev,
++					   PMBUS_CMD_WRITE_PROTECT,
++					   (void *)&value, sizeof(value));
++			if (ret)
++				goto exit;
++		}
++
++		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
++				   (void *)&buff, sizeof(buff));
++	}
++#endif
++exit:
+ 	if (ret) {
+ 		printf("VID: I2C failed to write to the volatge regulator\n");
+ 		return -1;
+@@ -131,25 +454,39 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
+ 
+ 	return vdd_last;
+ }
++#endif
+ 
+ static int set_voltage(int i2caddress, int vdd)
+ {
+ 	int vdd_last = -1;
+ 
++#ifdef CONFIG_VOL_MONITOR_IR36021_SET
++	vdd_last = set_voltage_to_IR(i2caddress, vdd);
++#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
+ 	vdd_last = set_voltage_to_LTC(i2caddress, vdd);
++#else
++	#error Specific voltage monitor must be defined
++#endif
+ 	return vdd_last;
+ }
+ 
++#ifdef CONFIG_FSL_LSCH3
+ int adjust_vdd(ulong vdd_override)
+ {
+ 	int re_enable = disable_interrupts();
+ 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ 	u32 fusesr;
++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
++	defined(CONFIG_VOL_MONITOR_IR36021_READ)
++	u8 vid, buf;
++#else
+ 	u8 vid;
++#endif
+ 	int vdd_target, vdd_current, vdd_last;
+-	int ret, i2caddress;
++	int ret, i2caddress = 0;
+ 	unsigned long vdd_string_override;
+ 	char *vdd_string;
++#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
+ 	static const u16 vdd[32] = {
+ 		8250,
+ 		7875,
+@@ -184,16 +521,129 @@ int adjust_vdd(ulong vdd_override)
+ 		0,      /* reserved */
+ 		0,      /* reserved */
+ 	};
++#else
++#ifdef CONFIG_ARCH_LS1088A
++	static const uint16_t vdd[32] = {
++		10250,
++		9875,
++		9750,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		9000,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		10000,  /* 1.0000V */
++		10125,
++		10250,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++	};
++
++#else
++	static const uint16_t vdd[32] = {
++		10500,
++		0,      /* reserved */
++		9750,
++		0,      /* reserved */
++		9500,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		9000,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		10000,  /* 1.0000V */
++		0,      /* reserved */
++		10250,
++		0,      /* reserved */
++		10500,
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++		0,      /* reserved */
++	};
++#endif
++#endif
+ 	struct vdd_drive {
+ 		u8 vid;
+ 		unsigned voltage;
+ 	};
++
+ 	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ 	if (ret) {
+ 		debug("VID: I2C failed to switch channel\n");
+ 		ret = -1;
+ 		goto exit;
+ 	}
++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
++	defined(CONFIG_VOL_MONITOR_IR36021_READ)
++	ret = find_ir_chip_on_i2c();
++	if (ret < 0) {
++		printf("VID: Could not find voltage regulator on I2C.\n");
++		ret = -1;
++		goto exit;
++	} else {
++		i2caddress = ret;
++		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
++	}
++
++	/* check IR chip work on Intel mode*/
++#ifndef CONFIG_DM_I2C
++	ret = i2c_read(i2caddress,
++		       IR36021_INTEL_MODE_OOFSET,
++		       1, (void *)&buf, 1);
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
++				  (void *)&buf, 1);
++#endif
++	if (ret) {
++		printf("VID: failed to read IR chip mode.\n");
++		ret = -1;
++		goto exit;
++	}
++
++	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
++		printf("VID: IR Chip is not used in Intel mode.\n");
++		ret = -1;
++		goto exit;
++	}
++#endif
++
+ 	/* get the voltage ID from fuse status register */
+ 	fusesr = in_le32(&gur->dcfg_fusesr);
+ 	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+@@ -203,7 +653,6 @@ int adjust_vdd(ulong vdd_override)
+ 			FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ 	}
+ 	vdd_target = vdd[vid];
+-	printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target);
+ 
+ 	/* check override variable for overriding VDD */
+ 	vdd_string = env_get(CONFIG_VID_FLS_ENV);
+@@ -246,8 +695,28 @@ int adjust_vdd(ulong vdd_override)
+ 	vdd_current = vdd_last;
+ 	debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ 
++#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
+ 	/* Set the target voltage */
+ 	vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
++#else
++	/*
++	  * Adjust voltage to at or one step above target.
++	  * As measurements are less precise than setting the values
++	  * we may run through dummy steps that cancel each other
++	  * when stepping up and then down.
++	  */
++	while (vdd_last > 0 &&
++	       vdd_last < vdd_target) {
++		vdd_current += IR_VDD_STEP_UP;
++		vdd_last = set_voltage(i2caddress, vdd_current);
++	}
++	while (vdd_last > 0 &&
++	       vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
++		vdd_current -= IR_VDD_STEP_DOWN;
++		vdd_last = set_voltage(i2caddress, vdd_current);
++	}
++
++#endif
+ 	if (board_adjust_vdd(vdd_target) < 0) {
+ 		ret = -1;
+ 		goto exit;
+@@ -264,16 +733,219 @@ exit:
+ 	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+ 	return ret;
+ }
++#else /* !CONFIG_FSL_LSCH3 */
++int adjust_vdd(ulong vdd_override)
++{
++	int re_enable = disable_interrupts();
++#if defined(CONFIG_FSL_LSCH2)
++	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++#else
++	ccsr_gur_t __iomem *gur =
++		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
++#endif
++	u32 fusesr;
++	u8 vid, buf;
++	int vdd_target, vdd_current, vdd_last;
++	int ret, i2caddress;
++	unsigned long vdd_string_override;
++	char *vdd_string;
++	static const uint16_t vdd[32] = {
++		0,      /* unused */
++		9875,   /* 0.9875V */
++		9750,
++		9625,
++		9500,
++		9375,
++		9250,
++		9125,
++		9000,
++		8875,
++		8750,
++		8625,
++		8500,
++		8375,
++		8250,
++		8125,
++		10000,  /* 1.0000V */
++		10125,
++		10250,
++		10375,
++		10500,
++		10625,
++		10750,
++		10875,
++		11000,
++		0,      /* reserved */
++	};
++	struct vdd_drive {
++		u8 vid;
++		unsigned voltage;
++	};
++
++	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
++	if (ret) {
++		debug("VID: I2C failed to switch channel\n");
++		ret = -1;
++		goto exit;
++	}
++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
++	defined(CONFIG_VOL_MONITOR_IR36021_READ)
++	ret = find_ir_chip_on_i2c();
++	if (ret < 0) {
++		printf("VID: Could not find voltage regulator on I2C.\n");
++		ret = -1;
++		goto exit;
++	} else {
++		i2caddress = ret;
++		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
++	}
++
++	/* check IR chip work on Intel mode*/
++#ifndef CONFIG_DM_I2C
++	ret = i2c_read(i2caddress,
++		       IR36021_INTEL_MODE_OOFSET,
++		       1, (void *)&buf, 1);
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
++				  (void *)&buf, 1);
++#endif
++	if (ret) {
++		printf("VID: failed to read IR chip mode.\n");
++		ret = -1;
++		goto exit;
++	}
++	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
++		printf("VID: IR Chip is not used in Intel mode.\n");
++		ret = -1;
++		goto exit;
++	}
++#endif
++
++	/* get the voltage ID from fuse status register */
++	fusesr = in_be32(&gur->dcfg_fusesr);
++	/*
++	 * VID is used according to the table below
++	 *                ---------------------------------------
++	 *                |                DA_V                 |
++	 *                |-------------------------------------|
++	 *                | 5b00000 | 5b00001-5b11110 | 5b11111 |
++	 * ---------------+---------+-----------------+---------|
++	 * | D | 5b00000  | NO VID  | VID = DA_V      | NO VID  |
++	 * | A |----------+---------+-----------------+---------|
++	 * | _ | 5b00001  |VID =    | VID =           |VID =    |
++	 * | V |   ~      | DA_V_ALT|   DA_V_ALT      | DA_A_VLT|
++	 * | _ | 5b11110  |         |                 |         |
++	 * | A |----------+---------+-----------------+---------|
++	 * | L | 5b11111  | No VID  | VID = DA_V      | NO VID  |
++	 * | T |          |         |                 |         |
++	 * ------------------------------------------------------
++	 */
++#ifdef CONFIG_FSL_LSCH2
++	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
++		FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
++	if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
++		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
++			FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
++	}
++#else
++	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
++		FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
++	if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
++		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
++			FSL_CORENET_DCFG_FUSESR_VID_MASK;
++	}
++#endif
++	vdd_target = vdd[vid];
++
++	/* check override variable for overriding VDD */
++	vdd_string = env_get(CONFIG_VID_FLS_ENV);
++	if (vdd_override == 0 && vdd_string &&
++	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
++		vdd_override = vdd_string_override;
++	if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
++		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
++		debug("VDD override is %lu\n", vdd_override);
++	} else if (vdd_override != 0) {
++		printf("Invalid value.\n");
++	}
++	if (vdd_target == 0) {
++		debug("VID: VID not used\n");
++		ret = 0;
++		goto exit;
++	} else {
++		/* divide and round up by 10 to get a value in mV */
++		vdd_target = DIV_ROUND_UP(vdd_target, 10);
++		debug("VID: vid = %d mV\n", vdd_target);
++	}
++
++	/*
++	 * Read voltage monitor to check real voltage.
++	 */
++	vdd_last = read_voltage(i2caddress);
++	if (vdd_last < 0) {
++		printf("VID: Couldn't read sensor abort VID adjustment\n");
++		ret = -1;
++		goto exit;
++	}
++	vdd_current = vdd_last;
++	debug("VID: Core voltage is currently at %d mV\n", vdd_last);
++	/*
++	  * Adjust voltage to at or one step above target.
++	  * As measurements are less precise than setting the values
++	  * we may run through dummy steps that cancel each other
++	  * when stepping up and then down.
++	  */
++	while (vdd_last > 0 &&
++	       vdd_last < vdd_target) {
++		vdd_current += IR_VDD_STEP_UP;
++		vdd_last = set_voltage(i2caddress, vdd_current);
++	}
++	while (vdd_last > 0 &&
++	       vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
++		vdd_current -= IR_VDD_STEP_DOWN;
++		vdd_last = set_voltage(i2caddress, vdd_current);
++	}
++
++	if (vdd_last > 0)
++		printf("VID: Core voltage after adjustment is at %d mV\n",
++		       vdd_last);
++	else
++		ret = -1;
++exit:
++	if (re_enable)
++		enable_interrupts();
++
++	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
++
++	return ret;
++}
++#endif
+ 
+ static int print_vdd(void)
+ {
+-	int vdd_last, ret, i2caddress;
++	int vdd_last, ret, i2caddress = 0;
+ 
+ 	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ 	if (ret) {
+ 		debug("VID : I2c failed to switch channel\n");
+ 		return -1;
+ 	}
++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
++	defined(CONFIG_VOL_MONITOR_IR36021_READ)
++	ret = find_ir_chip_on_i2c();
++	if (ret < 0) {
++		printf("VID: Could not find voltage regulator on I2C.\n");
++		goto exit;
++	} else {
++		i2caddress = ret;
++		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
++	}
++#endif
++
+ 	/*
+ 	 * Read voltage monitor to check real voltage.
+ 	 */
+@@ -295,13 +967,15 @@ static int do_vdd_override(cmd_tbl_t *cmdtp,
+ 			   char * const argv[])
+ {
+ 	ulong override;
+-
++	int ret = 0;
+ 	if (argc < 2)
+ 		return CMD_RET_USAGE;
+ 
+-	if (!strict_strtoul(argv[1], 10, &override))
+-		adjust_vdd(override);   /* the value is checked by callee */
+-	else
++	if (!strict_strtoul(argv[1], 10, &override)) {
++		ret = adjust_vdd(override);   /* the value is checked by callee */
++		if (ret < 0)
++			return CMD_RET_FAILURE;
++	} else
+ 		return CMD_RET_USAGE;
+ 	return 0;
+ }
+diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
+index 99778e9a93..9669e828a0 100644
+--- a/board/solidrun/common/vid.h
++++ b/board/solidrun/common/vid.h
+@@ -1,5 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0+ */
+ /*
++ * Copyright 2020 NXP
+  * Copyright 2014 Freescale Semiconductor, Inc.
+  */
+ 
+@@ -18,6 +19,25 @@
+ /* step the IR regulator in 5mV increments */
+ #define IR_VDD_STEP_DOWN		5
+ #define IR_VDD_STEP_UP			5
++
++/* LTC3882 */
++#define PMBUS_CMD_WRITE_PROTECT         0x10
++/*
++ * WRITE_PROTECT command supported values
++ * 0x80: Disable all writes except WRITE_PROTECT, PAGE,
++ *       STORE_USER_ALL and MFR_EE_UNLOCK commands.
++ * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
++ *       MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
++ *       Individual faults can also be cleared by writing a 1 to the
++ *       respective status bit.
++ * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
++ *       MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
++ *       and VOUT_COMMAND commands. Individual faults can be cleared by
++ *       writing a 1 to the respective status bit.
++ * 0x00: Enables write to all commands
++ */
++#define EN_WRITE_ALL_CMD (0)
++
+ int adjust_vdd(ulong vdd_override);
+ 
+ #endif  /* __VID_H_ */
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0015-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch

+From 1dee00c3e75cd6ca9060b526ab5cd3eb376363a6 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 3 Feb 2020 14:26:55 +0200
+Subject: [PATCH] lx2160a-cex7 : move from lsdk-19.06 to lsdk-19.09
+
+Following is a list of changes -
+1. I2C moved to DM model
+2. removed emc2301 support
+3. synchronized vid.c with NXP's driver. But it is still not functional
+in u-boot
+4. Added eMMC to distroboot target list
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts |  14 +
+ board/solidrun/common/Makefile    |   1 -
+ board/solidrun/common/emc2301.c   |  31 --
+ board/solidrun/common/vid.c       | 638 +++++++++++++++++++++++++++++-
+ board/solidrun/lx2160a/lx2160a.c  |   8 +
+ configs/lx2160acex7_tfa_defconfig |   8 +-
+ include/configs/lx2160a_common.h  |   1 +
+ 7 files changed, 666 insertions(+), 35 deletions(-)
+ delete mode 100644 board/solidrun/common/emc2301.c
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+index 4fbcaafb0e..4ca67df25a 100644
+--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -46,6 +46,20 @@
+ 	status = "okay";
+ };
+ 
++&i2c0 {
++	status = "okay";
++	u-boot,dm-pre-reloc;
++};
++
++&i2c4 {
++	status = "okay";
++
++	rtc@51 {
++		compatible = "pcf2127-rtc";
++		reg = <0x51>;
++	};
++};
++
+ &sata0 {
+ 	status = "okay";
+ };
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index b0d9f1012e..3713e91351 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -62,7 +62,15 @@ int select_i2c_ch_pca9547(u8 ch)
+ {
+ 	int ret;
+ 
++#ifndef CONFIG_DM_I2C
+ 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_write(dev, 0, &ch, 1);
++#endif
+ 	if (ret) {
+ 		puts("PCA: failed to select proper channel\n");
+ 		return ret;
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 3891d2a7c4..89a47adb23 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -2,7 +2,6 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
+-CONFIG_EMC2301=y
+ CONFIG_TFABOOT=y
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+@@ -73,3 +72,10 @@ CONFIG_DM_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_I2C_DEFAULT_BUS_NUMBER=0
++CONFIG_DM_RTC=y
++CONFIG_DM_GPIO=y
++CONFIG_CMD_DATE=y
++CONFIG_RTC_PCF2127=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0016-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch

+From d2e368b0df941fe8958df4f44dd2c7cfc32d0fb8 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:53:48 +0200
+Subject: [PATCH 16/16] lx2160acex7: pcie fixup and boot from eMMC print
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/lx2160a.c  | 66 +++++++++++++++++++++++++++++++
+ configs/lx2160acex7_tfa_defconfig |  3 +-
+ 2 files changed, 68 insertions(+), 1 deletion(-)
+
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index 3713e91351..b7211a2d5c 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -20,6 +20,8 @@
+ #include <efi_loader.h>
+ #include <asm/arch/mmu.h>
+ #include <hwconfig.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/config.h>
+ #include <asm/arch/fsl_serdes.h>
+ #include <asm/arch/soc.h>
+ #include "../../freescale/common/vid.h"
+@@ -106,6 +108,66 @@ int board_early_init_f(void)
+ #ifdef CONFIG_OF_BOARD_FIXUP
+ int board_fix_fdt(void *fdt)
+ {
++	char *reg_name, *old_str, *new_str;
++	const char *reg_names;
++	int names_len, old_str_len, new_str_len, remaining_str_len;
++	struct str_map {
++		char *old_str;
++		char *new_str;
++	} reg_names_map[] = {
++		{ "ccsr", "dbi" },
++		{ "pf_ctrl", "ctrl" }
++	};
++	int off = -1, i;
++
++	if (IS_SVR_REV(get_svr(), 1, 0))
++		return 0;
++
++	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
++	while (off != -FDT_ERR_NOTFOUND) {
++		fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
++			    strlen("fsl,ls-pcie") + 1);
++
++		reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
++		if (!reg_names)
++			continue;
++
++		reg_name = (char *)reg_names;
++		remaining_str_len = names_len - (reg_name - reg_names);
++		i = 0;
++		while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
++			old_str = reg_names_map[i].old_str;
++			new_str = reg_names_map[i].new_str;
++			old_str_len = strlen(old_str);
++			new_str_len = strlen(new_str);
++			if (memcmp(reg_name, old_str, old_str_len) == 0) {
++				/* first only leave required bytes for new_str
++				 * and copy rest of the string after it
++				 */
++				memcpy(reg_name + new_str_len,
++				       reg_name + old_str_len,
++				       remaining_str_len - old_str_len);
++				/* Now copy new_str */
++				memcpy(reg_name, new_str, new_str_len);
++				names_len -= old_str_len;
++				names_len += new_str_len;
++				i++;
++			}
++
++			reg_name = memchr(reg_name, '\0', remaining_str_len);
++			if (!reg_name)
++				break;
++
++			reg_name += 1;
++
++			remaining_str_len = names_len - (reg_name - reg_names);
++		}
++
++		fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
++		off = fdt_node_offset_by_compatible(fdt, off,
++						    "fsl,lx2160a-pcie");
++	}
++
+ 	return 0;
+ }
+ #endif
+@@ -135,6 +197,10 @@ int checkboard(void)
+ 
+ 	if (src == BOOT_SOURCE_SD_MMC) {
+ 		puts("SD\n");
++	} else if (src == BOOT_SOURCE_SD_MMC2) {
++		puts("eMMC\n");
++	} else {
++		puts("FlexSPI DEV#0\n");
+ 	}
+ 	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
+ 	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 89a47adb23..2a3441d263 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_FSPI_AHB_EN_4BYTE=y
+ CONFIG_TFABOOT=y
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+@@ -59,6 +60,7 @@ CONFIG_PCI=y
+ CONFIG_DM_PCI_COMPAT=y
+ CONFIG_PCIE_LAYERSCAPE_GEN4=y
+ CONFIG_PHY_ATHEROS=y
++CONFIG_PCIE_LAYERSCAPE=y
+ CONFIG_E1000=y
+ CONFIG_DM_SCSI=y
+ CONFIG_DM_SERIAL=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0017-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch

+From 1ec9f76ce5813ec7f2f825aecf0b9c6a2d8d1cf0 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 15:13:11 +0200
+Subject: [PATCH 17/17] lx2160a-cex7: set mmc dev to 0 when attempting
+ sd_bootcmd
+
+When attempting sd_bootcmd which is the fallback of failed distroboot
+then set mmc dev to 0; since distroboot already set that variable to 1.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160acex7.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 478cd8242f..7116e038a1 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -73,7 +73,7 @@
+ 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ 		" bootm $load_addr#$BOARD\0"			\
+ 	"sd_bootcmd=echo Trying load from sd card..;"		\
+-		"mmcinfo; mmc read $load_addr "			\
++		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
+ 		"$kernel_addr_sd $kernel_size_sd ;"		\
+ 		"env exists secureboot && mmc read $kernelheader_addr_r "\
+ 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0018-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch

+From 341eb7a1e9ce5f7764f39002b96e7975955cac0e Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 4 May 2020 22:52:02 +0300
+Subject: [PATCH] lx2160acex7: Misc fixes to support LSDK-20.04
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/Kconfig                  |  1 +
+ board/solidrun/lx2160a/lx2160a.c  |  4 +++-
+ configs/lx2160acex7_tfa_defconfig | 24 ++++++++++++------------
+ 3 files changed, 16 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 8615e1673f..c78e17a0ed 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1195,6 +1195,7 @@ config TARGET_LX2160ACEX7
+ 	select ARCH_MISC_INIT
+ 	select ARM64
+ 	select ARMV8_MULTIENTRY
++	select ARCH_SUPPORT_TFABOOT
+ 	select BOARD_LATE_INIT
+ 	help
+ 	  Support for SolidRun LX2160A based com express type 7 module and
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index b7211a2d5c..975431fd53 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -16,7 +16,7 @@
+ #include <fdt_support.h>
+ #include <linux/libfdt.h>
+ #include <fsl-mc/fsl_mc.h>
+-#include <environment.h>
++#include <env_internal.h>
+ #include <efi_loader.h>
+ #include <asm/arch/mmu.h>
+ #include <hwconfig.h>
+@@ -26,6 +26,8 @@
+ #include <asm/arch/soc.h>
+ #include "../../freescale/common/vid.h"
+ #include <fsl_immap.h>
++#include <asm/arch-fsl-layerscape/fsl_icid.h>
++#include <asm/gic-v3.h>
+ 
+ #ifdef CONFIG_EMC2301
+ #include "../common/emc2301.h"
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 2a3441d263..d2e62a6e91 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -1,16 +1,15 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_TFABOOT=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
+ CONFIG_FSPI_AHB_EN_4BYTE=y
+-CONFIG_TFABOOT=y
++CONFIG_NR_DRAM_BANKS=3
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+ CONFIG_AHCI=y
+-CONFIG_NR_DRAM_BANKS=3
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_OF_BOARD_SETUP=y
+-CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_OF_STDOUT_VIA_ALIAS=y
+ CONFIG_BOOTDELAY=10
+ CONFIG_USE_BOOTARGS=y
+@@ -29,6 +28,7 @@ CONFIG_CMD_NVME=y
+ CONFIG_NVME=y
+ CONFIG_MP=y
+ CONFIG_OF_CONTROL=y
++CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
+@@ -36,6 +36,10 @@ CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_DM=y
+ CONFIG_SATA_CEVA=y
+ CONFIG_FSL_CAAM=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+ CONFIG_DM_MMC=y
+ CONFIG_FSL_ESDHC=y
+ CONFIG_DM_SPI_FLASH=y
+@@ -55,28 +59,24 @@ CONFIG_CMD_MII=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_EXT2=y
++CONFIG_E1000=y
+ CONFIG_PCI=y
+ CONFIG_DM_PCI=y
+ CONFIG_DM_PCI_COMPAT=y
+ CONFIG_PCIE_LAYERSCAPE_GEN4=y
+ CONFIG_PHY_ATHEROS=y
+ CONFIG_PCIE_LAYERSCAPE=y
+-CONFIG_E1000=y
++CONFIG_DM_RTC=y
++CONFIG_RTC_PCF2127=y
++
+ CONFIG_DM_SCSI=y
+ CONFIG_DM_SERIAL=y
+-CONFIG_SERIAL_PROBE_ALL=y
+ CONFIG_SPI=y
+ CONFIG_DM_SPI=y
+ CONFIG_NXP_FSPI=y
+-# CONFIG_SYS_NXP_FSPI_AHB=y
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+-CONFIG_DM_I2C=y
+-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+-CONFIG_DM_RTC=y
+-CONFIG_DM_GPIO=y
+ CONFIG_CMD_DATE=y
+-CONFIG_RTC_PCF2127=y
++CONFIG_GIC_V3_ITS=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0019-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch

+From 1e1e86ebef25670922c7e1e65d897a4dba9a806f Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 5 May 2020 01:01:01 +0300
+Subject: [PATCH] lx2160acex7: misc fixes to get booting from eMMC functional
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 10 ++++++++++
+ include/configs/lx2160acex7.h    | 14 ++++++++------
+ 2 files changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 8983e615d1..d65e5c5cf2 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	"esbc_validate 0x80680000 ;"		\
+ 	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+ 
++#define SD2_MC_INIT_CMD				\
++	"mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;"	\
++	"mmc read 0x80e00000 0x7000 0x800;"	\
++	"env exists secureboot && "		\
++	"mmc read 0x80640000 0x3200 0x20 && "	\
++	"mmc read 0x80680000 0x3400 0x20 && "	\
++	"esbc_validate 0x80640000 && "		\
++	"esbc_validate 0x80680000 ;"		\
++	"fsl_mc start mc 0x80a00000 0x80e00000\0"
++
+ #define EXTRA_ENV_SETTINGS			\
+ 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+ 	"ramdisk_addr=0x800000\0"		\
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 7116e038a1..310168db47 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -46,11 +46,6 @@
+ 
+ #endif
+ 
+-/* EMC2301 */
+-#define I2C_MUX_CH_EMC2301	0x01
+-#define I2C_EMC2301_ADDR	0x2f
+-#define I2C_EMC2301_CMD		0x40
+-#define I2C_EMC2301_PWM		0x80
+ 
+ /* EEPROM */
+ #undef CONFIG_ID_EEPROM /* Fixme */
+@@ -73,7 +68,14 @@
+ 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ 		" bootm $load_addr#$BOARD\0"			\
+ 	"sd_bootcmd=echo Trying load from sd card..;"		\
+-		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
++		"mmcinfo; mmc read $load_addr "			\
++		"$kernel_addr_sd $kernel_size_sd ;"		\
++		"env exists secureboot && mmc read $kernelheader_addr_r "\
++		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
++		" && esbc_validate ${kernelheader_addr_r};"	\
++		"bootm $load_addr#$BOARD\0"			\
++	"emmc_bootcmd=echo Trying load from emmc card..;"	\
++		"mmc dev 1; mmcinfo; mmc read $load_addr "	\
+ 		"$kernel_addr_sd $kernel_size_sd ;"		\
+ 		"env exists secureboot && mmc read $kernelheader_addr_r "\
+ 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0020-lx2160a-add-ramdisk_addr_r-for-distro-boot-support.patch

+From 75cdf0872954e3a096a00a698c3ec9fbd6e1f9c7 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Wed, 22 Jul 2020 15:22:48 +0200
+Subject: [PATCH] lx2160a: add ramdisk_addr_r for distro-boot support
+
+Because ramdisks can be huge, the addresses were reordered by size so
+that ramdisk is loaded beyond kernel and fdt:
+- 0x81000000: 1MB for DTB
+- 0x81100000: 255MB for Kernel
+- 0x90000000: open end for ramdisk
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index d65e5c5cf2..4f23d9a96b 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -237,7 +237,8 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 
+ #define EXTRA_ENV_SETTINGS			\
+ 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+-	"ramdisk_addr=0x800000\0"		\
++	"ramdisk_addr=0x90000000\0"		\
++	"ramdisk_addr_r=0x90000000\0"		\
+ 	"ramdisk_size=0x2000000\0"		\
+ 	"fdt_high=0xa0000000\0"			\
+ 	"initrd_high=0xffffffffffffffff\0"	\
+@@ -248,9 +249,9 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	"scripthdraddr=0x80080000\0"		\
+ 	"fdtheader_addr_r=0x80100000\0"		\
+ 	"kernelheader_addr_r=0x80200000\0"	\
+-	"kernel_addr_r=0x81000000\0"		\
++	"kernel_addr_r=0x81100000\0"		\
+ 	"kernelheader_size=0x40000\0"		\
+-	"fdt_addr_r=0x90000000\0"		\
++	"fdt_addr_r=0x81000000\0"		\
+ 	"load_addr=0xa0000000\0"		\
+ 	"kernel_size=0x2800000\0"		\
+ 	"kernel_addr_sd=0x8000\0"		\
+-- 
+2.27.0
+

patches/u-boot-LSDK-20.12/0020-pci-fix-layerscape.patch

+From 04f824bd1210fbc6db08560dda9cd14318f859d9 Mon Sep 17 00:00:00 2001
+From: Russell King <rmk@armlinux.org.uk>
+Date: Tue, 5 May 2020 01:01:01 +0300
+Subject: [PATCH] pci: fix layerscape
+
+On the LX2160A rev 1, SVR_SOC_VER() returns 0x873610, and this causes
+the wrong PCIe fdt fixup code to be called, resulting in all PCIe
+devices remaining disabled in the DT passed to the kernel.  Fix this
+by detecting the ID and using the correct gen4 layerscape PCIe code.
+
+Signed-off-by: Russell King <rmk@armlinux.org.uk>
+---
+ drivers/pci/pcie_layerscape_fixup_common.c | 5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
+index b6179798b3..0327930ddb 100644
+--- a/drivers/pci/pcie_layerscape_fixup_common.c
++++ b/drivers/pci/pcie_layerscape_fixup_common.c
+@@ -18,8 +18,9 @@ void ft_pci_setup(void *blob, bd_t *bd)
+ 	uint svr;
+ 
+ 	svr = SVR_SOC_VER(get_svr());
+-
+-	if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
++	/* Rev 1 LX2160A have svr = 0x873610 */
++	if ((svr == SVR_LX2160A || svr == (SVR_LX2160A | 0x10)) &&
++	    IS_SVR_REV(get_svr(), 1, 0))
+ 		ft_pci_setup_ls_gen4(blob, bd);
+ 	else
+ #endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */

patches/u-boot-LSDK-20.12/0021-lx2160acex7-add-poweroff-and-disable-fan-full-speed.patch

+From 37c0a6113967619af24d58c3730afcf57f3bfbad Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 17 Jan 2021 17:14:06 +0200
+Subject: [PATCH] lx2160acex7: add poweroff and disable fan full speed
+
+1. Add poweroff command; when using Clearfog CX or HoneyComb carrier
+boards, the S5# signal is connected to the power button controller that
+cuts off the '12v' supply from the COM module.
+
+2. In board_fix_fdt, just before booting the kernel the fan full speed
+signal becomes inactive so that the kernel AMC6821 driver would take
+over and enable the auto thermal and pwm adjustments.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
+ board/solidrun/lx2160a/lx2160a.c                       | 8 +++++++-
+ configs/lx2160acex7_tfa_defconfig                      | 2 +-
+ 3 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+index dc740c999d..ab6297dae2 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+@@ -65,6 +65,9 @@
+ #define I2C7_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01060000)
+ #define I2C8_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01070000)
+ #endif
++#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01320000)
++#define GPIO3_GPDIR_ADDR			(GPIO3_BASE_ADDR + 0x0)
++#define GPIO3_GPDAT_ADDR			(GPIO3_BASE_ADDR + 0x8)
+ #define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01330000)
+ #define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
+ #define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index 975431fd53..0148ce2a48 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -358,7 +358,13 @@ int ft_board_setup(void *blob, bd_t *bd)
+ 	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+ 	fdt_fixup_board_enet(blob);
+ #endif
+-
++	printf ("Releasing fan controller full speed gpio\n");
++	/*
++	 * Set the GPIO to be input; the on-COM pullup will disable the full speed
++	 * signal.
++	 */
++	out_le32(GPIO3_GPDIR_ADDR, (~(1 << 29) &
++		in_le32(GPIO3_GPDIR_ADDR)));
+ 	return 0;
+ }
+ #endif
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 8e96265843..837d6070dd 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -68,7 +68,7 @@ CONFIG_PHY_ATHEROS=y
+ CONFIG_PCIE_LAYERSCAPE=y
+ CONFIG_DM_RTC=y
+ CONFIG_RTC_PCF2127=y
+-
++CONFIG_CMD_POWEROFF=y
+ CONFIG_DM_SCSI=y
+ CONFIG_DM_SERIAL=y
+ CONFIG_SPI=y
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0022-lx2160acex7-drop-ramdisk-from-default-bootargs.patch

+From b145ea98fe987b7955d11e7f2352b657ed14498f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Wed, 22 Jul 2020 15:35:30 +0200
+Subject: [PATCH] lx2160acex7: drop ramdisk from default bootargs
+
+root=/dev/ram0 along with ramdisk_size are deployment-specific and
+actually prevent booting a generic distro-boot enabled system that only
+extends rather than override firmware-defined bootargs.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 837d6070dd..97d3877047 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -13,7 +13,7 @@ CONFIG_OF_BOARD_SETUP=y
+ CONFIG_OF_STDOUT_VIA_ALIAS=y
+ CONFIG_BOOTDELAY=10
+ CONFIG_USE_BOOTARGS=y
+-CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+ # CONFIG_USE_BOOTCOMMAND is not set
+ CONFIG_CMD_GREPENV=y
+ CONFIG_CMD_EEPROM=y
+-- 
+2.27.0
+

patches/u-boot-LSDK-20.12/0023-lx2160acex7-add-25Gbps-TI-retimer-configuration.patch

+From ae9bf5e00231fb5957e81f1e16289a9eae707f03 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 28 Oct 2020 19:24:35 +0200
+Subject: [PATCH] lx2160acex7: add 25Gbps TI retimer configuration
+
+ClearFog CX revision 1.3 and newer adds two TI 4 channels retimers on
+egress and ingress.
+On egress the retimer is configured to be on I2C address 0x22 and the
+other on I2C address 0x23.
+
+This patch configures the egress retimer pre and post key and the
+amplitude.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 110 +++++++++++++++++------
+ include/configs/lx2160acex7.h            |   2 +-
+ 2 files changed, 85 insertions(+), 27 deletions(-)
+
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index 97e414838f..f335b4207a 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -12,6 +12,7 @@
+ #include <miiphy.h>
+ #include <phy.h>
+ #include <fm_eth.h>
++#include <i2c.h>
+ #include <asm/io.h>
+ #include <exports.h>
+ #include <asm/arch/fsl_serdes.h>
+@@ -20,6 +21,65 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++int select_i2c_ch_pca9547(u8 ch);
++
++void setup_retimer_25g(int chnum)
++{
++	int i, ret;
++	u8 reg;
++	struct udevice *dev;
++
++	select_i2c_ch_pca9547(0xb); /* SMB_CLK / DATA interface */
++	/*
++	 * Assumption is that LX2 TX --> RT1 RX is at 0x22 and
++	 * RT2 TX --> LX2 RX is at 0x23.
++	 */
++	ret = i2c_get_chip_for_busnum(0, 0x23, 1, &dev);
++	if (ret) {
++		/*
++		 * On HoneyComb and ClearFog CX ver 1.1 / 1.2 there is no retimer
++		 * assembled; silently return.
++		 */
++		return;
++	}
++	ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
++	if (ret) {
++		printf ("ERROR: Could not get retimer device ID\n");
++		return;
++	}
++	if (reg != 0x10) {
++		printf ("ERROR : DS250DF410 retimer not found\n");
++		return;
++	}
++	printf ("Found retimer... Setting up channels 0..%d as 25Gbps\n",chnum - 1);
++	dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
++	/*
++	 * Setup 25Gbps channel on 0..chnum.
++	 * Notice that the ingress retimer is mirrorly mapped with the SERDES
++	 * number, so SERDES #0 is connected to channel #3, SERDES 1 to channel
++	 * #2 ...
++	 */
++	for (i = 0 ; i < chnum; i++) { /* Setup channels 0..chnum as 25g */
++		dm_i2c_reg_write(dev, 0xfc, 1 << i);
++		dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
++		dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
++
++		printf ("Setting main cursor to 0xf\n");
++		dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
++		dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
++		if (i == 0)
++			/* Set post-cursor of channel #0 to -4 */
++			dm_i2c_reg_write(dev, 0x3f, 0x44);
++		else
++			/* Set all other channels pre-cursor to -1 */
++			dm_i2c_reg_write(dev, 0x3f, 0x41);
++		printf ("Releasing CDR\n");
++		dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
++	}
++
++	/* TODO: Setup other channels as 10Gbps */
++}
++
+ int board_eth_init(bd_t *bis)
+ {
+ #if defined(CONFIG_FSL_MC_ENET)
+@@ -45,35 +105,33 @@ int board_eth_init(bd_t *bis)
+ 			      RGMII_PHY_ADDR1);
+ 	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ 	switch (srds_s1) {
+-	case 3:
+-	case 5:
+-	case 8:
+-	case 13:
+-	case 14:
+-	case 15:
+-	case 17:
+-	case 20:
+-	case 23:
+-		wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+-				      RGMII_PHY_ADDR1);
+-		break;
+-
+-	default:
++		case 13:
++		case 14:
++		case 15:
++		case 16:
++		case 17:
++		case 21:
++			/* Setup 25gb retimer on lanes e,f,g,h */
++			setup_retimer_25g(4);
++			break;
++		case 18:
++		case 19:
++			/* Setup 25gb retimer on lanes e,f and 10g on g,h */
++			setup_retimer_25g(2);
++			break;
++
++		default:
+ 		printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
+ 		       srds_s1);
+-		goto next;
+ 	}
+-	for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
+-		interface = wriop_get_enet_if(i);
+-		switch (interface) {
+-		case PHY_INTERFACE_MODE_RGMII:
+-		case PHY_INTERFACE_MODE_RGMII_ID:
+-			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+-			wriop_set_mdio(i, dev);
+-			break;
+-		default:
+-			break;
+-		}
++	wriop_set_phy_address(WRIOP1_DPMAC17, 0,
++			      RGMII_PHY_ADDR1);
++	interface = wriop_get_enet_if(WRIOP1_DPMAC17);
++	switch (interface) {
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++		dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
++		wriop_set_mdio(WRIOP1_DPMAC17, dev);
+ 	}
+ 
+ next:
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 310168db47..de075eaeaa 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -11,7 +11,7 @@
+ /*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
+ /* VID */
+ 
+-#define I2C_MUX_CH_VOL_MONITOR		0x2
++#define I2C_MUX_CH_VOL_MONITOR		0xa /* Channel 2 */
+ /* Voltage monitor on channel 2*/
+ #define I2C_VOL_MONITOR_ADDR		0x5c
+ #define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0024-lx2160acex7-refine-pre-cursor-of-all-channels-to-4.patch

+From 0d832fe197168612c6c150e220b85fd907049cb4 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 3 Nov 2020 15:37:45 +0200
+Subject: [PATCH 24/24] lx2160acex7: refine pre-cursor of all channels to -4
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index f335b420..968190f1 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -63,17 +63,10 @@ void setup_retimer_25g(int chnum)
+ 		dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ 		dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ 		dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+-
+-		printf ("Setting main cursor to 0xf\n");
+ 		dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
+ 		dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
+-		if (i == 0)
+-			/* Set post-cursor of channel #0 to -4 */
+-			dm_i2c_reg_write(dev, 0x3f, 0x44);
+-		else
+-			/* Set all other channels pre-cursor to -1 */
+-			dm_i2c_reg_write(dev, 0x3f, 0x41);
+-		printf ("Releasing CDR\n");
++		/* Set post-cursor of channel #0 to -4 */
++		dm_i2c_reg_write(dev, 0x3f, 0x44);
+ 		dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ 	}
+ 
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0026-lx2160acex7-add-sys_eeprom-support-and-read-MAC-addr.patch

+From 05f7b0ddb485d587ee3638105a2b0536abc1eff0 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 17 Dec 2020 17:55:19 +0200
+Subject: [PATCH] lx2160acex7: add sys_eeprom support and read MAC addresses
+ from it
+
+1. Add eeprom on I2C0 - MUX (0x77) - I2C0 - EEPROM at 0x57 (2Kbit
+eeprom)
+2. After storing first TLV formatted data sys_eeprom will use that
+eeprom
+3. For now the DPMAC17 (1Gbps from the COM) is set as last DPMAC for
+registration, which means it will get the MAC register in sys_eeprom + 8
+in the case of SD1 protocol=8. We will modify that in the future the
+DPMAC17 will be registered first so it would get the sys_eeprom base MAC
+first.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts        | 61 ++++++++++++++++++++++++
+ board/solidrun/lx2160a/eth_lx2160acex7.c |  6 +--
+ configs/lx2160acex7_tfa_defconfig        |  7 +++
+ include/configs/lx2160acex7.h            |  8 +---
+ 4 files changed, 72 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+index 4ca67df2..04adbcf6 100644
+--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -49,6 +49,67 @@
+ &i2c0 {
+ 	status = "okay";
+ 	u-boot,dm-pre-reloc;
++	i2c-mux@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		i2c@0 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0>;
++/* The following eeprin is reserved so that the 2Kb eeprom at address 0x57
++   would be used as TLV eeprom.
++			24aa512@50 {
++				compatible = "atmel,24c512";
++				reg = <0x50>;
++			};
++*/
++			spd1@51 {
++				compatible = "atmel,spd";
++				reg = <0x51>;
++			};
++			spd2@53 {
++				compatible = "atmel,spd";
++				reg = <0x53>;
++			};
++			m24c02@57 {
++				compatible = "atmel,24c02";
++				reg = <0x57>;
++			};
++		};
++		i2c@1 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x1>;
++			fan-temperature-ctrlr@18 {
++				compatible = "ti,amc6821";
++				reg = <0x18>;
++				cooling-min-state = <0>;
++				cooling-max-state = <9>;
++				#cooling-cells = <2>;
++			};
++		};
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++			ltc3882@5c {
++				compatible = "ltc3882";
++				reg = <0x5c>;
++			};
++		};
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			temperature-sensor@48 {
++				compatible = "nxp,sa56004";
++				reg = <0x48>;
++			};
++		};
++	};
+ };
+ 
+ &i2c4 {
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index 968190f1..f286f72e 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -13,11 +13,13 @@
+ #include <phy.h>
+ #include <fm_eth.h>
+ #include <i2c.h>
++#include <sys_eeprom.h>
+ #include <asm/io.h>
+ #include <exports.h>
+ #include <asm/arch/fsl_serdes.h>
+ #include <fsl-mc/fsl_mc.h>
+ #include <fsl-mc/ldpaa_wriop.h>
++#include <fsl-mc/fsl_mc_private.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -127,7 +129,7 @@ int board_eth_init(bd_t *bis)
+ 		wriop_set_mdio(WRIOP1_DPMAC17, dev);
+ 	}
+ 
+-next:
++	mac_read_from_eeprom();
+ 	cpu_eth_init(bis);
+ #endif /* CONFIG_FSL_MC_ENET */
+ 
+@@ -145,9 +147,7 @@ void reset_phy(void)
+ 
+ int fdt_fixup_board_phy(void *fdt)
+ {
+-	int mdio_offset;
+ 	int ret;
+-	struct mii_dev *dev;
+ 
+ 	ret = 0;
+ 
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 97d38770..62ff236e 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -38,8 +38,12 @@ CONFIG_SATA_CEVA=y
+ CONFIG_FSL_CAAM=y
+ CONFIG_DM_GPIO=y
+ CONFIG_DM_I2C=y
++CONFIG_MISC=y
+ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+ CONFIG_I2C_DEFAULT_BUS_NUMBER=0
++CONFIG_I2C_EEPROM=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_MUX_PCA954x=y
+ CONFIG_DM_MMC=y
+ CONFIG_FSL_ESDHC=y
+ CONFIG_DM_SPI_FLASH=y
+@@ -59,6 +63,7 @@ CONFIG_CMD_MII=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_EXT2=y
++CONFIG_CMD_SYS_EEPROM=y
+ CONFIG_E1000=y
+ CONFIG_PCI=y
+ CONFIG_DM_PCI=y
+@@ -81,3 +86,5 @@ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+ CONFIG_CMD_DATE=y
+ CONFIG_RTC_PCF2127=y
++CONFIG_CMD_MEMORY=y
++CONFIG_CMD_MEMTEST=y
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index de075eae..9ba73fc0 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -48,13 +48,7 @@
+ 
+ 
+ /* EEPROM */
+-#undef CONFIG_ID_EEPROM /* Fixme */
+-#define CONFIG_SYS_I2C_EEPROM_NXID
+-#define CONFIG_SYS_EEPROM_BUS_NUM	           0
+-#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
+-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
+-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
+-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++#undef CONFIG_ID_EEPROM /* We use TLV with I2C DM */
+ 
+ /* Initial environment variables */
+ #define CONFIG_EXTRA_ENV_SETTINGS		\
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0027-lx2160a-set-dpaa-mac-registration-as-weak-and-clear-.patch

+From e290dcf25044b3b41406f50065812c69a29d9e64 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 17 Dec 2020 18:01:40 +0200
+Subject: [PATCH 27/27] lx2160a: set dpaa mac registration as weak, and clear
+ build warning msgs
+
+1. Set fsl_mc_ldpaa_init so that a board can register the dpmacs in it's
+own order
+2. Cleanup build warning messages which is triggered when using
+CONFIG_I2C_EEPROM required for sys_eeprom feature
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ drivers/net/fsl-mc/mc.c          | 2 +-
+ include/configs/lx2160a_common.h | 5 +++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
+index f7602493..2a0ec4a8 100644
+--- a/drivers/net/fsl-mc/mc.c
++++ b/drivers/net/fsl-mc/mc.c
+@@ -915,7 +915,7 @@ unsigned long mc_get_dram_block_size(void)
+ 	return dram_block_size;
+ }
+ 
+-int fsl_mc_ldpaa_init(bd_t *bis)
++__weak int fsl_mc_ldpaa_init(bd_t *bis)
+ {
+ 	int i;
+ 
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 288f0e14..c57b9ce2 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -119,6 +119,11 @@
+ #define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
+ 
+ /* EEPROM */
++#undef CONFIG_SYS_EEPROM_BUS_NUM
++#undef CONFIG_SYS_I2C_EEPROM_ADDR
++#undef CONFIG_SYS_I2C_EEPROM_ADDR_LEN
++#undef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
++#undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+ #define CONFIG_ID_EEPROM
+ #define CONFIG_SYS_I2C_EEPROM_NXID
+ #define CONFIG_SYS_EEPROM_BUS_NUM		0
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0028-lx2160acex7-add-mtest-start-and-end-addresses.patch

+From 4d76da48691cf5d87fff2626065978617c629fbb Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 20 Dec 2020 16:06:26 +0200
+Subject: [PATCH 28/28] lx2160acex7: add mtest start and end addresses
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160acex7.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 9ba73fc0..d2ef78a2 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -77,5 +77,7 @@
+ 		"bootm $load_addr#$BOARD\0"
+ 
+ #include <asm/fsl_secure_boot.h>
++#define CONFIG_SYS_MEMTEST_START		0x2080000000
++#define CONFIG_SYS_MEMTEST_END			0x2400000000
+ 
+ #endif /* __LX2_CEX7_H */
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0029-lx2160acex7-add-10Gbps-retimer-configuration.patch

+From abc79c9532750adfc37f3869bf0c17a2e665df41 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 30 Dec 2020 19:52:00 +0200
+Subject: [PATCH 29/29] lx2160acex7: add 10Gbps retimer configuration
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 47 ++++++++++++++++++++++--
+ 1 file changed, 44 insertions(+), 3 deletions(-)
+
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index f286f72e..a754d3fd 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -53,7 +53,11 @@ void setup_retimer_25g(int chnum)
+ 		printf ("ERROR : DS250DF410 retimer not found\n");
+ 		return;
+ 	}
+-	printf ("Found retimer... Setting up channels 0..%d as 25Gbps\n",chnum - 1);
++	if (chnum > 0)
++		printf ("Setting up retimer channels 1..%d as 25Gbps\n",chnum);
++	if (chnum < 4)
++		printf ("Setting up retimer channels %d..4 as 10Gbps\n",chnum+1);
++
+ 	dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
+ 	/*
+ 	 * Setup 25Gbps channel on 0..chnum.
+@@ -71,8 +75,42 @@ void setup_retimer_25g(int chnum)
+ 		dm_i2c_reg_write(dev, 0x3f, 0x44);
+ 		dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ 	}
+-
+-	/* TODO: Setup other channels as 10Gbps */
++	if (chnum < 4) {
++		/* Setup the rest of the channels as 10g */
++		for (i = chnum ; i < 4; i++) {
++			dm_i2c_reg_write(dev, 0xfc, 1 << i);
++			dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
++			dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
++			dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
++			dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
++			/* Set post-cursor of channel #0 to -4 */
++			dm_i2c_reg_write(dev, 0x3f, 0x44);
++			dm_i2c_reg_write(dev, 0x2f, 0x04); /* Set rate to 10.3125 Gbps */
++			dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
++		}
++		ret = i2c_get_chip_for_busnum(0, 0x22, 1, &dev);
++		if (ret) {
++			printf ("ERROR: Retimer at address 0x22 not found\n");
++			return;
++		}
++		ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
++		if (ret) {
++			printf ("ERROR: Could not get retimer device ID\n");
++			return;
++		}
++		if (reg != 0x10) {
++			printf ("ERROR : DS250DF410 retimer not found\n");
++			return;
++		}
++		dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
++		for (i = chnum ; i < 4; i++) {
++			dm_i2c_reg_write(dev, 0xfc, 1 << i);
++			dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
++			dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
++			dm_i2c_reg_write(dev, 0x2f, 0x04); /* Set rate to 10.3125 Gbps */
++			dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
++		}
++	}
+ }
+ 
+ int board_eth_init(bd_t *bis)
+@@ -100,6 +138,9 @@ int board_eth_init(bd_t *bis)
+ 			      RGMII_PHY_ADDR1);
+ 	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ 	switch (srds_s1) {
++		case 8:
++			setup_retimer_25g(0);
++			break;
+ 		case 13:
+ 		case 14:
+ 		case 15:
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0030-lx2160acex7-add-support-for-LSDK-20.12-and-it-s-newe.patch

+From d75709426d141ee7e8fd8c38eddc420676c75f49 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 17 Jan 2021 17:25:25 +0200
+Subject: [PATCH] lx2160acex7: add support for LSDK-20.12 and it's newer u-boot
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/eth_lx2160acex7.c |  2 +-
+ board/solidrun/lx2160a/lx2160a.c         |  7 ++++---
+ configs/lx2160acex7_tfa_defconfig        | 16 +++++++++++++++-
+ 3 files changed, 20 insertions(+), 5 deletions(-)
+
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index a754d3fd63..211de59971 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -13,7 +13,7 @@
+ #include <phy.h>
+ #include <fm_eth.h>
+ #include <i2c.h>
+-#include <sys_eeprom.h>
++#include <tlv_eeprom.h>
+ #include <asm/io.h>
+ #include <exports.h>
+ #include <asm/arch/fsl_serdes.h>
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index 0148ce2a48..8f9251c294 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -1,9 +1,10 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+- * Copyright 2019 SolidRun ltd.
++ * Copyright 2019-2021 SolidRun ltd.
+  */
+ 
+ #include <common.h>
++#include <clock_legacy.h>
+ #include <dm.h>
+ #include <dm/platform_data/serial_pl01x.h>
+ #include <i2c.h>
+@@ -252,8 +253,8 @@ void detail_board_ddr_info(void)
+ 	print_ddr_info(0);
+ }
+ 
+-#if defined(CONFIG_ARCH_MISC_INIT)
+-int arch_misc_init(void)
++#ifdef CONFIG_MISC_INIT_R
++int misc_init_r(void)
+ {
+ 	config_board_mux();
+ 
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 62ff236e71..8c2a6b338b 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -3,6 +3,9 @@ CONFIG_TARGET_LX2160ACEX7=y
+ CONFIG_TFABOOT=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_ENV_SIZE=0x2000
++CONFIG_ENV_SECT_SIZE=0x20000
++CONFIG_ENV_OFFSET=0x500000
+ CONFIG_FSPI_AHB_EN_4BYTE=y
+ CONFIG_NR_DRAM_BANKS=3
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+@@ -15,6 +18,7 @@ CONFIG_BOOTDELAY=10
+ CONFIG_USE_BOOTARGS=y
+ CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+ # CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_MISC_INIT_R=y
+ CONFIG_CMD_GREPENV=y
+ CONFIG_CMD_EEPROM=y
+ CONFIG_CMD_GPT=y
+@@ -23,6 +27,7 @@ CONFIG_CMD_MMC=y
+ CONFIG_CMD_PCI=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
++CONFIG_CMD_WDT=y
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_NVME=y
+ CONFIG_NVME=y
+@@ -32,6 +37,7 @@ CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_ENV_ADDR=0x20500000
+ CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_DM=y
+ CONFIG_SATA_CEVA=y
+@@ -63,7 +69,7 @@ CONFIG_CMD_MII=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_EXT2=y
+-CONFIG_CMD_SYS_EEPROM=y
++CONFIG_CMD_TLV_EEPROM=y
+ CONFIG_E1000=y
+ CONFIG_PCI=y
+ CONFIG_DM_PCI=y
+@@ -83,8 +89,16 @@ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
++CONFIG_WDT=y
++CONFIG_WDT_SBSA=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+ CONFIG_CMD_DATE=y
+ CONFIG_RTC_PCF2127=y
+ CONFIG_CMD_MEMORY=y
+ CONFIG_CMD_MEMTEST=y
++CONFIG_GIC_V3_ITS=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_OPTEE_TA_AVB=y
++CONFIG_SUPPORT_EMMC_RPMB=y
++CONFIG_CMD_OPTEE_RPMB=y
+-- 
+2.25.1
+

runme.sh

@@ -12,17 +12,26 @@ BUILDROOT_VERSION=2020.02.1
 ###############################################################################
 # Misc
 ###############################################################################
-RELEASE=${RELEASE:-LSDK-20.04}
+RELEASE=${RELEASE:-LSDK-20.12}
 DDR_SPEED=${DDR_SPEED:-3200}
 SERDES=${SERDES:-8_5_2}
 UEFI_RELEASE=${UEFI_RELEASE:-RELEASE}
 SHALLOW=${SHALLOW:false}
-
+SECURE=${SECURE:false}
+ATF_DEBUG=${ATF_DEBUG:false}
 
 if [ "x$SHALLOW" == "xtrue" ]; then
 	SHALLOW_FLAG="--depth 1"
 fi
 
+if [ "x$ATF_DEBUG" == "xtrue" ]; then
+	ATF_DEBUG="DEBUG=1 LOG_LEVEL=40"
+	ATF_BUILD="debug"
+else
+	ATF_DEBUG=""
+	ATF_BUILD="release"
+fi
+
 mkdir -p build images
 ROOTDIR=`pwd`
 PARALLEL=$(getconf _NPROCESSORS_ONLN) # Amount of parallel jobs for the builds
@@ -105,12 +114,17 @@ cd $ROOTDIR
 ###############################################################################
 # source code cloning
 ###############################################################################
-QORIQ_COMPONENTS="u-boot atf rcw restool mc-utils linux dpdk"
+QORIQ_COMPONENTS="u-boot atf rcw restool mc-utils linux dpdk cst"
 for i in $QORIQ_COMPONENTS; do
 	if [[ ! -d $ROOTDIR/build/$i ]]; then
 		echo "Cloing https://source.codeaurora.org/external/qoriq/qoriq-components/$i release $RELEASE"
 		cd $ROOTDIR/build
 		CHECKOUT=$RELEASE
+		# Release LSDK-20.12
+		if [ "x$i" == "xlinux" ] && [ "x$RELEASE" == "xLSDK-20.12" ]; then
+			CHECKOUT=LSDK-20.12-V5.4
+		fi
+		# Release LSDK-20.4
 		if [ "x$i" == "xu-boot" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
 			CHECKOUT=LSDK-20.04-update-290520
 		fi
@@ -123,9 +137,6 @@ for i in $QORIQ_COMPONENTS; do
 		if [ "x$i" == "xrcw" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
 			CHECKOUT=LSDK-20.04-update-290520
 		fi
-		if [ "x$i" == "xdpdk" ] && [ "x$RELEASE" == "xLSDK-20.04" ]; then
-			CHECKOUT=LSDK-19.09
-		fi
 		git clone $SHALLOW_FLAG https://source.codeaurora.org/external/qoriq/qoriq-components/$i -b $CHECKOUT
 		cd $i
 		if [ "x$i" == "xatf" ]; then
@@ -225,27 +236,50 @@ echo "#include <configs/lx2160a_${SPEED}.rcwi>" >> RCW/template.rcw
 echo "#include <configs/lx2160a_SD1_${arr[0]}.rcwi>" >> RCW/template.rcw
 echo "#include <configs/lx2160a_SD2_${arr[1]}.rcwi>" >> RCW/template.rcw
 echo "#include <configs/lx2160a_SD3_${arr[2]}.rcwi>" >> RCW/template.rcw
+if [ "x$SECURE" == "xtrue" ]; then
+	echo "SB_EN=1" #>> RCW/template.rcw
+fi
 IFS=$OLDIFS
 make clean
 make -j${PARALLEL}
 
+if [ "x$SECURE" == "xtrue" ]; then
+	echo "Building CST"
+	cd $ROOTDIR/build/cst
+	make
+	./gen_fusescr input_files/gen_fusescr/ls2088_1088/input_fuse_file
+fi
+
 echo "Build u-boot"
 cd $ROOTDIR/build/u-boot
 #make distclean
-make lx2160acex7_tfa_defconfig
+if [ "x$SECURE" == "xtrue" ]; then
+	make lx2160acex7_tfa_SECURE_BOOT_defconfig
+else
+	make lx2160acex7_tfa_defconfig
+fi
 make -j${PARALLEL}
 export BL33=$ROOTDIR/build/u-boot/u-boot.bin
 
 echo "Building atf"
 cd $ROOTDIR/build/atf/
 make PLAT=lx2160acex7 clean
-make -j${PARALLEL} PLAT=lx2160acex7 all fip pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=0 GENERATE_COT=0 BOOT_MODE=auto SECURE_BOOT=false
+if [ "x$SECURE" == "xtrue" ]; then
+	if [ ! -f "srk.pub" ] || [ ! -f "srk.pri" ]; then
+		echo "Create srk.pub and srk.pri pair via ./gen_keys 4096 under $ROOTDIR/build/cst and place them under $ROOTDIR/build/atf"
+		exit -1
+	fi
+	# Following is without COT
+	cp tools/fiptool/ddr-phy-binary/lx2160a/*.bin .
+	make -j1 PLAT=lx2160acex7 all fip fip_ddr_sec fip_fuse pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=1 CST_DIR=$ROOTDIR/build/cst/ GENERATE_COT=0 BOOT_MODE=auto SECURE_BOOT=true FUSE_PROG=1 FUSE_PROV_FILE=$ROOTDIR/build/cst/fuse_scr.bin $ATF_DEBUG
+else
+	make -j${PARALLEL} PLAT=lx2160acex7 all fip pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=0 GENERATE_COT=0 BOOT_MODE=auto SECURE_BOOT=false
+fi
 
 echo "Building mc-utils"
 cd $ROOTDIR/build/mc-utils
 make -C config/
 
-
 echo "Building the kernel"
 cd $ROOTDIR/build/linux
 ./scripts/kconfig/merge_config.sh arch/arm64/configs/defconfig arch/arm64/configs/lsdk.config $ROOTDIR/configs/linux/lx2k_additions.config
@@ -322,11 +356,11 @@ cd $ROOTDIR/build/dpdk
 export CROSS=$CROSS_COMPILE
 export RTE_SDK=$ROOTDIR/build/dpdk
 export DESTDIR=$ROOTDIR/build/dpdk/install
-export RTE_TARGET=arm64-dpaa2-linuxapp-gcc
-#make -j32 T=arm64-dpaa2-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n clean
-make -j32 T=arm64-dpaa2-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n install
-make -j32 T=arm64-dpaa2-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l2fwd install
-make -j32 T=arm64-dpaa2-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l3fwd install
+export RTE_TARGET=arm64-dpaa-linuxapp-gcc
+#make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n clean
+make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n install
+make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l2fwd install
+make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l3fwd install
 
 
 ###############################################################################
@@ -397,31 +431,40 @@ truncate -s 463M $ROOTDIR/images/tmp/boot.part
 mkfs.ext4 -b 4096 -F $ROOTDIR/images/tmp/boot.part
 \rm -rf $ROOTDIR/images/tmp/xspi_header.img
 truncate -s 128K $ROOTDIR/images/tmp/xspi_header.img
-dd if=$ROOTDIR/build/atf/build/lx2160acex7/release/bl2_auto.pbl of=$ROOTDIR/images/tmp/xspi_header.img bs=512 conv=notrunc
+dd if=$ROOTDIR/build/atf/build/lx2160acex7/${ATF_BUILD}/bl2_auto.pbl of=$ROOTDIR/images/tmp/xspi_header.img bs=512 conv=notrunc
 e2cp -G 0 -O 0 $ROOTDIR/images/tmp/xspi_header.img $ROOTDIR/images/tmp/boot.part:/
 
 # PFE firmware at 0x100
 
 # FIP (BL31+BL32+BL33) at 0x800
-dd if=$ROOTDIR/build/atf/build/lx2160acex7/release/fip.bin of=images/${IMG} bs=512 seek=2048 conv=notrunc
+dd if=$ROOTDIR/build/atf/build/lx2160acex7/${ATF_BUILD}/fip.bin of=images/${IMG} bs=512 seek=2048 conv=notrunc
 
 # DDR PHY FIP at 0x4000
-dd if=$ROOTDIR/build/atf/tools/fiptool/fip_ddr_all.bin of=images/${IMG} bs=512 seek=16384 conv=notrunc
+if [ "x$SECURE" == "xtrue" ]; then
+	dd if=$ROOTDIR/build/atf/fip_ddr_sec.bin of=images/${IMG} bs=512 seek=16384 conv=notrunc
+else
+	dd if=$ROOTDIR/build/atf/tools/fiptool/fip_ddr_all.bin of=images/${IMG} bs=512 seek=16384 conv=notrunc
+fi
+
 # Env variables at 0x2800
 
 # Secureboot headers at 0x3000
 
+# Fuse header FIP at 0x4400
+if [ "x$SECURE" == "xtrue" ]; then
+	dd if=$ROOTDIR/build/atf/build/lx2160acex7/${ATF_BUILD}/fuse_fip.bin of=images/${IMG} bs=512 seek=17408 conv=notrunc
+fi
+
 # DPAA1 FMAN ucode at 0x4800
 
 # DPAA2-MC at 0x5000
-if [ "x$RELEASE" == "xLSDK-19.09" ]; then
-	MC=mc_10.18.0_lx2160a.itb
-elif [ "x$RELEASE" == "xlx2160a-early-access-bsp0.7" ]; then
-	MC=mc_10.20.1_lx2160a.itb
+if [ "x$RELEASE" == "xLSDK-20.04" ]; then
+	MC=mc_10.24.0_lx2160a.itb
+	dd if=$ROOTDIR/build/qoriq-mc-binary/lx2160a/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
 else
-	MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx2160a/ | cut -f1`
+	MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/ | cut -f1`
+	dd if=$ROOTDIR/build/qoriq-mc-binary/lx216xa/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
 fi
-dd if=$ROOTDIR/build/qoriq-mc-binary/lx2160a/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
 
 # DPAA2 DPL at 0x6800
 dd if=$ROOTDIR/build/mc-utils/config/lx2160a/CEX7/${DPL} of=images/${IMG} bs=512 seek=26624 conv=notrunc
@@ -435,8 +478,8 @@ dd if=$ROOTDIR/build/linux/kernel-lx2160acex7.itb of=images/${IMG} bs=512 seek=3
 # Ramdisk at 0x10000
 # RCW+PBI+BL2 at block 8
 dd if=$ROOTDIR/images/${IMG} of=$ROOTDIR/images/lx2160acex7_xspi_${SPEED}_${SERDES}-${REPO_PREFIX}.img bs=1M count=64
-dd if=$ROOTDIR/build/atf/build/lx2160acex7/release/bl2_auto.pbl of=images/lx2160acex7_xspi_${SPEED}_${SERDES}-${REPO_PREFIX}.img bs=512 conv=notrunc
-dd if=$ROOTDIR/build/atf/build/lx2160acex7/release/bl2_auto.pbl of=images/${IMG} bs=512 seek=8 conv=notrunc
+dd if=$ROOTDIR/build/atf/build/lx2160acex7/${ATF_BUILD}/bl2_auto.pbl of=images/lx2160acex7_xspi_${SPEED}_${SERDES}-${REPO_PREFIX}.img bs=512 conv=notrunc
+dd if=$ROOTDIR/build/atf/build/lx2160acex7/${ATF_BUILD}/bl2_auto.pbl of=images/${IMG} bs=512 seek=8 conv=notrunc
 
 # Copy first 64MByte from image excluding MBR to ubuntu-core.img for eMMC boot
 dd if=images/${IMG} of=$ROOTDIR/images/tmp/ubuntu-core.img bs=512 seek=1 skip=1 count=131071 conv=notrunc