Skip to content

L
lx2160a_build
Commit a393e2e7 authored by Rabeeh Khoury's avatar Rabeeh Khoury
Browse files
Options

Move to LSDK-21.08 and support LX2162-SOM 

Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent bc46e348
Show whitespace changes
Inline Side-by-side
Showing with 10423 additions and 23 deletions
configs/linux/lx2k_additions.config
View file @ a393e2e7
......@@ -32,6 +32,7 @@ CONFIG_SENSORS_AMC6821=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LTC2978=y
CONFIG_SENSORS_LTC2978_REGULATOR=y
CONFIG_SENSORS_TPS53679=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
......
patches/atf-LSDK-21.08/0001-plat-nxp-Add-lx2160acex7-module-support.patch 0 → 100644
View file @ a393e2e7
From 0aed3cda581d98ac755775ef3f490d6f1b3e9e01 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 5 Sep 2021 17:02:09 +0300
Subject: [PATCH 1/4] plat/nxp: Add lx2160acex7 module support
Adds SolidRun's LX2160A based SoC COM express type 7 module support.
The patch is based on LX2160ARDB board and modifies the support to two
SO-DIMMs DDR4 support on I2C address 0x51 and 0x53.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c | 101 +++++++++++++++++
plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h | 103 ++++++++++++++++++
plat/nxp/soc-lx2160a/lx2160acex7/platform.c | 30 +++++
plat/nxp/soc-lx2160a/lx2160acex7/platform.mk | 48 ++++++++
.../soc-lx2160a/lx2160acex7/platform_def.h | 15 +++
plat/nxp/soc-lx2160a/lx2160acex7/policy.h | 39 +++++++
6 files changed, 336 insertions(+)
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.c
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/policy.h
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
new file mode 100644
index 000000000..3e1881d4a
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2019 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+#include <load_img.h>
+
+#include "plat_common.h"
+#include <platform_def.h>
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ struct memctl_opt *popts = &priv->opt;
+
+ popts->vref_dimm = 0x24; /* range 1, 83.4% */
+ popts->rtt_override = 0;
+ popts->rtt_park = 240;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->trwt_override = 1;
+ popts->bstopre = 0; /* auto precharge */
+ popts->addr_hash = 1;
+ popts->trwt = 0x3;
+ popts->twrt = 0x3;
+ popts->trrt = 0x3;
+ popts->twwt = 0x3;
+ popts->vref_phy = 0x60; /* 75% */
+ popts->odt = 48;
+ popts->phy_tx_impedance = 48;
+
+ return 0;
+}
+
+long long init_ddr(void)
+{
+ int spd_addr[] = { 0x51, 0x53 };
+ struct ddr_info info;
+ struct sysinfo sys;
+ long long dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys) == 1) {
+ ERROR("System clocks are not set\n");
+ assert(0);
+ }
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(info));
+
+ /* Set two DDRC. Unused DDRC will be removed automatically. */
+ info.num_ctlrs = NUM_OF_DDRC;
+ info.spd_addr = spd_addr;
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+ info.ddr[1] = (void *)NXP_DDR2_ADDR;
+ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
+ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
+ info.clk = get_ddr_freq(&sys, 0);
+ info.img_loadr = load_img;
+ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
+ if (info.clk == 0) {
+ info.clk = get_ddr_freq(&sys, 1);
+ }
+ info.dimm_on_ctlr = DDRC_NUM_DIMM;
+
+ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
+#ifdef NXP_WARM_BOOT
+ if (wrm_bt_flg) {
+ info.warm_boot_flag = DDR_WARM_BOOT;
+ } else if (wrm_bt_flg == 0x0) {
+ info.warm_boot_flag = DDR_COLD_BOOT;
+ }
+#endif
+
+ dram_size = dram_init(&info
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , NXP_CCN_HN_F_0_ADDR
+#endif
+ );
+
+
+ if (dram_size < 0)
+ ERROR("DDR init failed.\n");
+
+ return dram_size;
+}
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
new file mode 100644
index 000000000..08db34dc2
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+#include <cortex_a72.h>
+#include <policy.h>
+#include <soc.h>
+/* Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+
+#if defined(IMAGE_BL31)
+#define LS_SYS_TIMCTL_BASE 0x2890000
+#define PLAT_LS_NSTIMER_FRAME_ID 0
+#define LS_CONFIG_CNTACR 1
+#endif
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+
+#ifdef SD_BOOT
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+#else
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+#endif
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 3
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+#define BL31_WDOG_SEC 89
+
+#define BL31_NS_WDOG_WS1 108
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
+#define PLAT_LS_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.c b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c
new file mode 100644
index 000000000..3186cc9a1
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
new file mode 100644
index 000000000..eabf6f580
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
@@ -0,0 +1,48 @@
+#
+# Copyright 2021 SolidRun ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Author Rabeeh Khoury <rabeeh@solid-run.com>
+
+# board-specific build parameters
+
+BOOT_MODE ?= flexspi_nor
+BOARD ?= lx2160acex7
+POVDD_ENABLE := no
+NXP_COINED_BB := no
+
+ # DDR Compilation Configs
+NUM_OF_DDRC := 2
+DDRC_NUM_DIMM := 1
+DDRC_NUM_CS := 2
+DDR_ECC_EN := yes
+ #enable address decoding feature
+DDR_ADDR_DEC := yes
+APPLY_MAX_CDD := yes
+
+ # On-Board Flash Details
+FLASH_TYPE := MT35XU512A
+XSPI_FLASH_SZ := 0x10000000
+NXP_XSPI_NOR_UNIT_SIZE := 0x20000
+BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
+# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
+# config is enabled for future use cases.
+FSPI_ERASE_4K := 0
+
+ # Platform specific features.
+WARM_BOOT := no
+
+ # Adding Platform files build files
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
+ ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE := flexspi_nor \
+ sd \
+ emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_common_def.mk
+
+ # Adding SoC build info
+include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
new file mode 100644
index 000000000..0e621d686
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2021 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include "plat_def.h"
+#include "plat_default_def.h"
+
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/policy.h b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h
new file mode 100644
index 000000000..da44acee3
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2021 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author : Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/* Following defines affect the PLATFORM SECURITY POLICY */
+
+/* set this to 0x0 if the platform is not using/responding to ECC errors
+ * set this to 0x1 if ECC is being used (we have to do some init)
+ */
+#define POLICY_USING_ECC 0x0
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+/*
+ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
+ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
+ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
+ */
+#define POLICY_PERF_WRIOP 0
+
+/*
+ * set this to '1' if the debug clocks need to remain enabled during
+ * system entry to low-power (LPM20) - this should only be necessary
+ * for testing and NEVER set for normal production
+ */
+#define POLICY_DEBUG_ENABLE 0
+
+
+#endif /* POLICY_H */
--
2.25.1
patches/atf-LSDK-21.08/0002-plat-nxp-Add-lx2162-som-support.patch 0 → 100644
View file @ a393e2e7
From f438a4ae56663a82d0ffbf02cddf5e67be54932a Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Nov 2021 13:28:56 +0200
Subject: [PATCH 2/4] plat/nxp: Add lx2162-som support
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
index 3e1881d4a..eb28216e7 100644
--- a/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
@@ -25,6 +25,7 @@
int ddr_board_options(struct ddr_info *priv)
{
struct memctl_opt *popts = &priv->opt;
+ uint32_t svr;
popts->vref_dimm = 0x24; /* range 1, 83.4% */
popts->rtt_override = 0;
@@ -42,7 +43,20 @@ int ddr_board_options(struct ddr_info *priv)
popts->odt = 48;
popts->phy_tx_impedance = 48;
+ svr = mmio_read_32(NXP_DCFG_ADDR + DCFG_SVR_OFFSET);
+ /* LX2162-SOM */
+ if (svr & 0x800) {
+ popts->vref_dimm = 0x19;
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 0x5;
+ popts->output_driver_impedance = 1;
+ popts->rtt_park = 120;
+ popts->phy_atx_impedance = 20;
+ popts->vref_phy = 0x4D;
+ popts->odt = 60;
+ }
return 0;
+
}
long long init_ddr(void)
--
2.25.1
patches/atf-LSDK-21.08/0003-lx2160acex7-assert-SUS_S5-GPIO-to-poweroff-the-COM.patch 0 → 100644
View file @ a393e2e7
From 1b9476295392acce9acdf3b34915d2da7abe5931 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Nov 2021 13:33:10 +0200
Subject: [PATCH 3/4] lx2160acex7: assert SUS_S5# GPIO to poweroff the COM
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/soc-lx2160a/aarch64/lx2160a.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
index 8bd06e765..8853e6e00 100644
--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
@@ -545,6 +545,10 @@ func _soc_sys_off
* spurious timeout reset request
* workaround: MASK RESET REQ RPTOE
*/
+ mov x3, #NXP_GPIO3_ADDR
+ mov w1, #0x01000000
+ str w1, [x3]
+
ldr x0, =NXP_RESET_ADDR
ldr w1, =RSTRQMR_RPTOE_MASK
str w1, [x0, #RST_RSTRQMR1_OFFSET]
--
2.25.1
patches/atf-LSDK-21.08/0004-plat-nxp-lx2160a-auto-boot.patch 0 → 100644
View file @ a393e2e7
From 980766e63965cd21c00e601d5b2106fbc6764266 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Nov 2021 14:00:07 +0200
Subject: [PATCH 4/4] plat/nxp: lx2160a auto boot
This patch adds support to patch RCW that already has SD/eMMC/SPI boot
support embedded with conditional load and jump.
The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size
address with the correct values; rather than adding blockread at the end
of RCW code.
With this patch images are unified and can be used to boot from SD /
eMMC and SPI.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/common/plat_common_def.mk | 5 ++
plat/nxp/soc-lx2160a/lx2160acex7/platform.mk | 3 +-
tools/nxp/create_pbl.c | 65 +++++++++++++++++---
3 files changed, 62 insertions(+), 11 deletions(-)
diff --git a/plat/nxp/common/plat_common_def.mk b/plat/nxp/common/plat_common_def.mk
index 45dd22353..aa5851254 100644
--- a/plat/nxp/common/plat_common_def.mk
+++ b/plat/nxp/common/plat_common_def.mk
@@ -88,6 +88,11 @@ define add_boot_mode_define
else ifeq ($(1),flexspi_nor)
$$(eval $$(call SET_FLAG,XSPI_NEEDED,BL2))
$$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
+ else ifeq ($(1),auto)
+ $$(eval $$(call SET_FLAG,SD_MMC_NEEDED,BL2))
+ $$(eval $$(call add_define,EMMC_BOOT))
+ $$(eval $$(call SET_FLAG,XSPI_NEEDED,BL2))
+ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
endif
endef
diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
index eabf6f580..98cbc22e7 100644
--- a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
@@ -39,7 +39,8 @@ BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
SUPPORTED_BOOT_MODE := flexspi_nor \
sd \
- emmc
+ emmc \
+ auto
# Adding platform board build info
include plat/nxp/common/plat_common_def.mk
diff --git a/tools/nxp/create_pbl.c b/tools/nxp/create_pbl.c
index bbf9ada5f..151d75a76 100644
--- a/tools/nxp/create_pbl.c
+++ b/tools/nxp/create_pbl.c
@@ -65,6 +65,7 @@ typedef enum {
FLXSPI_NOR_BOOT,
FLXSPI_NAND_BOOT,
FLXSPI_NAND4K_BOOT,
+ AUTO_BOOT,
MAX_BOOT /* must be last item in list */
} boot_src_t;
@@ -192,7 +193,7 @@ struct pbl_image {
#define SOC_LS2088 2088
#define SOC_LX2160 2160
-static uint32_t pbl_size;
+static uint32_t pbl_size = 0;
bool sb_flag;
/***************************************************************************
@@ -697,6 +698,8 @@ int main(int argc, char **argv)
int ret = FAILURE;
bool bootptr_flag = false;
enum stop_command flag_stop_cmd = CRC_STOP_COMMAND;
+ int skip = 0;
+ uint32_t saved_src;
/* Initializing the global structure to zero. */
memset(&pblimg, 0x0, sizeof(struct pbl_image));
@@ -796,6 +799,8 @@ int main(int argc, char **argv)
pblimg.boot_src = FLXSPI_NAND_BOOT;
else if (!strcmp(optarg, "flexspi_nand2k"))
pblimg.boot_src = FLXSPI_NAND4K_BOOT;
+ else if (!strcmp(optarg, "auto"))
+ pblimg.boot_src = AUTO_BOOT;
else {
printf("CMD Error: Invalid boot source.\n");
goto exit_main;
@@ -897,13 +902,14 @@ int main(int argc, char **argv)
printf("%s: Error reading PBI Cmd.\n", __func__);
goto exit_main;
}
+ saved_src = pblimg.src_addr;
while (word != 0x808f0000 && word != 0x80ff0000) {
pbl_size++;
/* 11th words in RCW has PBL length. Update it
* with new length. 2 comamnds get added
* Block copy + CCSR Write/CSF header write
*/
- if (pbl_size == 11) {
+ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) {
word_1 = (word & PBI_LEN_MASK)
+ (PBI_LEN_ADD << 20);
word = word & ~PBI_LEN_MASK;
@@ -920,8 +926,44 @@ int main(int argc, char **argv)
if (word == FAILURE)
goto exit_main;
}
- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
- fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ if (pblimg.boot_src == AUTO_BOOT) {
+ if (word == 0x80000008) {
+ printf ("Found SD boot at %d\n",pbl_size);
+ pblimg.boot_src = SD_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ if (word == 0x80000009) {
+ printf ("Found eMMC boot at %d\n",pbl_size);
+ pblimg.boot_src = EMMC_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ if (word == 0x8000000f) {
+ printf ("Found SPI boot at %d\n",pbl_size);
+ pblimg.boot_src = FLXSPI_NOR_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ }
+ if (!skip &&
+ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) {
printf("%s: [CH3] Error in Writing PBI Words\n",
__func__);
goto exit_main;
@@ -937,8 +979,9 @@ int main(int argc, char **argv)
flag_stop_cmd = CRC_STOP_COMMAND;
else if (word == STOP_CMD_ARM_CH3)
flag_stop_cmd = STOP_COMMAND;
+ if (skip) skip--;
}
- if (bootptr_flag == true) {
+ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) {
/* Add command to set boot_loc ptr */
ret = add_boot_ptr_cmd(fp_rcw_pbi_op);
if (ret != SUCCESS) {
@@ -949,11 +992,13 @@ int main(int argc, char **argv)
}
/* Write acs write commands to output file */
- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
- if (ret != SUCCESS) {
- printf("%s: Function add_blk_cpy_cmd return failure.\n",
- __func__);
- goto exit_main;
+ if (pblimg.boot_src != AUTO_BOOT) {
+ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ if (ret != SUCCESS) {
+ printf("%s: Function add_blk_cpy_cmd return failure.\n",
+ __func__);
+ goto exit_main;
+ }
}
/* Add stop command after adding pbi commands */
--
2.25.1
patches/linux-LSDK-21.08/0001-arch-arm64-dts-lx2162-add-som-and-solidnet-device-tr.patch 0 → 100644
View file @ a393e2e7
From 28aacde9406bd28c8660b1065d21e58a6bec570a Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 16:43:00 +0200
Subject: [PATCH] arch: arm64: dts: lx2162 add som and solidnet device trees
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/fsl-lx2162a-solidnet.dts | 31 +++++
.../boot/dts/freescale/fsl-lx2162a-som.dtsi | 109 ++++++++++++++++++
3 files changed, 141 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-solidnet.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index cfb8166a6aa3..eaf7319389b6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-solidnet.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-solidnet.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-solidnet.dts
new file mode 100644
index 000000000000..2878a460183f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-solidnet.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2162A SolidNet
+//
+// Copyright 2021 SolidRun ltd. (Rabeeh@solid-run.com)
+
+/dts-v1/;
+
+#include "fsl-lx2162a-som.dtsi"
+
+/ {
+ model = "SolidRun LX2162A based SolidNet";
+ compatible = "fsl,lx2162a-dpu", "fsl,lx2160a";
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&dpmac5 {
+ phy-connection-type = "usxgmii";
+ managed = "in-band-status";
+};
+
+&dpmac6 {
+ phy-connection-type = "usxgmii";
+ managed = "in-band-status";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
new file mode 100644
index 000000000000..9b90cef2df04
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-som.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2162A-SOM
+//
+// Copyright 2021 SolidRun Ltd. (rabeeh@solid-run.com)
+
+
+#include "fsl-lx2160a.dtsi"
+
+&crypto {
+ status = "okay";
+};
+
+&dpmac17 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ lx2162a-som-fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ tps5622@69 {
+ compatible = "tps53679";
+ reg = <0x69>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+ rtc@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
+};
+
+&fspi {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+
--
2.25.1
patches/mc-utils/0005-lx2160acex7-add-dpc-dpl-for-sd1-protocol-18.patch 0 → 100644
View file @ a393e2e7
From c9a78458b318f35a1e9da787b1cf254b0a334710 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 16:55:07 +0200
Subject: [PATCH] lx2160acex7: add dpc/dpl for sd1 protocol #18
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
config/lx2160a/CEX7/dpc-sd1-18.dts | 91 ++++++
config/lx2160a/CEX7/dpl-sd1-18.dts | 470 +++++++++++++++++++++++++++++
2 files changed, 561 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-sd1-18.dts
create mode 100644 config/lx2160a/CEX7/dpl-sd1-18.dts
diff --git a/config/lx2160a/CEX7/dpc-sd1-18.dts b/config/lx2160a/CEX7/dpc-sd1-18.dts
new file mode 100644
index 0000000..3aeb1d2
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-sd1-18.dts
@@ -0,0 +1,91 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-sd1-18.dts b/config/lx2160a/CEX7/dpl-sd1-18.dts
new file mode 100644
index 0000000..1442fa2
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-sd1-18.dts
@@ -0,0 +1,470 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ dpl-version = <0xa>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+ dprc@1 {
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
+ /* ------------ DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0x0>;
+ };
+
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0x11>;
+ };
+
+
+ /* ------------ DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0x0 0x1>;
+ };
+
+ /* ------------ DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+
+ /* ------------ DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+
+ /* ------------ DPCON --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ obj@700 {
+ obj_name = "dpseci@0";
+ };
+
+ /* ------------ DPRTC --------------*/
+ obj@800 {
+ obj_name="dprtc@0";
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ /* ------------ DPNI --------------*/
+ dpni@0 {
+ options = "";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+
+ dpni@1 {
+ options = "";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+
+
+ dpmac@3 {
+ };
+
+ dpmac@4 {
+ };
+
+ dpmac@5 {
+ };
+
+ dpmac@6 {
+ };
+
+ dpmac@17 {
+ };
+
+ /* ------------ DPBP --------------*/
+ dpbp@0 {
+ };
+
+ dpbp@1 {
+ };
+
+
+ /* ------------ DPIO --------------*/
+ dpio@0 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ /* ------------ DPMCP --------------*/
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+
+ /* ------------ DPCON --------------*/
+ dpcon@0 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ num_priorities = <0x2>;
+ };
+ dpcon@16 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ num_priorities = <0x2>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ dpseci@0 {
+ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
+ options = "DPSECI_OPT_HAS_CG";
+ };
+
+ /* ------------ DPRTC --------------*/
+ dprtc@0 {
+ compatible="fsl,dprtc";
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ connection@1 {
+ endpoint1 = "dpni@0";
+ endpoint2 = "dpmac@17";
+ };
+ };
+};
+
--
2.25.1
patches/rcw-LSDK-21.08/0001-lx2160acex7-misc-RCW-files.patch 0 → 100644
View file @ a393e2e7
From ef5ab1b5a7262a6ef9caf334b0c772b0ebf00fdf Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 14:43:06 +0300
Subject: [PATCH] lx2160acex7 misc RCW files
This patch adds support for lx2160a rcw project.
In general RCW has lots of redundent files and can be restructured
better as in this patch.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/Makefile | 2 +
lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 +++++++++++++++++++
.../rcw_1900_600_2600_17_4_2.rcw | 4 ++
.../rcw_1900_600_2600_17_4_2_sd.rcw | 4 ++
.../rcw_2000_700_2400_13_5_2_sd.rcw | 4 ++
.../rcw_2000_700_2400_20_5_2_sd.rcw | 4 ++
.../rcw_2000_700_2400_8_5_2_sd.rcw | 4 ++
.../rcw_2000_700_2600_8_5_2_sd.rcw | 4 ++
.../rcw_2000_700_2900_17_4_2_sd.rcw | 4 ++
.../rcw_2000_700_2900_8_5_2_sd.rcw | 4 ++
.../rcw_2000_700_3200_17_4_2_sd.rcw | 4 ++
.../rcw_2000_700_3200_20_5_2_sd.rcw | 4 ++
.../rcw_2000_700_3200_8_5_0_sd.rcw | 4 ++
.../rcw_2000_700_3200_8_5_2_sd.rcw | 4 ++
.../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 ++
.../rcw_2400_700_3200_8_5_2_sd.rcw | 4 ++
.../rcw_2500_700_3200_8_5_2_sd.rcw | 4 ++
.../rcw_2600_700_3200_8_5_2_sd.rcw | 4 ++
.../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 ++
lx2160acex7/configs/lx2160a_13_5_2.rcwi | 3 +
lx2160acex7/configs/lx2160a_17_4_2.rcwi | 7 +++
.../configs/lx2160a_1900_600_2600.rcwi | 12 ++++
.../configs/lx2160a_2000_700_2400.rcwi | 12 ++++
.../configs/lx2160a_2000_700_2600.rcwi | 12 ++++
.../configs/lx2160a_2000_700_2900.rcwi | 12 ++++
.../configs/lx2160a_2000_700_3200.rcwi | 12 ++++
lx2160acex7/configs/lx2160a_20_5_2.rcwi | 7 +++
.../configs/lx2160a_2400_700_3200.rcwi | 12 ++++
.../configs/lx2160a_2500_700_3200.rcwi | 12 ++++
.../configs/lx2160a_2600_700_3200.rcwi | 12 ++++
lx2160acex7/configs/lx2160a_8_5_0.rcwi | 7 +++
lx2160acex7/configs/lx2160a_8_5_2.rcwi | 7 +++
lx2160acex7/configs/lx2160a_defaults.rcwi | 19 ++++++
lx2160acex7/configs/lx2160a_sdboot.rcwi | 20 ++++++
lx2160acex7/configs/lx2160a_test.rcwi | 20 ++++++
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 17 ++++++
36 files changed, 334 insertions(+)
create mode 100644 lx2160acex7/Makefile
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
create mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_20_5_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_8_5_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_defaults.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_sdboot.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_test.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_xspiboot.rcwi
diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile
new file mode 100644
index 0000000..d7e9447
--- /dev/null
+++ b/lx2160acex7/Makefile
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
new file mode 100644
index 0000000..cdb6446
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
@@ -0,0 +1,61 @@
+/*
+ * SerDes Protocol 1 - 19
+ * SerDes Protocol 2 - 5
+ * SerDes Protocol 3 - 2
+ *
+ * Frequencies:
+ * Core -- 1900 MHz
+ * Platform -- 600 MHz
+ * DDR -- 2600 MT/s
+ */
+
+#include <../lx2160asi/lx2160a.rcwi>
+
+SYS_PLL_RAT=12
+MEM_PLL_CFG=3
+MEM_PLL_RAT=26
+MEM2_PLL_CFG=3
+MEM2_PLL_RAT=26
+CGA_PLL1_RAT=19
+CGA_PLL2_RAT=19
+CGB_PLL1_RAT=19
+CGB_PLL2_RAT=9
+C5_PLL_SEL=0
+C6_PLL_SEL=0
+C7_PLL_SEL=0
+C8_PLL_SEL=0
+HWA_CGA_M1_CLK_SEL=1
+HWA_CGB_M1_CLK_SEL=7
+BOOT_LOC=26
+SYSCLK_FREQ=600
+IIC2_PMUX=6
+IIC3_PMUX=2
+IIC4_PMUX=2
+USB3_CLK_FSEL=39
+SRDS_PRTCL_S1=19
+SRDS_PRTCL_S2=5
+SRDS_PRTCL_S3=2
+SRDS_PLL_REF_CLK_SEL_S1=2
+SRDS_DIV_PEX_S1=1
+SRDS_DIV_PEX_S2=3
+SRDS_DIV_PEX_S3=1
+
+/* Errata to write on scratch reg for validation */
+#include <../lx2160asi/scratchrw1.rcw>
+
+/* Copy SPL Uboot to Ocram */
+.pbi
+blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+.end
+
+/* Boot Location Pointer */
+#include <../lx2160asi/bootlocptr_sd.rcw>
+
+/* Errata for SATA controller */
+#include <../lx2160asi/a010554.rcw>
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_24.rcw>
+
+/* common PBI commands */
+#include <../lx2160asi/common.rcw>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
new file mode 100644
index 0000000..13ab0b9
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_1900_600_2600.rcwi>
+#include <configs/lx2160a_17_4_2.rcwi>
+#include <configs/lx2160a_xspiboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
new file mode 100644
index 0000000..14fae8c
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_1900_600_2600.rcwi>
+#include <configs/lx2160a_17_4_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
new file mode 100644
index 0000000..2dae5a2
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2400.rcwi>
+#include <configs/lx2160a_13_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
new file mode 100644
index 0000000..5335072
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2400.rcwi>
+#include <configs/lx2160a_20_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
new file mode 100644
index 0000000..e2a5bd3
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2400.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
new file mode 100644
index 0000000..a330bfe
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2600.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
new file mode 100644
index 0000000..8535dbd
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2900.rcwi>
+#include <configs/lx2160a_17_4_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
new file mode 100644
index 0000000..698be01
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_2900.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
new file mode 100644
index 0000000..780d8c3
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_3200.rcwi>
+#include <configs/lx2160a_17_4_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
new file mode 100644
index 0000000..eb9d240
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_3200.rcwi>
+#include <configs/lx2160a_20_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
new file mode 100644
index 0000000..ceb53a3
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_3200.rcwi>
+#include <configs/lx2160a_8_5_0.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
new file mode 100644
index 0000000..a220e98
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_3200.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
new file mode 100644
index 0000000..1eabd7d
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2000_700_3200.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_xspiboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
new file mode 100644
index 0000000..2ac59b1
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2400_700_3200.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
new file mode 100644
index 0000000..e7c08df
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2500_700_3200.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
new file mode 100644
index 0000000..1e7a8f7
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_2600_700_3200.rcwi>
+#include <configs/lx2160a_8_5_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
new file mode 100644
index 0000000..86f12f8
--- /dev/null
+++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
@@ -0,0 +1,4 @@
+#include <configs/lx2160a_defaults.rcwi>
+#include <configs/lx2160a_test.rcwi>
+#include <configs/lx2160a_17_4_2.rcwi>
+#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
new file mode 100644
index 0000000..76f44bc
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=13
+SRDS_PRTCL_S2=5
+SRDS_PRTCL_S3=2
diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
new file mode 100644
index 0000000..358972d
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
@@ -0,0 +1,7 @@
+SRDS_PRTCL_S1=17
+SRDS_PRTCL_S2=4
+SRDS_PRTCL_S3=2
+
+/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
+/*SRDS_PLL_REF_CLK_SEL_S1=2*/
+
diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
new file mode 100644
index 0000000..8b61021
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=19
+CGA_PLL2_RAT=19
+CGB_PLL1_RAT=19
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=12
+
+MEM_PLL_RAT=26
+MEM2_PLL_RAT=26
+
+/* Modify FlexSPI Clock Divisor value */
+/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
new file mode 100644
index 0000000..6b0b150
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=24
+MEM2_PLL_RAT=24
+
+/* Modify FlexSPI Clock Divisor value */
+/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
new file mode 100644
index 0000000..21dce67
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=26
+MEM2_PLL_RAT=26
+
+/* Modify FlexSPI Clock Divisor value */
+/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
new file mode 100644
index 0000000..e6a8e30
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=29
+MEM2_PLL_RAT=29
+
+/* Modify FlexSPI Clock Divisor value */
+/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
new file mode 100644
index 0000000..27ee377
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_20_5_2.rcwi
new file mode 100644
index 0000000..c2c7bea
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_20_5_2.rcwi
@@ -0,0 +1,7 @@
+SRDS_PRTCL_S1=20
+SRDS_PRTCL_S2=5
+SRDS_PRTCL_S3=2
+
+SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+SRDS_PLL_REF_CLK_SEL_S1=2
+SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
new file mode 100644
index 0000000..fc0fd6c
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=24
+CGA_PLL2_RAT=24
+CGB_PLL1_RAT=24
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
new file mode 100644
index 0000000..62d9069
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=25
+CGA_PLL2_RAT=25
+CGB_PLL1_RAT=25
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
new file mode 100644
index 0000000..e244917
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
@@ -0,0 +1,12 @@
+CGA_PLL1_RAT=26
+CGA_PLL2_RAT=26
+CGB_PLL1_RAT=26
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=14
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
new file mode 100644
index 0000000..62ff153
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
@@ -0,0 +1,7 @@
+SRDS_PRTCL_S1=8 /* should be 8 */
+SRDS_PRTCL_S2=5
+SRDS_PRTCL_S3=0
+
+SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+SRDS_PLL_REF_CLK_SEL_S1=2
+SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_8_5_2.rcwi
new file mode 100644
index 0000000..d7d707a
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_8_5_2.rcwi
@@ -0,0 +1,7 @@
+SRDS_PRTCL_S1=8 /* should be 8 */
+SRDS_PRTCL_S2=5
+SRDS_PRTCL_S3=2
+
+SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+SRDS_PLL_REF_CLK_SEL_S1=2
+SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
new file mode 100644
index 0000000..6fd65ec
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -0,0 +1,19 @@
+#include <../lx2160asi/lx2160a.rcwi>
+MEM_PLL_CFG=3
+MEM2_PLL_CFG=3
+C5_PLL_SEL=0
+C6_PLL_SEL=0
+C7_PLL_SEL=0
+C8_PLL_SEL=0
+HWA_CGA_M1_CLK_SEL=1
+HWA_CGB_M1_CLK_SEL=7
+BOOT_LOC=26
+SYSCLK_FREQ=600
+IIC2_PMUX=6
+IIC3_PMUX=0
+IIC4_PMUX=2
+USB3_CLK_FSEL=39
+SRDS_DIV_PEX_S1=1
+SRDS_DIV_PEX_S2=3
+SRDS_DIV_PEX_S3=1
+
diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
new file mode 100644
index 0000000..d537ea5
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
@@ -0,0 +1,20 @@
+/* Errata to write on scratch reg for validation */
+#include <../lx2160asi/scratchrw1.rcw>
+
+/* Copy SPL Uboot to Ocram */
+.pbi
+blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+.end
+
+/* Boot Location Pointer */
+#include <../lx2160asi/bootlocptr_sd.rcw>
+
+/* Errata for SATA controller */
+#include <../lx2160asi/a010554.rcw>
+
+/* Errata for PCIe controller */
+#include <../lx2160asi/a011270.rcw>
+
+/* common PBI commands */
+#include <../lx2160asi/common.rcw>
+
diff --git a/lx2160acex7/configs/lx2160a_test.rcwi b/lx2160acex7/configs/lx2160a_test.rcwi
new file mode 100644
index 0000000..a223be1
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_test.rcwi
@@ -0,0 +1,20 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=8
+
+SYS_PLL_RAT=12
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
+
+/* Modify FlexSPI Clock Divisor value */
+/* #include <../lx2160asi/flexspi_divisor_24.rcw> */
+
+SRDS_PLL_PD_PLL1=1
+SRDS_PLL_PD_PLL2=1
+SRDS_PLL_PD_PLL3=1
+SRDS_PLL_PD_PLL4=1
+SRDS_PLL_PD_PLL5=1
+SRDS_PLL_PD_PLL6=1
+
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
new file mode 100644
index 0000000..eecc314
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -0,0 +1,17 @@
+/* Errata to write on scratch reg for validation */
+#include <../lx2160asi/scratchrw1.rcw>
+
+/* Boot Location Pointer */
+#include <../lx2160asi/bootlocptr_nor.rcw>
+
+/* Errata for SATA controller */
+#include <../lx2160asi/a010554.rcw>
+
+/* Errata for PCIe controller */
+#include <../lx2160asi/a011270.rcw>
+
+/* common PBI commands */
+#include <../lx2160asi/common.rcw>
+
+/* Modify FlexSPI Clock Divisor value */
+#include <../lx2160asi/flexspi_divisor_24.rcw>
--
2.17.1
patches/rcw-LSDK-21.08/0002-Set-io-pads-as-GPIO.patch 0 → 100644
View file @ a393e2e7
From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 30 Oct 2019 11:43:37 +0200
Subject: [PATCH 2/2] Set io pads as GPIO
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 6fd65ec..dbc843f 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1
HWA_CGB_M1_CLK_SEL=7
BOOT_LOC=26
SYSCLK_FREQ=600
-IIC2_PMUX=6
+IIC2_PMUX=1
IIC3_PMUX=0
IIC4_PMUX=2
USB3_CLK_FSEL=39
SRDS_DIV_PEX_S1=1
SRDS_DIV_PEX_S2=3
SRDS_DIV_PEX_S3=1
-
+SDHC1_DIR_PMUX=1
+IRQ03_00_PMUX=1
+IRQ07_04_PMUX=1
+IRQ11_08_PMUX=1
+EVT20_PMUX=1
+EVT43_PMUX=1
--
2.17.1
patches/rcw-LSDK-21.08/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch 0 → 100644
View file @ a393e2e7
From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 5 Nov 2019 10:35:32 +0200
Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28
Serdes group 2 enable PCIe gen 3
XSPI increase divisor to 28 - this fixes UEFI SPI flash detection.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index dbc843f..3ea7683 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -14,7 +14,7 @@ IIC3_PMUX=0
IIC4_PMUX=2
USB3_CLK_FSEL=39
SRDS_DIV_PEX_S1=1
-SRDS_DIV_PEX_S2=3
+SRDS_DIV_PEX_S2=1
SRDS_DIV_PEX_S3=1
SDHC1_DIR_PMUX=1
IRQ03_00_PMUX=1
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index eecc314..28310c9 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -14,4 +14,4 @@
#include <../lx2160asi/common.rcw>
/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_24.rcw>
+#include <../lx2160asi/flexspi_divisor_28.rcw>
--
2.17.1
patches/rcw-LSDK-21.08/0004-refactor-a009531-a008851-and-a011270.patch 0 → 100644
View file @ a393e2e7
From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:16:13 +0200
Subject: [PATCH 4/4] refactor a009531, a008851 and a011270
1. Add 'load conditional', 'jump condidional' and 'jump' to PBI
instructions.
2. Use SVR register to execute the PCIe workarounds on the relevant rev
of the device.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++
lx2160asi/a011270.rcw | 6 +++
rcw.py | 28 ++++++++++
3 files changed, 130 insertions(+)
create mode 100644 lx2160asi/a009531_a008851.rcw
diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw
new file mode 100644
index 0000000..0eb7051
--- /dev/null
+++ b/lx2160asi/a009531_a008851.rcw
@@ -0,0 +1,96 @@
+/*
+ * Work-around for erratum A-009531
+ *
+ * Description:
+ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO)
+ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer
+ * is permitted to set IDO only if the IDO Completion Enable bit in the Device
+ * Control 2 Register is set. It is not required to copy the value of IDO from
+ * the Request into the Completion(s) for that Request".
+ *
+ * However, the PCI Express controller as the completer sets the IDO bit in the
+ * completion packet header, in response to non-posted requests (memory read) with
+ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the
+ * Device Control 2 Register is not set.
+ *
+ * Impact:
+ * The PCI Express controller as the completer sends completion packets with IDO
+ * bit set in packet header even when the IDO Completion Enable bit is cleared in
+ * the controller’s Device Control 2 Register.
+ * Applicable for SNP PCIe controller
+ */
+
+/*
+ * Work-around for erratum A-008851
+ *
+ * Invalid transmitter/receiver preset values are used in Gen3 equalization
+ * phases during link training for RC mode
+ * This errata is valid only for PCI gen3.
+ * Workaround:
+ * write 0x00000001 to MISC_CONTROL_1_OFF
+ * write 0x4747 to Lane Equalization Control register for each lane
+ * Applicable for SNP PCIe controller
+ */
+
+.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+
+/* If it is rev 2, skip the following jump command */
+jumpc 0x00000014,0x00000020
+
+/* Jump all the below instructions */
+jump 0x190 /* All instruction below including the jump are 0x190 bytes */
+
+loadc 0x01ea1080,0x70000000
+jumpc 0x00000034,0x00000000
+write 0x03400098,0x00000000
+write 0x034008bc,0x00000001
+write 0x03400154,0x47474747
+write 0x03400158,0x47474747
+write 0x034008bc,0x00000000
+
+loadc 0x01ea1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03500098,0x00000000
+write 0x035008bc,0x00000001
+write 0x03500154,0x47474747
+write 0x03500158,0x47474747
+write 0x035008bc,0x00000000
+
+loadc 0x01eb1080,0x70000000
+jumpc 0x00000044,0x00000000
+write 0x03600098,0x00000000
+write 0x036008bc,0x00000001
+write 0x03600164,0x47474747
+write 0x03600168,0x47474747
+write 0x0360016c,0x47474747
+write 0x03600170,0x47474747
+write 0x036008bc,0x00000000
+
+loadc 0x01eb1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03700098,0x00000000
+write 0x037008bc,0x00000001
+write 0x03700154,0x47474747
+write 0x03700158,0x47474747
+write 0x037008bc,0x00000000
+
+loadc 0x01ec1080,0x70000000
+jumpc 0x00000044,0x00000000
+write 0x03800098,0x00000000
+write 0x038008bc,0x00000001
+write 0x03800164,0x47474747
+write 0x03800168,0x47474747
+write 0x0380016c,0x47474747
+write 0x03800170,0x47474747
+write 0x038008bc,0x00000000
+
+loadc 0x01ec1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03900098,0x00000000
+write 0x039008bc,0x00000001
+write 0x03900154,0x47474747
+write 0x03900158,0x47474747
+write 0x039008bc,0x00000000
+.end
diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw
index 0dc774d..5bd5558 100644
--- a/lx2160asi/a011270.rcw
+++ b/lx2160asi/a011270.rcw
@@ -4,6 +4,12 @@
*/
.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+/* If it is rev 1, skip the following jump command */
+jumpc 0x00000014,0x00000010
+/* Skip the following instructions by jumping to the end */
+jump 0x38
write 0x03400688,0x00000001
write 0x03500688,0x00000001
write 0x03600688,0x00000001
diff --git a/rcw.py b/rcw.py
index 863f755..c2d06f6 100755
--- a/rcw.py
+++ b/rcw.py
@@ -328,6 +328,34 @@ def build_pbi(lines):
v2 = struct.pack(endianess + 'L', p2)
subsection += v1
subsection += v2
+ elif op == 'loadc':
+ if p1 == None or p2 == None:
+ print('Error: "loadc" instruction requires two parameters')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80140000)
+ v2 = struct.pack(endianess + 'L', p1)
+ v3 = struct.pack(endianess + 'L', p2)
+ subsection += v1
+ subsection += v2
+ subsection += v3
+ elif op == 'jumpc':
+ if p1 == None or p2 == None:
+ print('Error: "jumpc" instruction requires two parameters')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80850000)
+ v2 = struct.pack(endianess + 'L', p1)
+ v3 = struct.pack(endianess + 'L', p2)
+ subsection += v1
+ subsection += v2
+ subsection += v3
+ elif op == 'jump':
+ if p1 == None:
+ print('Error: "jump" instruction requires a parameter')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80840000)
+ v2 = struct.pack(endianess + 'L', p1)
+ subsection += v1
+ subsection += v2
elif op == 'awrite':
if p1 == None or p2 == None:
print('Error: "awrite" instruction requires two parameters')
--
2.17.1
patches/rcw-LSDK-21.08/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch 0 → 100644
View file @ a393e2e7
From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:35:04 +0200
Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160asi/a050234.rcw | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw
index 72a40e4..2130709 100644
--- a/lx2160asi/a050234.rcw
+++ b/lx2160asi/a050234.rcw
@@ -4,6 +4,12 @@
*/
.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+/* If it is rev 1, skip the following jump command */
+jumpc 0x00000014,0x00000010
+/* Skip the following instructions by jumping to the end */
+jump 0xc8
write 0x1ea1200,0x20081004
write 0x1ea1240,0x20081004
write 0x1ea1280,0x20081004
--
2.17.1
patches/rcw-LSDK-21.08/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch 0 → 100644
View file @ a393e2e7
From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:36:20 +0200
Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed
1. Moves calling the workarounds to the _defaults.rcwi
2. Toggle fan-full-speed GPIO. The fan controller starts throttling when
a driver exists (i.e. kernel); in order to avoid overheating until then
enable full speed.
3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox
ConnectX-5 NICs
4. Run a009531 and a00885 on rev2.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++----
lx2160acex7/configs/lx2160a_sdboot.rcwi | 6 ------
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 6 ------
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 3ea7683..7af1f5b 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -1,10 +1,6 @@
#include <../lx2160asi/lx2160a.rcwi>
MEM_PLL_CFG=3
MEM2_PLL_CFG=3
-C5_PLL_SEL=0
-C6_PLL_SEL=0
-C7_PLL_SEL=0
-C8_PLL_SEL=0
HWA_CGA_M1_CLK_SEL=1
HWA_CGB_M1_CLK_SEL=7
BOOT_LOC=26
@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1
IRQ11_08_PMUX=1
EVT20_PMUX=1
EVT43_PMUX=1
+
+/* Drive the fan full speed pin */
+.pbi
+write 0x2320000,0x20000000
+.end
+
+/* Errata for SATA controller */
+#include <../lx2160asi/a010554.rcw>
+
+/* Errata for rev 1 PCIe controller */
+#include <../lx2160asi/a011270.rcw>
+
+/* Errata a050234 - fix elastic buffer threshold in rev 1 */
+#include <../lx2160asi/a050234.rcw>
+
+/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
+#include <../lx2160asi/a009531_a008851.rcw>
diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
index d537ea5..9086ffc 100644
--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000
/* Boot Location Pointer */
#include <../lx2160asi/bootlocptr_sd.rcw>
-/* Errata for SATA controller */
-#include <../lx2160asi/a010554.rcw>
-
-/* Errata for PCIe controller */
-#include <../lx2160asi/a011270.rcw>
-
/* common PBI commands */
#include <../lx2160asi/common.rcw>
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index 28310c9..fa092c9 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -4,12 +4,6 @@
/* Boot Location Pointer */
#include <../lx2160asi/bootlocptr_nor.rcw>
-/* Errata for SATA controller */
-#include <../lx2160asi/a010554.rcw>
-
-/* Errata for PCIe controller */
-#include <../lx2160asi/a011270.rcw>
-
/* common PBI commands */
#include <../lx2160asi/common.rcw>
--
2.17.1
patches/rcw-LSDK-21.08/0008-lx2160a-add-generic-bootloc-section.patch 0 → 100644
View file @ a393e2e7
From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 24 Mar 2020 03:42:14 +0200
Subject: [PATCH 8/8] lx2160a: add generic bootloc section
The generic bootloc section does conditional blockcopy from SD/eMMC and
SPI with some predefined addresses.
Later on if ATF is used; those addresses are modified with ATF's
create_pbl.c
With this method a single boot image is unified for all the 3 different
boot methods.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++
lx2160asi/bootlocptr.rcw | 62 +++++++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100644 lx2160asi/bootlocptr.rcw
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 7af1f5b..7997d49 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -35,3 +35,15 @@ write 0x2320000,0x20000000
/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
#include <../lx2160asi/a009531_a008851.rcw>
+
+/* Unified boot location copy */
+#include <../lx2160asi/bootlocptr.rcw>
+
+/* Errata to write on scratch reg for validation */
+#include <../lx2160asi/scratchrw1.rcw>
+
+/* common PBI commands */
+#include <../lx2160asi/common.rcw>
+
+/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw
new file mode 100644
index 0000000..645182f
--- /dev/null
+++ b/lx2160asi/bootlocptr.rcw
@@ -0,0 +1,62 @@
+/*
+ * Generic code for auto booting.
+ * For each section blockcopy followed by write to bootlocl then bootloch must
+ * be followed in each section since when using ATF with create_pbl script in
+ * auto mode; it counts on the sequence of to be in that order.
+ */
+
+/* Boot from SD - copy SPL Uboot to Ocram */
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0x8 << 23 then skip the following jump command */
+jumpc 0x00000014,0x04000000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 40 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x1800a000
+write 0x01e00404,0x00000000
+.end
+
+/* Boot from eMMC - copy SPL Uboot to Ocram */
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0x9 << 23 then skip the following jump command */
+jumpc 0x00000014,0x04800000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 40 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x09,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x1800a000
+write 0x01e00404,0x00000000
+.end
+
+/* XSPI boot Location Pointer */
+/*
+ * Set the boot location pointer to the NOR flash boot area.
+ */
+
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0xf << 23 then skip the following jump command */
+jumpc 0x00000014,0x07800000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 0x190 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x0f,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x20100000
+write 0x01e00404,0x00000000
+.end
+
--
2.17.1
patches/rcw-LSDK-21.08/0009-lx2160acex7-remove-all-predefined-RCW-files.patch 0 → 100644
View file @ a393e2e7
From 151f650f383fc5ddd9c405cf96bc189c2eaf13bd Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 24 Mar 2020 03:51:28 +0200
Subject: [PATCH 9/9] lx2160acex7: remove all predefined RCW files
Remove all predefined RCW files and use on-the-fly created RCW from
external script.
For instance when using lx2160a_build repo; the runme.sh file creates
lx2160acex7/RCW/template.rcw file the gets compiled.
The creation is done using a simple bash script -
cd $ROOTDIR/build/rcw/lx2160acex7
mkdir -p RCW
echo "#include <configs/lx2160a_defaults.rcwi>" > RCW/template.rcw
echo "#include <configs/lx2160a_${SPEED}.rcwi>" >> RCW/template.rcw
echo "#include <configs/lx2160a_${SERDES}.rcwi>" >> RCW/template.rcw
make clean
make -j${PARALLEL}
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 -------------------
.../rcw_1900_600_2600_17_4_2.rcw | 4 --
.../rcw_1900_600_2600_17_4_2_sd.rcw | 4 --
.../rcw_2000_700_2400_13_5_2_sd.rcw | 4 --
.../rcw_2000_700_2400_20_5_2_sd.rcw | 4 --
.../rcw_2000_700_2400_8_5_2_sd.rcw | 4 --
.../rcw_2000_700_2600_8_5_2_sd.rcw | 4 --
.../rcw_2000_700_2900_17_4_2_sd.rcw | 4 --
.../rcw_2000_700_2900_8_5_2_sd.rcw | 4 --
.../rcw_2000_700_3200_17_4_2_sd.rcw | 4 --
.../rcw_2000_700_3200_20_5_2_sd.rcw | 4 --
.../rcw_2000_700_3200_8_5_0_sd.rcw | 4 --
.../rcw_2000_700_3200_8_5_2_sd.rcw | 4 --
.../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 --
.../rcw_2400_700_3200_8_5_2_sd.rcw | 4 --
.../rcw_2500_700_3200_8_5_2_sd.rcw | 4 --
.../rcw_2600_700_3200_8_5_2_sd.rcw | 4 --
.../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 --
18 files changed, 129 deletions(-)
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
deleted file mode 100644
index cdb6446..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * SerDes Protocol 1 - 19
- * SerDes Protocol 2 - 5
- * SerDes Protocol 3 - 2
- *
- * Frequencies:
- * Core -- 1900 MHz
- * Platform -- 600 MHz
- * DDR -- 2600 MT/s
- */
-
-#include <../lx2160asi/lx2160a.rcwi>
-
-SYS_PLL_RAT=12
-MEM_PLL_CFG=3
-MEM_PLL_RAT=26
-MEM2_PLL_CFG=3
-MEM2_PLL_RAT=26
-CGA_PLL1_RAT=19
-CGA_PLL2_RAT=19
-CGB_PLL1_RAT=19
-CGB_PLL2_RAT=9
-C5_PLL_SEL=0
-C6_PLL_SEL=0
-C7_PLL_SEL=0
-C8_PLL_SEL=0
-HWA_CGA_M1_CLK_SEL=1
-HWA_CGB_M1_CLK_SEL=7
-BOOT_LOC=26
-SYSCLK_FREQ=600
-IIC2_PMUX=6
-IIC3_PMUX=2
-IIC4_PMUX=2
-USB3_CLK_FSEL=39
-SRDS_PRTCL_S1=19
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
-SRDS_PLL_REF_CLK_SEL_S1=2
-SRDS_DIV_PEX_S1=1
-SRDS_DIV_PEX_S2=3
-SRDS_DIV_PEX_S3=1
-
-/* Errata to write on scratch reg for validation */
-#include <../lx2160asi/scratchrw1.rcw>
-
-/* Copy SPL Uboot to Ocram */
-.pbi
-blockcopy 0x08,0x00100000,0x1800a000,0x00020000
-.end
-
-/* Boot Location Pointer */
-#include <../lx2160asi/bootlocptr_sd.rcw>
-
-/* Errata for SATA controller */
-#include <../lx2160asi/a010554.rcw>
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_24.rcw>
-
-/* common PBI commands */
-#include <../lx2160asi/common.rcw>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
deleted file mode 100644
index 13ab0b9..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_1900_600_2600.rcwi>
-#include <configs/lx2160a_17_4_2.rcwi>
-#include <configs/lx2160a_xspiboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
deleted file mode 100644
index 14fae8c..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_1900_600_2600.rcwi>
-#include <configs/lx2160a_17_4_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
deleted file mode 100644
index 2dae5a2..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2400.rcwi>
-#include <configs/lx2160a_13_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
deleted file mode 100644
index 5335072..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2400.rcwi>
-#include <configs/lx2160a_20_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
deleted file mode 100644
index e2a5bd3..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2400.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
deleted file mode 100644
index a330bfe..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2600.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
deleted file mode 100644
index 8535dbd..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2900.rcwi>
-#include <configs/lx2160a_17_4_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
deleted file mode 100644
index 698be01..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_2900.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
deleted file mode 100644
index 780d8c3..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_3200.rcwi>
-#include <configs/lx2160a_17_4_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
deleted file mode 100644
index eb9d240..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_3200.rcwi>
-#include <configs/lx2160a_20_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
deleted file mode 100644
index ceb53a3..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_3200.rcwi>
-#include <configs/lx2160a_8_5_0.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
deleted file mode 100644
index a220e98..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_3200.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
deleted file mode 100644
index 1eabd7d..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2000_700_3200.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_xspiboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
deleted file mode 100644
index 2ac59b1..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2400_700_3200.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
deleted file mode 100644
index e7c08df..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2500_700_3200.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
deleted file mode 100644
index 1e7a8f7..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_2600_700_3200.rcwi>
-#include <configs/lx2160a_8_5_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
deleted file mode 100644
index 86f12f8..0000000
--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <configs/lx2160a_defaults.rcwi>
-#include <configs/lx2160a_test.rcwi>
-#include <configs/lx2160a_17_4_2.rcwi>
-#include <configs/lx2160a_sdboot.rcwi>
--
2.17.1
patches/rcw-LSDK-21.08/0010-lx2160acex7-remove-flexspi-divisor-optimization.patch 0 → 100644
View file @ a393e2e7
From 4f1f779e2d0757ab1d328761c06dc09b9c6a3544 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 1 Sep 2020 12:39:31 +0300
Subject: [PATCH 10/10] lx2160acex7: remove flexspi divisor optimization
Keep the flexspi divisor as default; which is 17MHz when the fabric at
700MHz.
The HoneyComb / ClearFog CX carrier boards holds an SPI flash that it's
MUX is limited to 20MHz.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_1900_600_2600.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2400.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2600.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_2900.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2000_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2400_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2500_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_2600_700_3200.rcwi | 3 ---
lx2160acex7/configs/lx2160a_defaults.rcwi | 10 ++++++++--
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 3 ---
10 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
index 8b61021..a3b7b29 100644
--- a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=12
MEM_PLL_RAT=26
MEM2_PLL_RAT=26
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
index 6b0b150..4cb3abf 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=24
MEM2_PLL_RAT=24
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
index 21dce67..a5c436c 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=26
MEM2_PLL_RAT=26
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
index e6a8e30..d1db3fb 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=29
MEM2_PLL_RAT=29
-
-/* Modify FlexSPI Clock Divisor value */
-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
index 27ee377..22fcadf 100644
--- a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
index fc0fd6c..8f74ff0 100644
--- a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
index 62d9069..2dc1460 100644
--- a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
index e244917..d9fd795 100644
--- a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
MEM_PLL_RAT=32
MEM2_PLL_RAT=32
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 7997d49..359e86c 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -45,5 +45,11 @@ write 0x2320000,0x20000000
/* common PBI commands */
#include <../lx2160asi/common.rcw>
-/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
+/*
+ * Do not modify the FlexSPI clock divisor value when using HoneyComb / ClearFog CX
+ * as carrier boards. The reason is that the analog mux used on the carrier board
+ * can't accomodate more than 20MHz SPI frequency. So keep the value default 0x14
+ * which indicates divide by 80. In 700MHz fabric clock this is around 17MHz SPI
+ * clock.
+ */
+/*#include <../lx2160asi/flexspi_divisor_28.rcw>*/
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index fa092c9..21782ec 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -6,6 +6,3 @@
/* common PBI commands */
#include <../lx2160asi/common.rcw>
-
-/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_28.rcw>
--
2.17.1
patches/rcw-LSDK-21.08/0011-lx210acex7-25Gbps-retimer-and-restructure-config.patch 0 → 100644
View file @ a393e2e7
From d4a721d712d8fd9f03be2965e0b37bcd33148bdc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 16:44:35 +0200
Subject: [PATCH] lx210acex7: 25Gbps retimer and restructure config
1. Split SERDES configuration files that each SERDES block from the
available 3 can be separately configured.
2. Added SD1 lanes e,f,g,h include files that configures the SERDES
lanes to suppoer 25Gbps rate with external retimer (using ClearFog CX
revision 1.3 and newer).
3. Added bus speeds 750 and 800MHz which are required to get wire speed
DPDK performance on a 100Gbps link.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_13_5_2.rcwi | 3 ---
lx2160acex7/configs/lx2160a_17_4_2.rcwi | 7 ------
.../configs/lx2160a_2000_750_3200.rcwi | 9 +++++++
.../configs/lx2160a_2000_800_3200.rcwi | 9 +++++++
lx2160acex7/configs/lx2160a_8_5_0.rcwi | 7 ------
lx2160acex7/configs/lx2160a_SD1_13.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_14.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_17.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_2.rcwi | 4 +++
...x2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} | 2 --
...{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} | 3 ---
lx2160acex7/configs/lx2160a_SD2_5.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_0.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_2.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_3.rcwi | 1 +
.../lx2160a_cex7_hc_sd1_lanes_e_f.rcwi | 24 ++++++++++++++++++
.../lx2160a_cex7_hc_sd1_lanes_g_h.rcwi | 25 +++++++++++++++++++
17 files changed, 84 insertions(+), 22 deletions(-)
delete mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
delete mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
delete mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_13.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_14.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_17.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_2.rcwi
rename lx2160acex7/configs/{lx2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} (78%)
rename lx2160acex7/configs/{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} (79%)
create mode 100644 lx2160acex7/configs/lx2160a_SD2_5.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_3.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
deleted file mode 100644
index 76f44bc..0000000
--- a/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+++ /dev/null
@@ -1,3 +0,0 @@
-SRDS_PRTCL_S1=13
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
deleted file mode 100644
index 358972d..0000000
--- a/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+++ /dev/null
@@ -1,7 +0,0 @@
-SRDS_PRTCL_S1=17
-SRDS_PRTCL_S2=4
-SRDS_PRTCL_S3=2
-
-/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
-/*SRDS_PLL_REF_CLK_SEL_S1=2*/
-
diff --git a/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
new file mode 100644
index 0000000..84d544d
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
@@ -0,0 +1,9 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=15
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
diff --git a/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
new file mode 100644
index 0000000..31d7cfd
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
@@ -0,0 +1,9 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=16
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
deleted file mode 100644
index 62ff153..0000000
--- a/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+++ /dev/null
@@ -1,7 +0,0 @@
-SRDS_PRTCL_S1=8 /* should be 8 */
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=0
-
-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
-SRDS_PLL_REF_CLK_SEL_S1=2
-SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_SD1_13.rcwi b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
new file mode 100644
index 0000000..61b1eea
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=13
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_14.rcwi b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
new file mode 100644
index 0000000..75e3fab
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=14
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_17.rcwi b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
new file mode 100644
index 0000000..5504271
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=17
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
new file mode 100644
index 0000000..0f013e6
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
@@ -0,0 +1,4 @@
+SRDS_PRTCL_S1=2
+
+SRDS_PLL_REF_CLK_SEL_S1=0
+SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
similarity index 78%
rename from lx2160acex7/configs/lx2160a_20_5_2.rcwi
rename to lx2160acex7/configs/lx2160a_SD1_20.rcwi
index c2c7bea..053aee7 100644
--- a/lx2160acex7/configs/lx2160a_20_5_2.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
@@ -1,6 +1,4 @@
SRDS_PRTCL_S1=20
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
similarity index 79%
rename from lx2160acex7/configs/lx2160a_8_5_2.rcwi
rename to lx2160acex7/configs/lx2160a_SD1_8.rcwi
index d7d707a..abd6dfd 100644
--- a/lx2160acex7/configs/lx2160a_8_5_2.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
@@ -1,7 +1,4 @@
SRDS_PRTCL_S1=8 /* should be 8 */
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
-
SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
SRDS_PLL_REF_CLK_SEL_S1=2
SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_SD2_5.rcwi b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
new file mode 100644
index 0000000..559a90c
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S2=5
diff --git a/lx2160acex7/configs/lx2160a_SD3_0.rcwi b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
new file mode 100644
index 0000000..1904856
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=0
diff --git a/lx2160acex7/configs/lx2160a_SD3_2.rcwi b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
new file mode 100644
index 0000000..b9c3e6f
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=2
diff --git a/lx2160acex7/configs/lx2160a_SD3_3.rcwi b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
new file mode 100644
index 0000000..4695755
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=3
diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
new file mode 100644
index 0000000..d870a4b
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
@@ -0,0 +1,24 @@
+/*
+ * SERDES tuning based on the following hardware -
+ * - SolidRun COM express type 7 revision 1.7 and newer
+ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
+ */
+
+.pbi
+/* Lane E (SD1 TX/RX 3) */
+write 0x01EA0C28,0x00000000
+write 0x01EA0C30,0x20868120
+write 0x01EA0C34,0x23000000
+write 0x01EA0C68,0x80000000
+write 0x01EA0C74,0x00002020
+write 0x01EA0C80,0x00008000
+
+/* Lane F (SD1 TX/RX 2)*/
+write 0x01EA0D28,0x00000000
+write 0x01EA0D30,0x20868120
+write 0x01EA0D34,0x23000000
+write 0x01EA0D68,0x80000000
+write 0x01EA0D74,0x00002020
+write 0x01EA0D80,0x00008000
+.end
+
diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
new file mode 100644
index 0000000..4097b77
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
@@ -0,0 +1,25 @@
+/*
+ * SERDES tuning based on the following hardware -
+ * - SolidRun COM express type 7 revision 1.7 and newer
+ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
+ */
+
+.pbi
+/* Lane G (SD1 TX/RX 1)*/
+write 0x01EA0E28,0x00000000
+write 0x01EA0E30,0x20818120
+write 0x01EA0E34,0x23000000
+write 0x01EA0E68,0x80000000
+write 0x01EA0E74,0x00002020
+write 0x01EA0E80,0x00008000
+
+/* Lane H (SD1 TX/RX 0)*/
+write 0x01EA0F28,0x00000000
+write 0x01EA0F30,0x20818120
+write 0x01EA0F34,0x23000000
+write 0x01EA0F68,0x80000000
+write 0x01EA0F74,0x00002020
+write 0x01EA0F80,0x00008000
+
+.end
+
--
2.25.1
patches/rcw-LSDK-21.08/0012-lx2160acex7-adjust-lanes-e-and-f-for-25g-links.patch 0 → 100644
View file @ a393e2e7
From 08fedde7e5422756a898dd389250aa1a30c97c7d Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Thu, 29 Oct 2020 17:42:50 +0200
Subject: [PATCH] lx2160acex7: adjust lanes e and f for 25g links
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
index d870a4b..bd35bdc 100644
--- a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
@@ -7,7 +7,7 @@
.pbi
/* Lane E (SD1 TX/RX 3) */
write 0x01EA0C28,0x00000000
-write 0x01EA0C30,0x20868120
+write 0x01EA0C30,0x20818120
write 0x01EA0C34,0x23000000
write 0x01EA0C68,0x80000000
write 0x01EA0C74,0x00002020
@@ -15,7 +15,7 @@ write 0x01EA0C80,0x00008000
/* Lane F (SD1 TX/RX 2)*/
write 0x01EA0D28,0x00000000
-write 0x01EA0D30,0x20868120
+write 0x01EA0D30,0x20818120
write 0x01EA0D34,0x23000000
write 0x01EA0D68,0x80000000
write 0x01EA0D74,0x00002020
--
2.25.1
patches/rcw-LSDK-21.08/0013-lx2160acex7-added-SERDES-bank-2-with-pcie-x8.patch 0 → 100644
View file @ a393e2e7
From 30614556e914de366769e6d1bd235d9caa3c6528 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 3 Nov 2020 15:34:34 +0200
Subject: [PATCH] lx2160acex7: added SERDES bank 2 with pcie x8
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD2_2.rcwi | 1 +
1 file changed, 1 insertion(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD2_2.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD2_2.rcwi b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
new file mode 100644
index 0000000..daeeb5e
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S2=2
--
2.25.1
patches/rcw-LSDK-21.08/0014-lx2160acex7-set-correctly-sdcard-card-detect-and-wri.patch 0 → 100644
View file @ a393e2e7
From ec8c382532d01a3e26491dbcfe2ad854a164006f Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Thu, 3 Dec 2020 19:55:07 +0200
Subject: [PATCH] lx2160acex7: set correctly sdcard card detect and write
protect pmux
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 359e86c..30e0399 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -5,7 +5,7 @@ HWA_CGA_M1_CLK_SEL=1
HWA_CGB_M1_CLK_SEL=7
BOOT_LOC=26
SYSCLK_FREQ=600
-IIC2_PMUX=1
+IIC2_PMUX=6
IIC3_PMUX=0
IIC4_PMUX=2
USB3_CLK_FSEL=39
--
2.25.1
patches/rcw-LSDK-21.08/0015-lx2160acex7-more-SERDES-prototocol-configurations.patch 0 → 100644
View file @ a393e2e7
From 04ac1bae27bc5eafc588431bc9e268e655f5bb38 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 14 Jun 2021 08:30:53 +0300
Subject: [PATCH] lx2160acex7: more SERDES prototocol configurations
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_0.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_7.rcwi | 6 ++++++
lx2160acex7/configs/lx2160a_SD2_0.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD2_9.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_0.rcwi | 2 ++
5 files changed, 15 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_7.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD2_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD2_9.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_0.rcwi b/lx2160acex7/configs/lx2160a_SD1_0.rcwi
new file mode 100644
index 0000000..8a2dd84
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_0.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=0
+SRDS_PLL_PD_PLL1=1
+SRDS_PLL_PD_PLL2=1
diff --git a/lx2160acex7/configs/lx2160a_SD1_7.rcwi b/lx2160acex7/configs/lx2160a_SD1_7.rcwi
new file mode 100644
index 0000000..73a8115
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_7.rcwi
@@ -0,0 +1,6 @@
+/*
+ * Notice that this requires swapping PLLF and PLLS on the PCB.
+ */
+
+SRDS_PRTCL_S1=7
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_SD2_0.rcwi b/lx2160acex7/configs/lx2160a_SD2_0.rcwi
new file mode 100644
index 0000000..a1215d2
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_0.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S2=0
+SRDS_PLL_PD_PLL3=1
+SRDS_PLL_PD_PLL4=1
diff --git a/lx2160acex7/configs/lx2160a_SD2_9.rcwi b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
new file mode 100644
index 0000000..c3e03a5
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S2=9
diff --git a/lx2160acex7/configs/lx2160a_SD3_0.rcwi b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
index 1904856..0ff505d 100644
--- a/lx2160acex7/configs/lx2160a_SD3_0.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
@@ -1 +1,3 @@
SRDS_PRTCL_S3=0
+SRDS_PLL_PD_PLL5=1
+SRDS_PLL_PD_PLL6=1
--
2.25.1
patches/rcw-LSDK-21.08/0016-lx2162-som-add-customization-for-this-sku.patch 0 → 100644
View file @ a393e2e7
From a6db2cc5af8ff2353c4821402d5a9c3ee1263bef Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Nov 2021 15:12:16 +0200
Subject: [PATCH 16/16] lx2162-som: add customization for this sku
LX2162A has the following disabled -
1. PCIe 2,5,6
2. Second USB controller
3. MAC7 to MAC10
4. Second DDR controller
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 30e0399..e22fbef 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -53,3 +53,20 @@ write 0x2320000,0x20000000
* clock.
*/
/*#include <../lx2160asi/flexspi_divisor_28.rcw>*/
+
+.pbi
+/* Load condition SVR register and mask LX2162A 23x23 package */
+loadc 0x01e000a4, 0x00000800
+/* If LX2160A jump forward */
+jumpc 0x14, 0x00000800
+jump 0x28
+/* Following is LX2162A specific code */
+/* Disable clock of PEX2, PEX5 and PEX6 by using DEVDISR register */
+write 0x1e00078,0x00000032
+/* Disabled second USB controller */
+write 0x1e00070,0x00002000
+/* MAC7 to MAC10 clock disable*/
+write 0x1e00074,0x00007c0
+/* Disable second DDR controller */
+write 0x1e00080,0x00000002
+.end
--
2.25.1
patches/rcw-LSDK-21.08/9999-lx2160acex7-add-SD1-mode-4-serdes-configuration.patch 0 → 100644
View file @ a393e2e7
From 2ae3b51f85375e32b818cb64fbe42750d1d6254f Mon Sep 17 00:00:00 2001
From: Russell King <rmk@armlinux.org.uk>
Date: Thu, 23 Jan 2020 15:53:30 +0000
Subject: [PATCH] lx2160acex7: add SD1 mode 4 serdes configuration
Add mode 4 serdes configuration for SGMII and 1000BASE-X on serdes 1.
Signed-off-by: Russell King <rmk@armlinux.org.uk>
---
lx2160acex7/configs/lx2160a_SD1_4.rcwi | 4 ++++
1 file changed, 4 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_4.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_4.rcwi b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
new file mode 100644
index 000000000000..ec8ca959b59b
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
@@ -0,0 +1,4 @@
+SRDS_PRTCL_S1=4
+/* SRDS_INTRA_REF_CLK_S1 = 1 PLLF used for PLLS */
+SRDS_PLL_REF_CLK_SEL_S1=0
+SRDS_PLL_PD_PLL1=1
--
2.20.1
patches/u-boot-LSDK-21.08/0001-armv8-add-lx2160acex7-build-inclusion.patch 0 → 100644
View file @ a393e2e7
From fbee75687141952103530e0b68aee00415e47fbf Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 5 Sep 2021 19:00:09 +0300
Subject: [PATCH] armv8: add lx2160acex7 build inclusion
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/Kconfig | 13 +++++++++++++
arch/arm/cpu/armv8/Kconfig | 1 +
arch/arm/dts/Makefile | 3 ++-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6db6561824..6f5a131ee7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1333,6 +1333,18 @@ config TARGET_LX2162AQDS
Support for NXP LX2162AQDS platform.
The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
+config TARGET_LX2160ACEX7
+ bool "Support lx2160acex7"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ help
+ Support for SolidRun LX2160A based com express type 7 module and
+ platform. The lx2160acex7 high-performance platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
@@ -2007,6 +2019,7 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
+source "board/solidrun/lx2160a/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9cd6a8d642..6477f948cc 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -116,6 +116,7 @@ config PSCI_RESET
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
+ !TARGET_LX2160ACEX7 && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7304facd7e..3559b5e0ee 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -424,7 +424,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2162a-qds.dtb\
fsl-lx2162a-qds-17-x.dtb\
fsl-lx2162a-qds-18-x.dtb\
- fsl-lx2162a-qds-20-x.dtb
+ fsl-lx2162a-qds-20-x.dtb\
+ fsl-lx2160a-cex7.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
--
2.25.1
patches/u-boot-LSDK-21.08/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch 0 → 100644
View file @ a393e2e7
From 62af256d25d61136913a739b14452b6d35eff3dc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:29:31 +0300
Subject: [PATCH 3/6] armv8: lx2160acex7: defconfig and main platform include
This patch add lx2160acex7 main defconfig and main include file.
Notice that the defconfig doesn't support the secured boot mode where a
follow up patch will cover this.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++
include/configs/lx2160acex7.h | 85 +++++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 configs/lx2160acex7_tfa_defconfig
create mode 100644 include/configs/lx2160acex7.h
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
new file mode 100644
index 0000000000..d59de7d054
--- /dev/null
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ACEX7=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_EMC2301=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MICRON=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT2=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_E1000=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+# CONFIG_SYS_NXP_FSPI_AHB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
new file mode 100644
index 0000000000..478cd8242f
--- /dev/null
+++ b/include/configs/lx2160acex7.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#ifndef __LX2_CEX7_H
+#define __LX2_CEX7_H
+
+#include "lx2160a_common.h"
+
+/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0x2
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x5c
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160acex7_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 700
+#define VDD_MV_MAX 855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
+
+#define RGMII_PHY_ADDR1 0x01
+
+#endif
+
+/* EMC2301 */
+#define I2C_MUX_CH_EMC2301 0x01
+#define I2C_EMC2301_ADDR 0x2f
+#define I2C_EMC2301_CMD 0x40
+#define I2C_EMC2301_PWM 0x80
+
+/* EEPROM */
+#undef CONFIG_ID_EEPROM /* Fixme */
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160acex7_vdd_mv=800\0" \
+ "BOARD=lx2160acex7\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_CEX7_H */
--
2.17.1
patches/u-boot-LSDK-21.08/0004-armv8-lx2160acex7-common-files-for-platform-support.patch 0 → 100644
View file @ a393e2e7
From 7aae154166d92aa59c8b097b4dd076d969e0e12b Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 12 Jan 2021 11:51:37 +0200
Subject: [PATCH 4/4] armv8: lx2160acex7: common files for platform support
The patch copies and modifies NXP's common platform resources that adds
support to the following -
1. Secureboot
2. Analog devices DC-DC controller
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/common/Makefile | 5 +
board/solidrun/common/cmd_esbc_validate.c | 85 ++
board/solidrun/common/fsl_chain_of_trust.c | 164 ++++
board/solidrun/common/fsl_validate.c | 962 +++++++++++++++++++++
board/solidrun/common/vid.c | 330 +++++++
board/solidrun/common/vid.h | 23 +
6 files changed, 1571 insertions(+)
create mode 100644 board/solidrun/common/cmd_esbc_validate.c
create mode 100644 board/solidrun/common/fsl_chain_of_trust.c
create mode 100644 board/solidrun/common/fsl_validate.c
create mode 100644 board/solidrun/common/vid.c
create mode 100644 board/solidrun/common/vid.h
diff --git a/board/solidrun/common/Makefile b/board/solidrun/common/Makefile
index a72ac1b7b9..77b0d798da 100644
--- a/board/solidrun/common/Makefile
+++ b/board/solidrun/common/Makefile
@@ -3,3 +3,8 @@
# Copyright (C) SolidRun
obj-$(CONFIG_TARGET_CLEARFOG) += tlv_data.o
+obj-$(CONFIG_VID) += vid.o
+ifdef CONFIG_SECURE_BOOT
+obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
+endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
diff --git a/board/solidrun/common/cmd_esbc_validate.c b/board/solidrun/common/cmd_esbc_validate.c
new file mode 100644
index 0000000000..b06235f291
--- /dev/null
+++ b/board/solidrun/common/cmd_esbc_validate.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fsl_validate.h>
+
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (fsl_check_boot_mode_secure() == 0) {
+ printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+ return 0;
+ }
+
+ printf("Core is entering spin loop.\n");
+loop:
+ goto loop;
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ char *hash_str = NULL;
+ uintptr_t haddr;
+ int ret;
+ uintptr_t img_addr = 0;
+ char buf[20];
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+ else if (argc > 2)
+ /* Second arg - Optional - Hash Str*/
+ hash_str = argv[2];
+
+ /* First argument - header address -32/64bit */
+ haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16);
+
+ /* With esbc_validate command, Image address must be
+ * part of header. So, the function is called
+ * by passing this argument as 0.
+ */
+ ret = fsl_secboot_validate(haddr, hash_str, &img_addr);
+
+ /* Need to set "img_addr" even if validation failure.
+ * Required when SB_EN in RCW set and non-fatal error
+ * to continue U-Boot
+ */
+ sprintf(buf, "%lx", img_addr);
+ env_set("img_addr", buf);
+
+ if (ret)
+ return 1;
+
+ printf("esbc_validate command successful\n");
+ return 0;
+}
+
+/***************************************************/
+static char esbc_validate_help_text[] =
+ "esbc_validate hdr_addr <hash_val> - Validates signature using\n"
+ " RSA verification\n"
+ " $hdr_addr Address of header of the image\n"
+ " to be validated.\n"
+ " $hash_val -Optional\n"
+ " It provides Hash of public/srk key to be\n"
+ " used to verify signature.\n";
+
+U_BOOT_CMD(
+ esbc_validate, 3, 0, do_esbc_validate,
+ "Validates signature on a given image using RSA verification",
+ esbc_validate_help_text
+);
+
+U_BOOT_CMD(
+ esbc_halt, 1, 0, do_esbc_halt,
+ "Put the core in spin loop (Secure Boot Only)",
+ ""
+);
+#endif
diff --git a/board/solidrun/common/fsl_chain_of_trust.c b/board/solidrun/common/fsl_chain_of_trust.c
new file mode 100644
index 0000000000..dddfd26a13
--- /dev/null
+++ b/board/solidrun/common/fsl_chain_of_trust.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <dm/root.h>
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
+#include <spl.h>
+#endif
+
+#ifdef CONFIG_ADDR_MAP
+#include <asm/mmu.h>
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
+
+#ifdef CONFIG_ARCH_LS1021A
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#else
+#define gur_in32(a) in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+ uint32_t val;
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+ val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
+ if (val == ITS_MASK)
+ return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+ /* For PBL based platforms check the SB_EN bit in RCWSR */
+ val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+ if (val == RCW_SB_EN_MASK)
+ return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+ /* For Non-PBL Platforms, check the Device Status register 2*/
+ val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+ if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+ return 1;
+
+#endif
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int fsl_setenv_chain_of_trust(void)
+{
+ /* Check Boot Mode
+ * If Boot Mode is Non-Secure, no changes are required
+ */
+ if (fsl_check_boot_mode_secure() == 0)
+ return 0;
+
+ /* If Boot mode is Secure, set the environment variables
+ * bootdelay = 0 (To disable Boot Prompt)
+ * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+ */
+ env_set("bootdelay", "-2");
+
+#ifdef CONFIG_ARM
+ env_set("secureboot", "y");
+#else
+ env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
+{
+ int res;
+
+ /*
+ * Check Boot Mode
+ * If Boot Mode is Non-Secure, skip validation
+ */
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
+ printf("SPL: Validating U-Boot image\n");
+
+#ifdef CONFIG_ADDR_MAP
+ init_addr_map();
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ if (sec_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
+#endif
+
+/*
+ * dm_init_and_scan() is called as part of common SPL framework, so no
+ * need to call it again but in case of powerpc platforms which currently
+ * do not use common SPL framework, so need to call this function here.
+ */
+#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
+ dm_init_and_scan(true);
+#endif
+ res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
+ &img_addr);
+
+ if (res == 0)
+ printf("SPL: Validation of U-boot successful\n");
+}
+
+#ifdef CONFIG_SPL_FRAMEWORK
+/* Override weak funtion defined in SPL framework to enable validation
+ * of main u-boot image before jumping to u-boot image.
+ */
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+ uint32_t hdr_addr;
+
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+
+ hdr_addr = (spl_image->entry_point + spl_image->size -
+ CONFIG_U_BOOT_HDR_SIZE);
+ spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
+ /*
+ * In case of failure in validation, spl_validate_uboot would
+ * not return back in case of Production environment with ITS=1.
+ * Thus U-Boot will not start.
+ * In Development environment (ITS=0 and SB_EN=1), the function
+ * may return back in case of non-fatal failures.
+ */
+
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
+ image_entry();
+}
+#endif /* ifdef CONFIG_SPL_FRAMEWORK */
+#endif /* ifdef CONFIG_SPL_BUILD */
diff --git a/board/solidrun/common/fsl_validate.c b/board/solidrun/common/fsl_validate.c
new file mode 100644
index 0000000000..2bf9d58746
--- /dev/null
+++ b/board/solidrun/common/fsl_validate.c
@@ -0,0 +1,962 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <fsl_sec.h>
+#include <command.h>
+#include <malloc.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <hash.h>
+#include <fsl_secboot_err.h>
+#ifdef CONFIG_ARCH_LS1021A
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#define SHA256_BITS 256
+#define SHA256_BYTES (256/8)
+#define SHA256_NIBBLES (256/4)
+#define NUM_HEX_CHARS (sizeof(ulong) * 2)
+
+#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
+ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
+ ((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
+
+/* This array contains DER value for SHA-256 */
+static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
+ 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
+ 0x04, 0x20
+ };
+
+static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
+
+void branch_to_self(void) __attribute__ ((noreturn));
+
+/*
+ * This function will put core in infinite loop.
+ * This will be called when the ESBC can not proceed further due
+ * to some unknown errors.
+ */
+void branch_to_self(void)
+{
+ printf("Core is in infinite loop due to errors.\n");
+self:
+ goto self;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 check_ie(struct fsl_secboot_img_priv *img)
+{
+ if (img->hdr.ie_flag & IE_FLAG_MASK)
+ return 1;
+
+ return 0;
+}
+
+/* This function returns the CSF Header Address of uboot
+ * For MPC85xx based platforms, the LAW mapping for NOR
+ * flash changes in uboot code. Hence the offset needs
+ * to be calculated and added to the new NOR flash base
+ * address
+ */
+#if defined(CONFIG_MPC85xx)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+ u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+ u32 flash_addr, addr;
+ int found = 0;
+ int i = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ flash_addr = flash_info[i].start[0];
+ addr = flash_info[i].start[0] + csf_flash_offset;
+ if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
+ debug("Barker found on addr %x\n", addr);
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ return -1;
+
+ *csf_addr = addr;
+ *flash_base_addr = flash_addr;
+
+ return 0;
+}
+#else
+/* For platforms like LS1020, correct flash address is present in
+ * the header. So the function reqturns flash base address as 0
+ */
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+
+ if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+ barker_code, ESBC_BARKER_LEN))
+ return -1;
+
+ *csf_addr = csf_hdr_addr;
+ *flash_base_addr = 0;
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ /* For LS-CH3, the address of IE Table is
+ * stated in Scratch13 and scratch14 of DCFG.
+ * Bootrom validates this table while validating uboot.
+ * DCFG is LE*/
+ *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
+ *ie_addr = *ie_addr << 32;
+ *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
+ return 0;
+}
+#else /* CONFIG_ESBC_HDR_LS */
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+ struct fsl_secboot_img_hdr *hdr;
+ struct fsl_secboot_sg_table *sg_tbl;
+ u32 flash_base_addr, csf_addr;
+
+ if (get_csf_base_addr(&csf_addr, &flash_base_addr))
+ return -1;
+
+ hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
+
+ /* For SoC's with Trust Architecture v1 with corenet bus
+ * the sg table field in CSF header has absolute address
+ * for sg table in memory. In other Trust Architecture,
+ * this field specifies the offset of sg table from the
+ * base address of CSF Header
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+ sg_tbl = (struct fsl_secboot_sg_table *)
+ (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
+#else
+ sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
+ (u32)hdr->psgtable);
+#endif
+
+ /* IE Key Table is the first entry in the SG Table */
+#if defined(CONFIG_MPC85xx)
+ *ie_addr = (uintptr_t)((sg_tbl->src_addr &
+ ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ flash_base_addr);
+#else
+ *ie_addr = (uintptr_t)sg_tbl->src_addr;
+#endif
+
+ debug("IE Table address is %lx\n", *ie_addr);
+ return 0;
+}
+#endif /* CONFIG_ESBC_HDR_LS */
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+/* This function checks srk_table_flag in header and set/reset srk_flag.*/
+static u32 check_srk(struct fsl_secboot_img_priv *img)
+{
+#ifdef CONFIG_ESBC_HDR_LS
+ /* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ return !check_ie(img);
+#endif
+ return 1;
+#else
+ if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
+ return 1;
+
+ return 0;
+#endif
+}
+
+/* This function returns ospr's key_revoc values.*/
+static u32 get_key_revoc(void)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+ OSPR_KEY_REVOC_SHIFT;
+}
+
+/* This function checks if selected key is revoked or not.*/
+static u32 is_key_revoked(u32 keynum, u32 rev_flag)
+{
+ if (keynum == UNREVOCABLE_KEY)
+ return 0;
+
+ if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag)
+ return 1;
+
+ return 0;
+}
+
+/* It read validates srk_table key lengths.*/
+static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img)
+{
+ int i = 0;
+ u32 ret, key_num, key_revoc_flag, size;
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+ key_num = hdr->len_kr.srk_sel;
+ if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+ size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+ memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+ for (i = 0; i < hdr->len_kr.num_srk; i++) {
+ if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len))
+ return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
+ }
+
+ img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+ memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
+ img->key_len);
+
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_ESBC_HDR_LS
+static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ /* check key length */
+ if (!CHECK_KEY_LEN(hdr->key_len))
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+ memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
+
+ img->key_len = hdr->key_len;
+
+ return 0;
+}
+#endif /* CONFIG_ESBC_HDR_LS */
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+ struct fsl_secboot_img_priv *img)
+{
+ /* Copy IE tbl to Global Data */
+ memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
+ img->ie_addr = (uintptr_t)&glb.ie_tbl;
+ glb.ie_addr = img->ie_addr;
+}
+
+static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ u32 ie_key_len, ie_revoc_flag, ie_num;
+ struct ie_key_info *ie_info;
+
+ if (!img->ie_addr) {
+ if (get_ie_info_addr(&img->ie_addr))
+ return ERROR_IE_TABLE_NOT_FOUND;
+ else
+ install_ie_tbl(img->ie_addr, img);
+ }
+
+ ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
+ if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+ ie_num = hdr->ie_key_sel;
+ if (ie_num == 0 || ie_num > ie_info->num_keys)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+ ie_revoc_flag = ie_info->key_revok;
+ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+ if (!CHECK_KEY_LEN(ie_key_len))
+ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+ memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+ ie_key_len);
+
+ img->key_len = ie_key_len;
+ return 0;
+}
+#endif
+
+
+/* This function return length of public key.*/
+static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
+{
+ return img->key_len;
+}
+
+/*
+ * Handles the ESBC uboot client header verification failure.
+ * This function handles all the errors which might occur in the
+ * parsing and checking of ESBC uboot client header. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_header_verification_failure(void)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+
+ /* 29th bit of OSPR is ITS */
+ u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
+
+ if (its == 1)
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+ else
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+}
+
+/*
+ * Handles the ESBC uboot client image verification failure.
+ * This function handles all the errors which might occur in the
+ * public key hash comparison and signature verification of
+ * ESBC uboot client image. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_image_verification_failure(void)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+
+ u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
+
+ if (its == 1) {
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
+ } else {
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
+ }
+}
+
+static void fsl_secboot_bootscript_parse_failure(void)
+{
+ fsl_secboot_header_verification_failure();
+}
+
+/*
+ * Handles the errors in esbc boot.
+ * This function handles all the errors which might occur in the
+ * esbc boot phase. It will call the appropriate api to log the
+ * errors and set the error bits in the SEC_MON.
+ */
+void fsl_secboot_handle_error(int error)
+{
+#ifndef CONFIG_SPL_BUILD
+ const struct fsl_secboot_errcode *e;
+
+ for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
+ e++) {
+ if (e->errcode == error)
+ printf("ERROR :: %x :: %s\n", error, e->name);
+ }
+#else
+ printf("ERROR :: %x\n", error);
+#endif
+
+ /* If Boot Mode is secure, transition the SNVS state and issue
+ * reset based on type of failure and ITS setting.
+ * If Boot mode is non-secure, return from this function.
+ */
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
+ switch (error) {
+ case ERROR_ESBC_CLIENT_HEADER_BARKER:
+ case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1:
+ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2:
+ case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
+ case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+ case ERROR_KEY_TABLE_NOT_FOUND:
+#ifdef CONFIG_KEY_REVOCATION
+ case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ /*@fallthrough@*/
+ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
+ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM:
+ case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN:
+ case ERROR_IE_TABLE_NOT_FOUND:
+#endif
+ fsl_secboot_header_verification_failure();
+ break;
+ case ERROR_ESBC_SEC_RESET:
+ case ERROR_ESBC_SEC_DEQ:
+ case ERROR_ESBC_SEC_ENQ:
+ case ERROR_ESBC_SEC_DEQ_TO:
+ case ERROR_ESBC_SEC_JOBQ_STATUS:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY:
+ case ERROR_ESBC_CLIENT_HASH_COMPARE_EM:
+ fsl_secboot_image_verification_failure();
+ break;
+ case ERROR_ESBC_MISSING_BOOTM:
+ fsl_secboot_bootscript_parse_failure();
+ break;
+ case ERROR_ESBC_WRONG_CMD:
+ default:
+ branch_to_self();
+ break;
+ }
+}
+
+static void fsl_secblk_handle_error(int error)
+{
+ switch (error) {
+ case ERROR_ESBC_SEC_ENQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ);
+ break;
+ case ERROR_ESBC_SEC_DEQ_TO:
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO);
+ break;
+ default:
+ printf("Job Queue Output status %x\n", error);
+ fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS);
+ break;
+ }
+}
+
+/*
+ * Calculate hash of key obtained via offset present in ESBC uboot
+ * client hdr. This function calculates the hash of key which is obtained
+ * through offset present in ESBC uboot client header.
+ */
+static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int i, srk = 0;
+ int ret = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate hash of the esbc key */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ if (ret)
+ return ret;
+
+ /* Update hash for ESBC key */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ srk = 1;
+ }
+#endif
+ if (!srk)
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->key_len, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < SHA256_BYTES; i++)
+ img->img_key_hash[i] = hash_val[i];
+
+ return 0;
+}
+
+/*
+ * Calculate hash of ESBC hdr and ESBC. This function calculates the
+ * single hash of ESBC header and ESBC image. If SG flag is on, all
+ * SG entries are also hashed alongwith the complete SG table.
+ */
+static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
+{
+ struct hash_algo *algo;
+ void *ctx;
+ int ret = 0;
+ int key_hash = 0;
+ const char *algo_name = "sha256";
+
+ /* Calculate the hash of the ESBC */
+ ret = hash_progressive_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ ret = algo->hash_init(algo, &ctx);
+ /* Copy hash at destination buffer */
+ if (ret)
+ return ret;
+
+ /* Update hash for CSF Header */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
+ if (ret)
+ return ret;
+
+ /* Update the hash with that of srk table if srk flag is 1
+ * If IE Table is selected, key is not added in the hash
+ * If neither srk table nor IE key table available, add key
+ * from header in the hash calculation
+ */
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+ key_hash = 1;
+ }
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_hash && check_ie(img))
+ key_hash = 1;
+#endif
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+ if (!key_hash) {
+ ret = algo->hash_update(algo, ctx,
+ img->img_key, img->hdr.key_len, 0);
+ key_hash = 1;
+ }
+#endif
+ if (ret)
+ return ret;
+ if (!key_hash)
+ return ERROR_KEY_TABLE_NOT_FOUND;
+
+ /* Update hash for actual Image */
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
+ if (ret)
+ return ret;
+
+ /* Copy hash at destination buffer */
+ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
+ * pointers for padding, DER value and hash. And finally, constructs EM'
+ * which includes hash of complete CSF header and ESBC image. If SG flag
+ * is on, hash of SG table and entries is also included.
+ */
+static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img)
+{
+ /*
+ * RSA PKCSv1.5 encoding format for encoded message is below
+ * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
+ * PS is Padding String
+ * DER is DER value for SHA-256
+ * Hash is SHA-256 hash
+ * *********************************************************
+ * representative points to first byte of EM initially and is
+ * filled with 0x0
+ * representative is incremented by 1 and second byte is filled
+ * with 0x1
+ * padding points to third byte of EM
+ * digest points to full length of EM - 32 bytes
+ * hash_id (DER value) points to 19 bytes before pDigest
+ * separator is one byte which separates padding and DER
+ */
+
+ size_t len;
+ u8 *representative;
+ u8 *padding, *digest;
+ u8 *hash_id, *separator;
+ int i;
+
+ len = (get_key_len(img) / 2) - 1;
+ representative = img->img_encoded_hash_second;
+ representative[0] = 0;
+ representative[1] = 1; /* block type 1 */
+
+ padding = &representative[2];
+ digest = &representative[1] + len - 32;
+ hash_id = digest - sizeof(hash_identifier);
+ separator = hash_id - 1;
+
+ /* fill padding area pointed by padding with 0xff */
+ memset(padding, 0xff, separator - padding);
+
+ /* fill byte pointed by separator */
+ *separator = 0;
+
+ /* fill SHA-256 DER value pointed by HashId */
+ memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
+
+ /* fill hash pointed by Digest */
+ for (i = 0; i < SHA256_BYTES; i++)
+ digest[i] = hash_val[i];
+}
+
+/*
+ * Reads and validates the ESBC client header.
+ * This function reads key and signature from the ESBC client header.
+ * If Scatter/Gather flag is on, lengths and offsets of images
+ * present as SG entries are also read. This function also checks
+ * whether the header is valid or not.
+ */
+static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = &img->hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+ u8 *k, *s;
+ u32 ret = 0;
+
+ int key_found = 0;
+
+ /* check barker code */
+ if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
+ return ERROR_ESBC_CLIENT_HEADER_BARKER;
+
+ /* If Image Address is not passed as argument to function,
+ * then Address and Size must be read from the Header.
+ */
+ if (*(img->img_addr_ptr) == 0) {
+ #ifdef CONFIG_ESBC_ADDR_64BIT
+ *(img->img_addr_ptr) = hdr->pimg64;
+ #else
+ *(img->img_addr_ptr) = hdr->pimg;
+ #endif
+ }
+
+ if (!hdr->img_size)
+ return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+
+ img->img_size = hdr->img_size;
+
+ /* Key checking*/
+#ifdef CONFIG_KEY_REVOCATION
+ if (check_srk(img)) {
+ ret = read_validate_srk_tbl(img);
+ if (ret != 0)
+ return ret;
+ key_found = 1;
+ }
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!key_found && check_ie(img)) {
+ ret = read_validate_ie_tbl(img);
+ if (ret != 0)
+ return ret;
+ key_found = 1;
+ }
+#endif
+#ifndef CONFIG_ESBC_HDR_LS
+/* Single Key Feature not available in LS ESBC Header */
+ if (key_found == 0) {
+ ret = read_validate_single_key(img);
+ if (ret != 0)
+ return ret;
+ key_found = 1;
+ }
+#endif
+ if (!key_found)
+ return ERROR_KEY_TABLE_NOT_FOUND;
+
+ /* check signaure */
+ if (get_key_len(img) == 2 * hdr->sign_len) {
+ /* check signature length */
+ if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) ||
+ (hdr->sign_len == KEY_SIZE_BYTES / 2) ||
+ (hdr->sign_len == KEY_SIZE_BYTES)))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_LEN;
+ } else {
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN;
+ }
+
+ memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
+/* No SG support in LS-CH3 */
+#ifndef CONFIG_ESBC_HDR_LS
+ /* No SG support */
+ if (hdr->sg_flag)
+ return ERROR_ESBC_CLIENT_HEADER_SG;
+#endif
+
+ /* modulus most significant bit should be set */
+ k = (u8 *)&img->img_key;
+
+ if ((k[0] & 0x80) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1;
+
+ /* modulus value should be odd */
+ if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2;
+
+ /* Check signature value < modulus value */
+ s = (u8 *)&img->img_sign;
+
+ if (!(memcmp(s, k, hdr->sign_len) < 0))
+ return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD;
+
+ return ESBC_VALID_HDR;
+}
+
+static inline int str2longbe(const char *p, ulong *num)
+{
+ char *endptr;
+ ulong tmp;
+
+ if (!p) {
+ return 0;
+ } else {
+ tmp = simple_strtoul(p, &endptr, 16);
+ if (sizeof(ulong) == 4)
+ *num = cpu_to_be32(tmp);
+ else
+ *num = cpu_to_be64(tmp);
+ }
+
+ return *p != '\0' && *endptr == '\0';
+}
+/* Function to calculate the ESBC Image Hash
+ * and hash from Digital signature.
+ * The Two hash's are compared to yield the
+ * result of signature validation.
+ */
+static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
+{
+ int ret;
+ uint32_t key_len;
+ struct key_prop prop;
+#if !defined(USE_HOSTCC)
+ struct udevice *mod_exp_dev;
+#endif
+ ret = calc_esbchdr_esbc_hash(img);
+ if (ret)
+ return ret;
+
+ /* Construct encoded hash EM' wrt PKCSv1.5 */
+ construct_img_encoded_hash_second(img);
+
+ /* Fill prop structure for public key */
+ memset(&prop, 0, sizeof(struct key_prop));
+ key_len = get_key_len(img) / 2;
+ prop.modulus = img->img_key;
+ prop.public_exponent = img->img_key + key_len;
+ prop.num_bits = key_len * 8;
+ prop.exp_len = key_len;
+
+ ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
+ if (ret) {
+ printf("RSA: Can't find Modular Exp implementation\n");
+ return -EINVAL;
+ }
+
+ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+ &prop, img->img_encoded_hash);
+ if (ret)
+ return ret;
+
+ /*
+ * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+ * memcmp returns zero on success
+ * memcmp returns non-zero on failure
+ */
+ ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
+ img->hdr.sign_len);
+
+ if (ret)
+ return ERROR_ESBC_CLIENT_HASH_COMPARE_EM;
+
+ return 0;
+}
+/* Function to initialize img priv and global data structure
+ */
+static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
+{
+ *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
+
+ struct fsl_secboot_img_priv *img = *img_ptr;
+
+ if (!img)
+ return -ENOMEM;
+ memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (glb.ie_addr)
+ img->ie_addr = glb.ie_addr;
+#endif
+ return 0;
+}
+
+
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overrides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overrides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+ uintptr_t *img_addr_ptr)
+{
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ ulong hash[SHA256_BYTES/sizeof(ulong)];
+ char hash_str[NUM_HEX_CHARS + 1];
+ struct fsl_secboot_img_priv *img;
+ struct fsl_secboot_img_hdr *hdr;
+ void *esbc;
+ int ret, i, hash_cmd = 0;
+ u32 srk_hash[8];
+
+ if (arg_hash_str != NULL) {
+ const char *cp = arg_hash_str;
+ int i = 0;
+
+ if (*cp == '0' && *(cp + 1) == 'x')
+ cp += 2;
+
+ /* The input string expected is in hex, where
+ * each 4 bits would be represented by a hex
+ * sha256 hash is 256 bits long, which would mean
+ * num of characters = 256 / 4
+ */
+ if (strlen(cp) != SHA256_NIBBLES) {
+ printf("%s is not a 256 bits hex string as expected\n",
+ arg_hash_str);
+ return -1;
+ }
+
+ for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) {
+ strncpy(hash_str, cp + (i * NUM_HEX_CHARS),
+ NUM_HEX_CHARS);
+ hash_str[NUM_HEX_CHARS] = '\0';
+ if (!str2longbe(hash_str, &hash[i])) {
+ printf("%s is not a 256 bits hex string ",
+ arg_hash_str);
+ return -1;
+ }
+ }
+
+ hash_cmd = 1;
+ }
+
+ ret = secboot_init(&img);
+ if (ret)
+ goto exit;
+
+ /* Update the information in Private Struct */
+ hdr = &img->hdr;
+ img->ehdrloc = haddr;
+ img->img_addr_ptr = img_addr_ptr;
+ esbc = (u8 *)img->ehdrloc;
+
+ memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
+
+ /* read and validate esbc header */
+ ret = read_validate_esbc_client_header(img);
+
+ if (ret != ESBC_VALID_HDR) {
+ fsl_secboot_handle_error(ret);
+ goto exit;
+ }
+
+ /* SRKH present in SFP */
+ for (i = 0; i < NUM_SRKH_REGS; i++)
+ srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]);
+
+ /*
+ * Calculate hash of key obtained via offset present in
+ * ESBC uboot client hdr
+ */
+ ret = calc_img_key_hash(img);
+ if (ret) {
+ fsl_secblk_handle_error(ret);
+ goto exit;
+ }
+
+ /* Compare hash obtained above with SRK hash present in SFP */
+ if (hash_cmd)
+ ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES);
+ else
+ ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+ if (!hash_cmd && check_ie(img))
+ ret = 0;
+#endif
+
+ if (ret != 0) {
+ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY);
+ goto exit;
+ }
+
+ ret = calculate_cmp_img_sig(img);
+ if (ret) {
+ fsl_secboot_handle_error(ret);
+ goto exit;
+ }
+
+exit:
+ /* Free Img as it was malloc'ed*/
+ free(img);
+ return ret;
+}
diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
new file mode 100644
index 0000000000..cc81e80c37
--- /dev/null
+++ b/board/solidrun/common/vid.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ */
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/io.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#elif defined(CONFIG_FSL_LSCH3)
+#include <asm/arch/immap_lsch3.h>
+#else
+#include <asm/immap_85xx.h>
+#endif
+#include "vid.h"
+
+int __weak i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return 0;
+}
+
+/*
+ * Compensate for a board specific voltage drop between regulator and SoC
+ * return a value in mV
+ */
+int __weak board_vdd_drop_compensation(void)
+{
+ return 0;
+}
+
+/*
+ * Board specific settings for specific voltage value
+ */
+int __weak board_adjust_vdd(int vdd)
+{
+ return 0;
+}
+
+/* Maximum loop count waiting for new voltage to take effect */
+#define MAX_LOOP_WAIT_NEW_VOL 100
+/* Maximum loop count waiting for the voltage to be stable */
+#define MAX_LOOP_WAIT_VOL_STABLE 100
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
+ * another reading
+ */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+/* If an INA220 chip is available, we can use it to read back the voltage
+ * as it may have a higher accuracy than the IR chip for the same purpose
+ */
+#ifdef CONFIG_VOL_MONITOR_INA220
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#else
+#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#endif
+
+/* read the current value of the LTC Regulator Voltage */
+static int read_voltage_from_LTC(int i2caddress)
+{
+ int ret, vcode = 0;
+ u8 chan = PWM_CHANNEL0;
+
+ /* select the PAGE 0 using PMBus commands PAGE for VDD*/
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE, 1, &chan, 1);
+ if (ret) {
+ printf("VID: failed to select VDD Page 0\n");
+ return ret;
+ }
+
+ /*read the output voltage using PMBus command READ_VOUT*/
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+
+ /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
+ vcode = DIV_ROUND_UP(vcode * 1000, 4096);
+
+ return vcode;
+}
+
+static int read_voltage(int i2caddress)
+{
+ int voltage_read;
+ voltage_read = read_voltage_from_LTC(i2caddress);
+ return voltage_read;
+}
+
+/* this function sets the VDD and returns the value set */
+static int set_voltage_to_LTC(int i2caddress, int vdd)
+{
+ int ret, vdd_last, vdd_target = vdd;
+ int count = 100, temp = 0;
+
+ /* Scale up to the LTC resolution is 1/4096V */
+ vdd = (vdd * 4096) / 1000;
+
+ /* 5-byte buffer which needs to be sent following the
+ * PMBus command PAGE_PLUS_WRITE.
+ */
+ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+ vdd & 0xFF, (vdd & 0xFF00) >> 8};
+
+ /* Write the desired voltage code to the regulator */
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ if (ret) {
+ printf("VID: I2C failed to write to the volatge regulator\n");
+ return -1;
+ }
+
+ /* Wait for the volatge to get to the desired value */
+ do {
+ vdd_last = read_voltage_from_LTC(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjust\n");
+ return -1;
+ }
+ count--;
+ temp = vdd_last - vdd_target;
+ } while ((abs(temp) > 2) && (count > 0));
+
+ return vdd_last;
+}
+
+static int set_voltage(int i2caddress, int vdd)
+{
+ int vdd_last = -1;
+
+ vdd_last = set_voltage_to_LTC(i2caddress, vdd);
+ return vdd_last;
+}
+
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const u16 vdd[32] = {
+ 8250,
+ 7875,
+ 7750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 8000,
+ 8125,
+ 8250,
+ 0, /* reserved */
+ 8500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+ printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target);
+
+ /* check override variable for overriding VDD */
+ vdd_string = env_get(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
+ /* Check vdd_target is in valid range */
+ printf("VID: Target VID %d mV is not in range.\n",
+ vdd_target);
+ ret = -1;
+ goto exit;
+ } else {
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+
+ /* Set the target voltage */
+ vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
+ if (board_adjust_vdd(vdd_target) < 0) {
+ ret = -1;
+ goto exit;
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+ return ret;
+}
+
+static int print_vdd(void)
+{
+ int vdd_last, ret, i2caddress;
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID : I2c failed to switch channel\n");
+ return -1;
+ }
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ goto exit;
+ }
+ printf("VID: Core voltage is at %d mV\n", vdd_last);
+exit:
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+ return ret < 0 ? -1 : 0;
+
+}
+
+static int do_vdd_override(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ ulong override;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!strict_strtoul(argv[1], 10, &override))
+ adjust_vdd(override); /* the value is checked by callee */
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+static int do_vdd_read(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ print_vdd();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vdd_override, 2, 0, do_vdd_override,
+ "override VDD",
+ " - override with the voltage specified in mV, eg. 1050"
+);
+
+U_BOOT_CMD(
+ vdd_read, 1, 0, do_vdd_read,
+ "read VDD",
+ " - Read the voltage specified in mV"
+)
diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
new file mode 100644
index 0000000000..99778e9a93
--- /dev/null
+++ b/board/solidrun/common/vid.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __VID_H_
+#define __VID_H_
+
+#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
+#define IR36021_LOOP1_VOUT_OFFSET 0x9A
+#define IR36021_MFR_ID_OFFSET 0x92
+#define IR36021_MFR_ID 0x43
+#define IR36021_INTEL_MODE_OOFSET 0x14
+#define IR36021_MODE_MASK 0x20
+#define IR36021_INTEL_MODE 0x00
+#define IR36021_AMD_MODE 0x20
+
+/* step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN 5
+#define IR_VDD_STEP_UP 5
+int adjust_vdd(ulong vdd_override);
+
+#endif /* __VID_H_ */
--
2.25.1
patches/u-boot-LSDK-21.08/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch 0 → 100644
View file @ a393e2e7
From f8ac0b82bf2af732251419f05b9058e78ca2dbec Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:37:22 +0300
Subject: [PATCH 5/6] armv8: lx2160acex7: lx2160acex device tree
Based on NXP's LX2160ARDB device tree; it defines -
1. MX35X based SPI flash
2. SDHC0 (SD card) and SDHC1 (eMMC)
3. 4 SATA ports that depending on SERDES configuration they can get
connected to external SATA drives
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
new file mode 100644
index 0000000000..4fbcaafb0e
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2160ACEX7 device tree source
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * Copyright 2019 SolidRun ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160ACEX7 COM express type 7 based board";
+ compatible = "fsl,lx2160acex7", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+ };
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: MT35XU512ABA1G12@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
--
2.17.1
patches/u-boot-LSDK-21.08/0006-armv8-lx2160acex7-board-support-files.patch 0 → 100644
View file @ a393e2e7
From 462ecf12a531de55b68fd846c10aa5487934479b Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:45:24 +0300
Subject: [PATCH 6/6] armv8: lx2160acex7: board support files
The lx2160acex7 board support files does the following -
1. Initializes 1GBps PHY address according to SERDES1 block config.
2. Sets uart0 as the console
3. Sets EMC2301 PWM fan controller to it's default value
4. Misc FDT fixups prior to booting Linux
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/Kconfig | 22 ++
board/solidrun/lx2160a/MAINTAINERS | 8 +
board/solidrun/lx2160a/Makefile | 9 +
board/solidrun/lx2160a/ddr.c | 20 ++
board/solidrun/lx2160a/eth_lx2160acex7.c | 104 ++++++++
board/solidrun/lx2160a/lx2160a.c | 288 +++++++++++++++++++++++
6 files changed, 451 insertions(+)
create mode 100644 board/solidrun/lx2160a/Kconfig
create mode 100644 board/solidrun/lx2160a/MAINTAINERS
create mode 100644 board/solidrun/lx2160a/Makefile
create mode 100644 board/solidrun/lx2160a/ddr.c
create mode 100644 board/solidrun/lx2160a/eth_lx2160acex7.c
create mode 100644 board/solidrun/lx2160a/lx2160a.c
diff --git a/board/solidrun/lx2160a/Kconfig b/board/solidrun/lx2160a/Kconfig
new file mode 100644
index 0000000000..85abac9bfc
--- /dev/null
+++ b/board/solidrun/lx2160a/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_LX2160ACEX7
+
+config SYS_BOARD
+ default "lx2160a"
+
+config SYS_VENDOR
+ default "solidrun"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "lx2160acex7"
+
+config EMC2301
+ bool "Fan controller"
+ help
+ Enable the EMC2301 fan controller for configuration of fan
+ speed.
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/board/solidrun/lx2160a/MAINTAINERS b/board/solidrun/lx2160a/MAINTAINERS
new file mode 100644
index 0000000000..688ff66afa
--- /dev/null
+++ b/board/solidrun/lx2160a/MAINTAINERS
@@ -0,0 +1,8 @@
+LX2160ACEX7 BOARD
+M: Rabeeh Khoury <rabeeh@solid-run.com>
+S: Maintained
+F: board/solidrun/lx2160a/
+F: include/configs/lx2160a_common.h
+F: include/configs/lx2160acex7.h
+F: configs/lx2160acex7_tfa_defconfig
+F: arch/arm/dts/fsl-lx2160a-cex7.dts
diff --git a/board/solidrun/lx2160a/Makefile b/board/solidrun/lx2160a/Makefile
new file mode 100644
index 0000000000..c92266f322
--- /dev/null
+++ b/board/solidrun/lx2160a/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2019 SolidRun ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lx2160a.o
+obj-y += ddr.o
+obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o
diff --git a/board/solidrun/lx2160a/ddr.c b/board/solidrun/lx2160a/ddr.c
new file mode 100644
index 0000000000..9c7bd10475
--- /dev/null
+++ b/board/solidrun/lx2160a/ddr.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
new file mode 100644
index 0000000000..97e414838f
--- /dev/null
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 SolidRun ltd.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ struct memac_mdio_info mdio_info;
+ struct memac_mdio_controller *reg;
+ int i, interface;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ switch (srds_s1) {
+ case 3:
+ case 5:
+ case 8:
+ case 13:
+ case 14:
+ case 15:
+ case 17:
+ case 20:
+ case 23:
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ break;
+
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
+ srds_s1);
+ goto next;
+ }
+ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+next:
+ cpu_eth_init(bis);
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+int fdt_fixup_board_phy(void *fdt)
+{
+ int mdio_offset;
+ int ret;
+ struct mii_dev *dev;
+
+ ret = 0;
+
+ return ret;
+}
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
new file mode 100644
index 0000000000..b0d9f1012e
--- /dev/null
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <efi_loader.h>
+#include <asm/arch/mmu.h>
+#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include "../../freescale/common/vid.h"
+#include <fsl_immap.h>
+
+#ifdef CONFIG_EMC2301
+#include "../common/emc2301.h"
+#endif
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_serial_platdata serial0 = {
+#if CONFIG_CONS_INDEX == 0
+ .base = CONFIG_SYS_SERIAL0,
+#elif CONFIG_CONS_INDEX == 1
+ .base = CONFIG_SYS_SERIAL1,
+#else
+#error "Unsupported console index value."
+#endif
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial0,
+};
+
+static struct pl01x_serial_platdata serial1 = {
+ .base = CONFIG_SYS_SERIAL1,
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial1) = {
+ .name = "serial_pl01x",
+ .platdata = &serial1,
+};
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void uart_get_clock(void)
+{
+ serial0.clock = get_serial_clock();
+ serial1.clock = get_serial_clock();
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+ /* get required clock for UART IP */
+ uart_get_clock();
+
+#ifdef CONFIG_EMC2301
+ select_i2c_ch_pca9547(I2C_MUX_CH_EMC2301);
+ emc2301_init();
+ set_fan_speed(I2C_EMC2301_PWM);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#endif
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+ return 0;
+}
+#endif
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ /* Enable both esdhc DT nodes for LX2160ARDB */
+ do_fixup_by_compat(blob, compat, "status", "okay",
+ sizeof("okay"), 1);
+ return 0;
+}
+
+#if defined(CONFIG_VID)
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+#endif
+
+int checkboard(void)
+{
+ enum boot_src src = get_boot_src();
+ char buf[64];
+ cpu_name(buf);
+ printf("Board: %s-CEX7, ", buf);
+
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ }
+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+ return 0;
+}
+
+int config_board_mux(void)
+{
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return 100000000;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return 100000000;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ int i;
+ u64 ddr_size = 0;
+
+ puts("\nDDR ");
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ ddr_size += gd->bd->bi_dram[i].size;
+ print_size(ddr_size, "");
+ print_ddr_info(0);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ config_board_mux();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+extern int fdt_fixup_board_phy(void *fdt);
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0) {
+ printf("%s: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
+ fdt_status_okay(fdt, offset);
+ fdt_fixup_board_phy(fdt);
+ } else {
+ fdt_status_fail(fdt, offset);
+ }
+}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int i;
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
+
+ ft_cpu_setup(blob, bd);
+
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
+ /* fixup DT for the three GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+ else if (gd->arch.resv_ram >= base[2] &&
+ gd->arch.resv_ram < base[2] + size[2])
+ size[2] = gd->arch.resv_ram - base[2];
+#endif
+
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+#ifdef CONFIG_USB
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+#endif
--
2.17.1
patches/u-boot-LSDK-21.08/0008-uboot-add-nvme-commands-and-for-distroboot.patch 0 → 100644
View file @ a393e2e7
From a1fddcaae71a95bd4b9963c9000b9c88b6d152d5 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 11 Nov 2019 23:45:31 +0200
Subject: [PATCH] uboot - add nvme commands and for distroboot
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
configs/lx2160acex7_tfa_defconfig | 2 ++
include/configs/lx2160a_common.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index d59de7d054..3891d2a7c4 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_NVME=y
+CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 34cc29685d..7c2d749a9e 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -306,6 +306,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(SCSI, scsi, 0) \
+ func(NVME, nvme, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
--
2.17.1
patches/u-boot-LSDK-21.08/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch 0 → 100644
View file @ a393e2e7
From 4a5e1552f13acc1e8ee91b456ea37e9d39bdae01 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 13:32:09 +0200
Subject: [PATCH] armv8: lx2160acex7: Fix booting from NVMe drives
Currently NVMe is not initialized so u-boot fails to read kernel from
NVMe drive. This patch modifies default environment so it initializes
NVMe as part of default startup script...
Credit to Damjan Marion <dmarion@me.com> on fixing that on LSDK-19.09.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160a_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index bacad51bfb..cee462ef63 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -248,6 +248,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
BOOTENV \
"mcmemsize=0x70000000\0" \
XSPI_MC_INIT_CMD \
+ "nvme_need_init=true\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
--
2.17.1
patches/u-boot-LSDK-21.08/0011-lx2160acex7-common-update-vid-to-LSDK-20.12.patch 0 → 100644
View file @ a393e2e7
From 6f3137459f4093e70cfac8d1b51806f5a111cd52 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 12 Jan 2021 12:10:05 +0200
Subject: [PATCH 2/2] lx2160acex7: common: update vid to LSDK-20.12
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/common/vid.c | 692 +++++++++++++++++++++++++++++++++++-
board/solidrun/common/vid.h | 20 ++
2 files changed, 703 insertions(+), 9 deletions(-)
diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
index cc81e80c37..0256d035eb 100644
--- a/board/solidrun/common/vid.c
+++ b/board/solidrun/common/vid.c
@@ -1,11 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2020 NXP
*/
+
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
+#include <irq_func.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_LSCH2
#include <asm/arch/immap_lsch2.h>
@@ -38,6 +41,52 @@ int __weak board_adjust_vdd(int vdd)
return 0;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+/*
+ * Get the i2c address configuration for the IR regulator chip
+ *
+ * There are some variance in the RDB HW regarding the I2C address configuration
+ * for the IR regulator chip, which is likely a problem of external resistor
+ * accuracy. So we just check each address in a hopefully non-intrusive mode
+ * and use the first one that seems to work
+ *
+ * The IR chip can show up under the following addresses:
+ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
+ * 0x09 (Verified on T1040RDB-PA)
+ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
+ */
+static int find_ir_chip_on_i2c(void)
+{
+ int i2caddress;
+ int ret;
+ u8 byte;
+ int i;
+ const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
+
+ /* Check all the address */
+ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
+ i2caddress = ir_i2c_addr[i];
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
+ sizeof(byte));
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
+ (void *)&byte, sizeof(byte));
+#endif
+ if ((ret >= 0) && (byte == IR36021_MFR_ID))
+ return i2caddress;
+ }
+ return -1;
+}
+#endif
+
/* Maximum loop count waiting for new voltage to take effect */
#define MAX_LOOP_WAIT_NEW_VOL 100
/* Maximum loop count waiting for the voltage to be stable */
@@ -60,23 +109,135 @@ int __weak board_adjust_vdd(int vdd)
#define ADC_MIN_ACCURACY 4
#endif
+#ifdef CONFIG_VOL_MONITOR_INA220
+static int read_voltage_from_INA220(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf[2];
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
+
+ for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
+ (void *)&buf, 2);
+#else
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+ (void *)&buf, 2);
+#endif
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ vol_mon = (buf[0] << 8) | buf[1];
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+#endif
+
+/* read voltage from IR */
+#ifdef CONFIG_VOL_MONITOR_IR36021_READ
+static int read_voltage_from_IR(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
+
+ for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ IR36021_LOOP1_VOUT_OFFSET,
+ 1, (void *)&buf, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
+ (void *)&buf, 1);
+#endif
+ if (ret) {
+ printf("VID: failed to read vcpu\n");
+ return ret;
+ }
+ vol_mon = buf;
+ if (!vol_mon) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%02x\n", vol_mon);
+ /* Resolution is 1/128V. We scale up here to get 1/128mV
+ * and divide at the end
+ */
+ voltage_read += vol_mon * 1000;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* Scale down to the real mV as IR resolution is 1/128V, rounding up */
+ voltage_read = DIV_ROUND_UP(voltage_read, 128);
+
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ voltage_read -= board_vdd_drop_compensation();
+
+ return voltage_read;
+}
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
/* read the current value of the LTC Regulator Voltage */
static int read_voltage_from_LTC(int i2caddress)
{
int ret, vcode = 0;
u8 chan = PWM_CHANNEL0;
+#ifndef CONFIG_DM_I2C
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
+#endif
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
+#ifndef CONFIG_DM_I2C
/*read the output voltage using PMBus command READ_VOUT*/
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+ ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@@ -87,19 +248,137 @@ static int read_voltage_from_LTC(int i2caddress)
return vcode;
}
+#endif
static int read_voltage(int i2caddress)
{
int voltage_read;
+#ifdef CONFIG_VOL_MONITOR_INA220
+ voltage_read = read_voltage_from_INA220(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_IR36021_READ
+ voltage_read = read_voltage_from_IR(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
voltage_read = read_voltage_from_LTC(i2caddress);
+#else
+ return -1;
+#endif
return voltage_read;
}
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+/*
+ * We need to calculate how long before the voltage stops to drop
+ * or increase. It returns with the loop count. Each loop takes
+ * several readings (WAIT_FOR_ADC)
+ */
+static int wait_for_new_voltage(int vdd, int i2caddress)
+{
+ int timeout, vdd_current;
+
+ vdd_current = read_voltage(i2caddress);
+ /* wait until voltage starts to reach the target. Voltage slew
+ * rates by typical regulators will always lead to stable readings
+ * within each fairly long ADC interval in comparison to the
+ * intended voltage delta change until the target voltage is
+ * reached. The fairly small voltage delta change to any target
+ * VID voltage also means that this function will always complete
+ * within few iterations. If the timeout was ever reached, it would
+ * point to a serious failure in the regulator system.
+ */
+ for (timeout = 0;
+ abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
+ timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+ return timeout;
+}
+
+/*
+ * this function keeps reading the voltage until it is stable or until the
+ * timeout expires
+ */
+static int wait_for_voltage_stable(int i2caddress)
+{
+ int timeout, vdd_current, vdd;
+
+ vdd = read_voltage(i2caddress);
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+
+ /* wait until voltage is stable */
+ vdd_current = read_voltage(i2caddress);
+ /* The maximum timeout is
+ * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
+ */
+ for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
+ abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
+ timeout > 0; timeout--) {
+ vdd = vdd_current;
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout == 0)
+ return -1;
+ return vdd_current;
+}
+
+/* Set the voltage to the IR chip */
+static int set_voltage_to_IR(int i2caddress, int vdd)
+{
+ int wait, vdd_last;
+ int ret;
+ u8 vid;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_FSL_LSCH2
+ vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
+ vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
+
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ 1, (void *)&vid, sizeof(vid));
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ (void *)&vid, sizeof(vid));
+
+#endif
+ if (ret) {
+ printf("VID: failed to write VID\n");
+ return -1;
+ }
+ wait = wait_for_new_voltage(vdd, i2caddress);
+ if (wait < 0)
+ return -1;
+ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+
+ vdd_last = wait_for_voltage_stable(i2caddress);
+ if (vdd_last < 0)
+ return -1;
+ debug("VID: Current voltage is %d mV\n", vdd_last);
+ return vdd_last;
+}
+
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
/* this function sets the VDD and returns the value set */
static int set_voltage_to_LTC(int i2caddress, int vdd)
{
int ret, vdd_last, vdd_target = vdd;
int count = 100, temp = 0;
+ unsigned char value;
/* Scale up to the LTC resolution is 1/4096V */
vdd = (vdd * 4096) / 1000;
@@ -111,8 +390,52 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */
+#ifndef CONFIG_DM_I2C
+ /* Check write protect state */
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_WRITE_PROTECT, 1,
+ (void *)&value, sizeof(value));
+ if (ret)
+ goto exit;
+
+ if (value != EN_WRITE_ALL_CMD) {
+ value = EN_WRITE_ALL_CMD;
+ ret = i2c_write(I2C_VOL_MONITOR_ADDR,
+ PMBUS_CMD_WRITE_PROTECT, 1,
+ (void *)&value, sizeof(value));
+ if (ret)
+ goto exit;
+ }
+
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+ PMBUS_CMD_PAGE_PLUS_WRITE, 1,
+ (void *)&buff, sizeof(buff));
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret) {
+ /* Check write protect state */
+ ret = dm_i2c_read(dev,
+ PMBUS_CMD_WRITE_PROTECT,
+ (void *)&value, sizeof(value));
+ if (ret)
+ goto exit;
+
+ if (value != EN_WRITE_ALL_CMD) {
+ value = EN_WRITE_ALL_CMD;
+ ret = dm_i2c_write(dev,
+ PMBUS_CMD_WRITE_PROTECT,
+ (void *)&value, sizeof(value));
+ if (ret)
+ goto exit;
+ }
+
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+ (void *)&buff, sizeof(buff));
+ }
+#endif
+exit:
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@@ -131,25 +454,39 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
return vdd_last;
}
+#endif
static int set_voltage(int i2caddress, int vdd)
{
int vdd_last = -1;
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+ vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
vdd_last = set_voltage_to_LTC(i2caddress, vdd);
+#else
+ #error Specific voltage monitor must be defined
+#endif
return vdd_last;
}
+#ifdef CONFIG_FSL_LSCH3
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 fusesr;
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+ u8 vid, buf;
+#else
u8 vid;
+#endif
int vdd_target, vdd_current, vdd_last;
- int ret, i2caddress;
+ int ret, i2caddress = 0;
unsigned long vdd_string_override;
char *vdd_string;
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
static const u16 vdd[32] = {
8250,
7875,
@@ -184,16 +521,129 @@ int adjust_vdd(ulong vdd_override)
0, /* reserved */
0, /* reserved */
};
+#else
+#ifdef CONFIG_ARCH_LS1088A
+ static const uint16_t vdd[32] = {
+ 10250,
+ 9875,
+ 9750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+#else
+ static const uint16_t vdd[32] = {
+ 10500,
+ 0, /* reserved */
+ 9750,
+ 0, /* reserved */
+ 9500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 0, /* reserved */
+ 10250,
+ 0, /* reserved */
+ 10500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+#endif
+#endif
struct vdd_drive {
u8 vid;
unsigned voltage;
};
+
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
debug("VID: I2C failed to switch channel\n");
ret = -1;
goto exit;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+#endif
+
/* get the voltage ID from fuse status register */
fusesr = in_le32(&gur->dcfg_fusesr);
vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
@@ -203,7 +653,6 @@ int adjust_vdd(ulong vdd_override)
FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
}
vdd_target = vdd[vid];
- printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target);
/* check override variable for overriding VDD */
vdd_string = env_get(CONFIG_VID_FLS_ENV);
@@ -246,8 +695,28 @@ int adjust_vdd(ulong vdd_override)
vdd_current = vdd_last;
debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
/* Set the target voltage */
vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
+#else
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+#endif
if (board_adjust_vdd(vdd_target) < 0) {
ret = -1;
goto exit;
@@ -264,16 +733,219 @@ exit:
i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
return ret;
}
+#else /* !CONFIG_FSL_LSCH3 */
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2)
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+ u32 fusesr;
+ u8 vid, buf;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+#endif
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ /*
+ * VID is used according to the table below
+ * ---------------------------------------
+ * | DA_V |
+ * |-------------------------------------|
+ * | 5b00000 | 5b00001-5b11110 | 5b11111 |
+ * ---------------+---------+-----------------+---------|
+ * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
+ * | A |----------+---------+-----------------+---------|
+ * | _ | 5b00001 |VID = | VID = |VID = |
+ * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
+ * | _ | 5b11110 | | | |
+ * | A |----------+---------+-----------------+---------|
+ * | L | 5b11111 | No VID | VID = DA_V | NO VID |
+ * | T | | | | |
+ * ------------------------------------------------------
+ */
+#ifdef CONFIG_FSL_LSCH2
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+ }
+#else
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ }
+#endif
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = env_get(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else {
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+ return ret;
+}
+#endif
static int print_vdd(void)
{
- int vdd_last, ret, i2caddress;
+ int vdd_last, ret, i2caddress = 0;
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
debug("VID : I2c failed to switch channel\n");
return -1;
}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_READ)
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+#endif
+
/*
* Read voltage monitor to check real voltage.
*/
@@ -295,13 +967,15 @@ static int do_vdd_override(cmd_tbl_t *cmdtp,
char * const argv[])
{
ulong override;
-
+ int ret = 0;
if (argc < 2)
return CMD_RET_USAGE;
- if (!strict_strtoul(argv[1], 10, &override))
- adjust_vdd(override); /* the value is checked by callee */
- else
+ if (!strict_strtoul(argv[1], 10, &override)) {
+ ret = adjust_vdd(override); /* the value is checked by callee */
+ if (ret < 0)
+ return CMD_RET_FAILURE;
+ } else
return CMD_RET_USAGE;
return 0;
}
diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
index 99778e9a93..9669e828a0 100644
--- a/board/solidrun/common/vid.h
+++ b/board/solidrun/common/vid.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Copyright 2020 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -18,6 +19,25 @@
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
+
+/* LTC3882 */
+#define PMBUS_CMD_WRITE_PROTECT 0x10
+/*
+ * WRITE_PROTECT command supported values
+ * 0x80: Disable all writes except WRITE_PROTECT, PAGE,
+ * STORE_USER_ALL and MFR_EE_UNLOCK commands.
+ * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
+ * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
+ * Individual faults can also be cleared by writing a 1 to the
+ * respective status bit.
+ * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
+ * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
+ * and VOUT_COMMAND commands. Individual faults can be cleared by
+ * writing a 1 to the respective status bit.
+ * 0x00: Enables write to all commands
+ */
+#define EN_WRITE_ALL_CMD (0)
+
int adjust_vdd(ulong vdd_override);
#endif /* __VID_H_ */
--
2.25.1
patches/u-boot-LSDK-21.08/0015-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch 0 → 100644
View file @ a393e2e7
From 1dee00c3e75cd6ca9060b526ab5cd3eb376363a6 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 3 Feb 2020 14:26:55 +0200
Subject: [PATCH] lx2160a-cex7 : move from lsdk-19.06 to lsdk-19.09
Following is a list of changes -
1. I2C moved to DM model
2. removed emc2301 support
3. synchronized vid.c with NXP's driver. But it is still not functional
in u-boot
4. Added eMMC to distroboot target list
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/fsl-lx2160a-cex7.dts | 14 +
board/solidrun/common/Makefile | 1 -
board/solidrun/common/emc2301.c | 31 --
board/solidrun/common/vid.c | 638 +++++++++++++++++++++++++++++-
board/solidrun/lx2160a/lx2160a.c | 8 +
configs/lx2160acex7_tfa_defconfig | 8 +-
include/configs/lx2160a_common.h | 1 +
7 files changed, 666 insertions(+), 35 deletions(-)
delete mode 100644 board/solidrun/common/emc2301.c
diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
index 4fbcaafb0e..4ca67df25a 100644
--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
+++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
@@ -46,6 +46,20 @@
status = "okay";
};
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+};
+
&sata0 {
status = "okay";
};
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index b0d9f1012e..3713e91351 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -62,7 +62,15 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 3891d2a7c4..89a47adb23 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_TARGET_LX2160ACEX7=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_EMC2301=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -73,3 +72,10 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_DATE=y
+CONFIG_RTC_PCF2127=y
--
2.17.1
patches/u-boot-LSDK-21.08/0016-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch 0 → 100644
View file @ a393e2e7
From d2e368b0df941fe8958df4f44dd2c7cfc32d0fb8 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:53:48 +0200
Subject: [PATCH 16/16] lx2160acex7: pcie fixup and boot from eMMC print
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/lx2160a.c | 66 +++++++++++++++++++++++++++++++
configs/lx2160acex7_tfa_defconfig | 3 +-
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index 3713e91351..b7211a2d5c 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -20,6 +20,8 @@
#include <efi_loader.h>
#include <asm/arch/mmu.h>
#include <hwconfig.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/config.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include "../../freescale/common/vid.h"
@@ -106,6 +108,66 @@ int board_early_init_f(void)
#ifdef CONFIG_OF_BOARD_FIXUP
int board_fix_fdt(void *fdt)
{
+ char *reg_name, *old_str, *new_str;
+ const char *reg_names;
+ int names_len, old_str_len, new_str_len, remaining_str_len;
+ struct str_map {
+ char *old_str;
+ char *new_str;
+ } reg_names_map[] = {
+ { "ccsr", "dbi" },
+ { "pf_ctrl", "ctrl" }
+ };
+ int off = -1, i;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ return 0;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
+ strlen("fsl,ls-pcie") + 1);
+
+ reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
+ if (!reg_names)
+ continue;
+
+ reg_name = (char *)reg_names;
+ remaining_str_len = names_len - (reg_name - reg_names);
+ i = 0;
+ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
+ old_str = reg_names_map[i].old_str;
+ new_str = reg_names_map[i].new_str;
+ old_str_len = strlen(old_str);
+ new_str_len = strlen(new_str);
+ if (memcmp(reg_name, old_str, old_str_len) == 0) {
+ /* first only leave required bytes for new_str
+ * and copy rest of the string after it
+ */
+ memcpy(reg_name + new_str_len,
+ reg_name + old_str_len,
+ remaining_str_len - old_str_len);
+ /* Now copy new_str */
+ memcpy(reg_name, new_str, new_str_len);
+ names_len -= old_str_len;
+ names_len += new_str_len;
+ i++;
+ }
+
+ reg_name = memchr(reg_name, '\0', remaining_str_len);
+ if (!reg_name)
+ break;
+
+ reg_name += 1;
+
+ remaining_str_len = names_len - (reg_name - reg_names);
+ }
+
+ fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie");
+ }
+
return 0;
}
#endif
@@ -135,6 +197,10 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
+ } else {
+ puts("FlexSPI DEV#0\n");
}
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 89a47adb23..2a3441d263 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LX2160ACEX7=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -59,6 +60,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_E1000=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
--
2.17.1
patches/u-boot-LSDK-21.08/0017-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch 0 → 100644
View file @ a393e2e7
From 1ec9f76ce5813ec7f2f825aecf0b9c6a2d8d1cf0 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 15:13:11 +0200
Subject: [PATCH 17/17] lx2160a-cex7: set mmc dev to 0 when attempting
sd_bootcmd
When attempting sd_bootcmd which is the fallback of failed distroboot
then set mmc dev to 0; since distroboot already set that variable to 1.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160acex7.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index 478cd8242f..7116e038a1 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -73,7 +73,7 @@
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0" \
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmcinfo; mmc read $load_addr " \
+ "mmc dev 0; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
--
2.17.1
patches/u-boot-LSDK-21.08/0018-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch 0 → 100644
View file @ a393e2e7
From 341eb7a1e9ce5f7764f39002b96e7975955cac0e Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 4 May 2020 22:52:02 +0300
Subject: [PATCH] lx2160acex7: Misc fixes to support LSDK-20.04
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/Kconfig | 1 +
board/solidrun/lx2160a/lx2160a.c | 4 +++-
configs/lx2160acex7_tfa_defconfig | 24 ++++++++++++------------
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8615e1673f..c78e17a0ed 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1195,6 +1195,7 @@ config TARGET_LX2160ACEX7
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for SolidRun LX2160A based com express type 7 module and
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index b7211a2d5c..975431fd53 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -16,7 +16,7 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <efi_loader.h>
#include <asm/arch/mmu.h>
#include <hwconfig.h>
@@ -26,6 +26,8 @@
#include <asm/arch/soc.h>
#include "../../freescale/common/vid.h"
#include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
#ifdef CONFIG_EMC2301
#include "../common/emc2301.h"
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 2a3441d263..d2e62a6e91 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -1,16 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LX2160ACEX7=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
-CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_BOARD_FIXUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
@@ -29,6 +28,7 @@ CONFIG_CMD_NVME=y
CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -36,6 +36,10 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -55,28 +59,24 @@ CONFIG_CMD_MII=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_EXT2=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_E1000=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
+
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
-CONFIG_SERIAL_PROBE_ALL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
-# CONFIG_SYS_NXP_FSPI_AHB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
-CONFIG_DM_RTC=y
-CONFIG_DM_GPIO=y
CONFIG_CMD_DATE=y
-CONFIG_RTC_PCF2127=y
+CONFIG_GIC_V3_ITS=y
--
2.17.1
patches/u-boot-LSDK-21.08/0019-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch 0 → 100644
View file @ a393e2e7
From 1e1e86ebef25670922c7e1e65d897a4dba9a806f Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 5 May 2020 01:01:01 +0300
Subject: [PATCH] lx2160acex7: misc fixes to get booting from eMMC functional
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160a_common.h | 10 ++++++++++
include/configs/lx2160acex7.h | 14 ++++++++------
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 8983e615d1..d65e5c5cf2 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
"esbc_validate 0x80680000 ;" \
"fsl_mc start mc 0x80a00000 0x80e00000\0"
+#define SD2_MC_INIT_CMD \
+ "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
+ "mmc read 0x80e00000 0x7000 0x800;" \
+ "env exists secureboot && " \
+ "mmc read 0x80640000 0x3200 0x20 && " \
+ "mmc read 0x80680000 0x3400 0x20 && " \
+ "esbc_validate 0x80640000 && " \
+ "esbc_validate 0x80680000 ;" \
+ "fsl_mc start mc 0x80a00000 0x80e00000\0"
+
#define EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index 7116e038a1..310168db47 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -46,11 +46,6 @@
#endif
-/* EMC2301 */
-#define I2C_MUX_CH_EMC2301 0x01
-#define I2C_EMC2301_ADDR 0x2f
-#define I2C_EMC2301_CMD 0x40
-#define I2C_EMC2301_PWM 0x80
/* EEPROM */
#undef CONFIG_ID_EEPROM /* Fixme */
@@ -73,7 +68,14 @@
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0" \
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmc dev 0; mmcinfo; mmc read $load_addr " \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0" \
+ "emmc_bootcmd=echo Trying load from emmc card..;" \
+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
--
2.17.1
patches/u-boot-LSDK-21.08/0020-lx2160a-add-ramdisk_addr_r-for-distro-boot-support.patch 0 → 100644
View file @ a393e2e7
From 19c1a661a69a7b2d6af0867c112e1cf25acd03b6 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 16:17:16 +0200
Subject: [PATCH] lx2160a: add ramdisk_addr_r for distro-boot support
Because ramdisks can be huge, the addresses were reordered by size so
that ramdisk is loaded beyond kernel and fdt:
- 0x81000000: 1MB for DTB
- 0x81100000: 255MB for Kernel
- 0x90000000: open end for ramdisk
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
include/configs/lx2160a_common.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 4a9c28858f..c18b9170ad 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -238,7 +238,8 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
#define EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
- "ramdisk_addr=0x800000\0" \
+ "ramdisk_addr=0x9000000\0" \
+ "ramdisk_addr_r=0x9000000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
@@ -248,10 +249,10 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
- "kernel_addr_r=0x81000000\0" \
+ "kernel_addr_r=0x81100000\0" \
"kernelheader_size=0x40000\0" \
- "fdt_addr_r=0x90000000\0" \
- "fdt_addr=0x90000000\0" \
+ "fdt_addr_r=0x81000000\0" \
+ "fdt_addr=0x81000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernel_addr_sd=0x8000\0" \
--
2.25.1
patches/u-boot-LSDK-21.08/0020-pci-fix-layerscape.patch 0 → 100644
View file @ a393e2e7
From 04f824bd1210fbc6db08560dda9cd14318f859d9 Mon Sep 17 00:00:00 2001
From: Russell King <rmk@armlinux.org.uk>
Date: Tue, 5 May 2020 01:01:01 +0300
Subject: [PATCH] pci: fix layerscape
On the LX2160A rev 1, SVR_SOC_VER() returns 0x873610, and this causes
the wrong PCIe fdt fixup code to be called, resulting in all PCIe
devices remaining disabled in the DT passed to the kernel. Fix this
by detecting the ID and using the correct gen4 layerscape PCIe code.
Signed-off-by: Russell King <rmk@armlinux.org.uk>
---
drivers/pci/pcie_layerscape_fixup_common.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
index b6179798b3..0327930ddb 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -18,8 +18,9 @@ void ft_pci_setup(void *blob, bd_t *bd)
uint svr;
svr = SVR_SOC_VER(get_svr());
-
- if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
+ /* Rev 1 LX2160A have svr = 0x873610 */
+ if ((svr == SVR_LX2160A || svr == (SVR_LX2160A | 0x10)) &&
+ IS_SVR_REV(get_svr(), 1, 0))
ft_pci_setup_ls_gen4(blob, bd);
else
#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
patches/u-boot-LSDK-21.08/0021-lx2160acex7-add-poweroff-and-disable-fan-full-speed.patch 0 → 100644
View file @ a393e2e7
From 37c0a6113967619af24d58c3730afcf57f3bfbad Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 17 Jan 2021 17:14:06 +0200
Subject: [PATCH] lx2160acex7: add poweroff and disable fan full speed
1. Add poweroff command; when using Clearfog CX or HoneyComb carrier
boards, the S5# signal is connected to the power button controller that
cuts off the '12v' supply from the COM module.
2. In board_fix_fdt, just before booting the kernel the fan full speed
signal becomes inactive so that the kernel AMC6821 driver would take
over and enable the auto thermal and pwm adjustments.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
board/solidrun/lx2160a/lx2160a.c | 8 +++++++-
configs/lx2160acex7_tfa_defconfig | 2 +-
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index dc740c999d..ab6297dae2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -65,6 +65,9 @@
#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
#endif
+#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01320000)
+#define GPIO3_GPDIR_ADDR (GPIO3_BASE_ADDR + 0x0)
+#define GPIO3_GPDAT_ADDR (GPIO3_BASE_ADDR + 0x8)
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index 975431fd53..0148ce2a48 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -358,7 +358,13 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
#endif
-
+ printf ("Releasing fan controller full speed gpio\n");
+ /*
+ * Set the GPIO to be input; the on-COM pullup will disable the full speed
+ * signal.
+ */
+ out_le32(GPIO3_GPDIR_ADDR, (~(1 << 29) &
+ in_le32(GPIO3_GPDIR_ADDR)));
return 0;
}
#endif
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 8e96265843..837d6070dd 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -68,7 +68,7 @@ CONFIG_PHY_ATHEROS=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-
+CONFIG_CMD_POWEROFF=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
--
2.25.1
patches/u-boot-LSDK-21.08/0022-lx2160acex7-drop-ramdisk-from-default-bootargs.patch 0 → 100644
View file @ a393e2e7
From b145ea98fe987b7955d11e7f2352b657ed14498f Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Wed, 22 Jul 2020 15:35:30 +0200
Subject: [PATCH] lx2160acex7: drop ramdisk from default bootargs
root=/dev/ram0 along with ramdisk_size are deployment-specific and
actually prevent booting a generic distro-boot enabled system that only
extends rather than override firmware-defined bootargs.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
configs/lx2160acex7_tfa_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 837d6070dd..97d3877047 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -13,7 +13,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
--
2.27.0
patches/u-boot-LSDK-21.08/0023-lx2160acex7-add-25Gbps-TI-retimer-configuration.patch 0 → 100644
View file @ a393e2e7
From ae9bf5e00231fb5957e81f1e16289a9eae707f03 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 19:24:35 +0200
Subject: [PATCH] lx2160acex7: add 25Gbps TI retimer configuration
ClearFog CX revision 1.3 and newer adds two TI 4 channels retimers on
egress and ingress.
On egress the retimer is configured to be on I2C address 0x22 and the
other on I2C address 0x23.
This patch configures the egress retimer pre and post key and the
amplitude.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 110 +++++++++++++++++------
include/configs/lx2160acex7.h | 2 +-
2 files changed, 85 insertions(+), 27 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 97e414838f..f335b4207a 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -12,6 +12,7 @@
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <i2c.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
@@ -20,6 +21,65 @@
DECLARE_GLOBAL_DATA_PTR;
+int select_i2c_ch_pca9547(u8 ch);
+
+void setup_retimer_25g(int chnum)
+{
+ int i, ret;
+ u8 reg;
+ struct udevice *dev;
+
+ select_i2c_ch_pca9547(0xb); /* SMB_CLK / DATA interface */
+ /*
+ * Assumption is that LX2 TX --> RT1 RX is at 0x22 and
+ * RT2 TX --> LX2 RX is at 0x23.
+ */
+ ret = i2c_get_chip_for_busnum(0, 0x23, 1, &dev);
+ if (ret) {
+ /*
+ * On HoneyComb and ClearFog CX ver 1.1 / 1.2 there is no retimer
+ * assembled; silently return.
+ */
+ return;
+ }
+ ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
+ if (ret) {
+ printf ("ERROR: Could not get retimer device ID\n");
+ return;
+ }
+ if (reg != 0x10) {
+ printf ("ERROR : DS250DF410 retimer not found\n");
+ return;
+ }
+ printf ("Found retimer... Setting up channels 0..%d as 25Gbps\n",chnum - 1);
+ dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
+ /*
+ * Setup 25Gbps channel on 0..chnum.
+ * Notice that the ingress retimer is mirrorly mapped with the SERDES
+ * number, so SERDES #0 is connected to channel #3, SERDES 1 to channel
+ * #2 ...
+ */
+ for (i = 0 ; i < chnum; i++) { /* Setup channels 0..chnum as 25g */
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+
+ printf ("Setting main cursor to 0xf\n");
+ dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
+ dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
+ if (i == 0)
+ /* Set post-cursor of channel #0 to -4 */
+ dm_i2c_reg_write(dev, 0x3f, 0x44);
+ else
+ /* Set all other channels pre-cursor to -1 */
+ dm_i2c_reg_write(dev, 0x3f, 0x41);
+ printf ("Releasing CDR\n");
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+
+ /* TODO: Setup other channels as 10Gbps */
+}
+
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
@@ -45,35 +105,33 @@ int board_eth_init(bd_t *bis)
RGMII_PHY_ADDR1);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
switch (srds_s1) {
- case 3:
- case 5:
- case 8:
- case 13:
- case 14:
- case 15:
- case 17:
- case 20:
- case 23:
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- break;
-
- default:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 17:
+ case 21:
+ /* Setup 25gb retimer on lanes e,f,g,h */
+ setup_retimer_25g(4);
+ break;
+ case 18:
+ case 19:
+ /* Setup 25gb retimer on lanes e,f and 10g on g,h */
+ setup_retimer_25g(2);
+ break;
+
+ default:
printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
srds_s1);
- goto next;
}
- for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ interface = wriop_get_enet_if(WRIOP1_DPMAC17);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(WRIOP1_DPMAC17, dev);
}
next:
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index 310168db47..de075eaeaa 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -11,7 +11,7 @@
/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
/* VID */
-#define I2C_MUX_CH_VOL_MONITOR 0x2
+#define I2C_MUX_CH_VOL_MONITOR 0xa /* Channel 2 */
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x5c
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
--
2.25.1
patches/u-boot-LSDK-21.08/0024-lx2160acex7-refine-pre-cursor-of-all-channels-to-4.patch 0 → 100644
View file @ a393e2e7
From 0d832fe197168612c6c150e220b85fd907049cb4 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 3 Nov 2020 15:37:45 +0200
Subject: [PATCH 24/24] lx2160acex7: refine pre-cursor of all channels to -4
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index f335b420..968190f1 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -63,17 +63,10 @@ void setup_retimer_25g(int chnum)
dm_i2c_reg_write(dev, 0xfc, 1 << i);
dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
-
- printf ("Setting main cursor to 0xf\n");
dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
- if (i == 0)
- /* Set post-cursor of channel #0 to -4 */
- dm_i2c_reg_write(dev, 0x3f, 0x44);
- else
- /* Set all other channels pre-cursor to -1 */
- dm_i2c_reg_write(dev, 0x3f, 0x41);
- printf ("Releasing CDR\n");
+ /* Set post-cursor of channel #0 to -4 */
+ dm_i2c_reg_write(dev, 0x3f, 0x44);
dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
}
--
2.25.1
patches/u-boot-LSDK-21.08/0026-lx2160acex7-add-sys_eeprom-support-and-read-MAC-addr.patch 0 → 100644
View file @ a393e2e7
From 05f7b0ddb485d587ee3638105a2b0536abc1eff0 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Thu, 17 Dec 2020 17:55:19 +0200
Subject: [PATCH] lx2160acex7: add sys_eeprom support and read MAC addresses
from it
1. Add eeprom on I2C0 - MUX (0x77) - I2C0 - EEPROM at 0x57 (2Kbit
eeprom)
2. After storing first TLV formatted data sys_eeprom will use that
eeprom
3. For now the DPMAC17 (1Gbps from the COM) is set as last DPMAC for
registration, which means it will get the MAC register in sys_eeprom + 8
in the case of SD1 protocol=8. We will modify that in the future the
DPMAC17 will be registered first so it would get the sys_eeprom base MAC
first.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/fsl-lx2160a-cex7.dts | 61 ++++++++++++++++++++++++
board/solidrun/lx2160a/eth_lx2160acex7.c | 6 +--
configs/lx2160acex7_tfa_defconfig | 7 +++
include/configs/lx2160acex7.h | 8 +---
4 files changed, 72 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
index 4ca67df2..04adbcf6 100644
--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
+++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
@@ -49,6 +49,67 @@
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+/* The following eeprin is reserved so that the 2Kb eeprom at address 0x57
+ would be used as TLV eeprom.
+ 24aa512@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+*/
+ spd1@51 {
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+ spd2@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ ltc3882@5c {
+ compatible = "ltc3882";
+ reg = <0x5c>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@48 {
+ compatible = "nxp,sa56004";
+ reg = <0x48>;
+ };
+ };
+ };
};
&i2c4 {
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 968190f1..f286f72e 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -13,11 +13,13 @@
#include <phy.h>
#include <fm_eth.h>
#include <i2c.h>
+#include <sys_eeprom.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
+#include <fsl-mc/fsl_mc_private.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -127,7 +129,7 @@ int board_eth_init(bd_t *bis)
wriop_set_mdio(WRIOP1_DPMAC17, dev);
}
-next:
+ mac_read_from_eeprom();
cpu_eth_init(bis);
#endif /* CONFIG_FSL_MC_ENET */
@@ -145,9 +147,7 @@ void reset_phy(void)
int fdt_fixup_board_phy(void *fdt)
{
- int mdio_offset;
int ret;
- struct mii_dev *dev;
ret = 0;
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 97d38770..62ff236e 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -38,8 +38,12 @@ CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_MISC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_EEPROM=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -59,6 +63,7 @@ CONFIG_CMD_MII=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_SYS_EEPROM=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
@@ -81,3 +86,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_MEMTEST=y
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index de075eae..9ba73fc0 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -48,13 +48,7 @@
/* EEPROM */
-#undef CONFIG_ID_EEPROM /* Fixme */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#undef CONFIG_ID_EEPROM /* We use TLV with I2C DM */
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
--
2.25.1
patches/u-boot-LSDK-21.08/0028-lx2160acex7-add-mtest-start-and-end-addresses.patch 0 → 100644
View file @ a393e2e7
From 4d76da48691cf5d87fff2626065978617c629fbb Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 20 Dec 2020 16:06:26 +0200
Subject: [PATCH 28/28] lx2160acex7: add mtest start and end addresses
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160acex7.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index 9ba73fc0..d2ef78a2 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -77,5 +77,7 @@
"bootm $load_addr#$BOARD\0"
#include <asm/fsl_secure_boot.h>
+#define CONFIG_SYS_MEMTEST_START 0x2080000000
+#define CONFIG_SYS_MEMTEST_END 0x2400000000
#endif /* __LX2_CEX7_H */
--
2.25.1
patches/u-boot-LSDK-21.08/0029-lx2160acex7-add-10Gbps-retimer-configuration.patch 0 → 100644
View file @ a393e2e7
From abc79c9532750adfc37f3869bf0c17a2e665df41 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 30 Dec 2020 19:52:00 +0200
Subject: [PATCH 29/29] lx2160acex7: add 10Gbps retimer configuration
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 47 ++++++++++++++++++++++--
1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index f286f72e..a754d3fd 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -53,7 +53,11 @@ void setup_retimer_25g(int chnum)
printf ("ERROR : DS250DF410 retimer not found\n");
return;
}
- printf ("Found retimer... Setting up channels 0..%d as 25Gbps\n",chnum - 1);
+ if (chnum > 0)
+ printf ("Setting up retimer channels 1..%d as 25Gbps\n",chnum);
+ if (chnum < 4)
+ printf ("Setting up retimer channels %d..4 as 10Gbps\n",chnum+1);
+
dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
/*
* Setup 25Gbps channel on 0..chnum.
@@ -71,8 +75,42 @@ void setup_retimer_25g(int chnum)
dm_i2c_reg_write(dev, 0x3f, 0x44);
dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
}
-
- /* TODO: Setup other channels as 10Gbps */
+ if (chnum < 4) {
+ /* Setup the rest of the channels as 10g */
+ for (i = chnum ; i < 4; i++) {
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+ dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
+ dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
+ /* Set post-cursor of channel #0 to -4 */
+ dm_i2c_reg_write(dev, 0x3f, 0x44);
+ dm_i2c_reg_write(dev, 0x2f, 0x04); /* Set rate to 10.3125 Gbps */
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+ ret = i2c_get_chip_for_busnum(0, 0x22, 1, &dev);
+ if (ret) {
+ printf ("ERROR: Retimer at address 0x22 not found\n");
+ return;
+ }
+ ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
+ if (ret) {
+ printf ("ERROR: Could not get retimer device ID\n");
+ return;
+ }
+ if (reg != 0x10) {
+ printf ("ERROR : DS250DF410 retimer not found\n");
+ return;
+ }
+ dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
+ for (i = chnum ; i < 4; i++) {
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+ dm_i2c_reg_write(dev, 0x2f, 0x04); /* Set rate to 10.3125 Gbps */
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+ }
}
int board_eth_init(bd_t *bis)
@@ -100,6 +138,9 @@ int board_eth_init(bd_t *bis)
RGMII_PHY_ADDR1);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
switch (srds_s1) {
+ case 8:
+ setup_retimer_25g(0);
+ break;
case 13:
case 14:
case 15:
--
2.25.1
patches/u-boot-LSDK-21.08/0030-lx2160acex7-add-support-for-LSDK-20.12-and-it-s-newe.patch 0 → 100644
View file @ a393e2e7
From d75709426d141ee7e8fd8c38eddc420676c75f49 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 17 Jan 2021 17:25:25 +0200
Subject: [PATCH] lx2160acex7: add support for LSDK-20.12 and it's newer u-boot
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 2 +-
board/solidrun/lx2160a/lx2160a.c | 7 ++++---
configs/lx2160acex7_tfa_defconfig | 16 +++++++++++++++-
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index a754d3fd63..211de59971 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -13,7 +13,7 @@
#include <phy.h>
#include <fm_eth.h>
#include <i2c.h>
-#include <sys_eeprom.h>
+#include <tlv_eeprom.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index 0148ce2a48..8f9251c294 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 SolidRun ltd.
+ * Copyright 2019-2021 SolidRun ltd.
*/
#include <common.h>
+#include <clock_legacy.h>
#include <dm.h>
#include <dm/platform_data/serial_pl01x.h>
#include <i2c.h>
@@ -252,8 +253,8 @@ void detail_board_ddr_info(void)
print_ddr_info(0);
}
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
{
config_board_mux();
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 62ff236e71..8c2a6b338b 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -3,6 +3,9 @@ CONFIG_TARGET_LX2160ACEX7=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x500000
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -15,6 +18,7 @@ CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
@@ -23,6 +27,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y
@@ -32,6 +37,7 @@ CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@@ -63,7 +69,7 @@ CONFIG_CMD_MII=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_EXT2=y
-CONFIG_CMD_SYS_EEPROM=y
+CONFIG_CMD_TLV_EEPROM=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
@@ -83,8 +89,16 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y
CONFIG_CMD_MEMORY=y
CONFIG_CMD_MEMTEST=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_TA_AVB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_CMD_OPTEE_RPMB=y
--
2.25.1
patches/u-boot-LSDK-21.08/0031-lx2160a-modify-SVR_WO_E-mask.patch 0 → 100644
View file @ a393e2e7
From e4ad857ceb0d05568473b63c501fa9d567e1c47c Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 24 Jan 2021 12:26:56 +0200
Subject: [PATCH] lx2160a: modify SVR_WO_E mask
In LX2120A bit 12 of the SVR (bit 4 when 8 bit shifter right) is the
indicatation of FD/CAN support. This patch fixes the detection issue for
LX2 family of SoCs but unfortunately it breaks other layerscape devices.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 10359ec9ac..3c5a0f687b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -77,7 +77,7 @@ enum boot_src {
enum boot_src get_boot_src(void);
#endif
#endif
-#define SVR_WO_E 0xFFFFFE
+#define SVR_WO_E 0xFFFFEE
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
--
2.25.1
patches/u-boot-LSDK-21.08/0032-lx2160acex7-add-secureboot-defconfig.patch 0 → 100644
View file @ a393e2e7
From dd85c69ddd44f059092b7ba7aed54fadbfc87e7b Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 24 Jan 2021 12:30:17 +0200
Subject: [PATCH] lx2160acex7: add secureboot defconfig
This adds secureboot configuration to u-boot; but still without esbc
validate function.
i.e. the chain of trust boot is still not full supported
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
configs/lx2160acex7_tfa_SECURE_BOOT_defconfig | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
diff --git a/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000..59298de9ac
--- /dev/null
+++ b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ACEX7=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_NXP_ESBC=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+# Uncomment the following to remove the countdown
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NVME=y
+CONFIG_NVME=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_EEPROM=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MICRON=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_TLV_EEPROM=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_CMD_DATE=y
+CONFIG_RTC_PCF2127=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_GIC_V3_ITS=y
--
2.25.1
patches/u-boot-LSDK-21.08/0033-lx2160acex7-soft-link-to-freescale-common-vid-instea.patch 0 → 100644
View file @ a393e2e7
From 45398b8e48c202fe0b316059ee2c9183122b2199 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 15:59:07 +0200
Subject: [PATCH] lx2160acex7: soft link to freescale common vid instead of
copying
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/common/vid.c | 1005 +----------------------------------
board/solidrun/common/vid.h | 44 +-
2 files changed, 2 insertions(+), 1047 deletions(-)
mode change 100644 => 120000 board/solidrun/common/vid.c
mode change 100644 => 120000 board/solidrun/common/vid.h
diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
deleted file mode 100644
index 0256d035eb..0000000000
--- a/board/solidrun/common/vid.c
+++ /dev/null
@@ -1,1004 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <i2c.h>
-#include <irq_func.h>
-#include <asm/io.h>
-#ifdef CONFIG_FSL_LSCH2
-#include <asm/arch/immap_lsch2.h>
-#elif defined(CONFIG_FSL_LSCH3)
-#include <asm/arch/immap_lsch3.h>
-#else
-#include <asm/immap_85xx.h>
-#endif
-#include "vid.h"
-
-int __weak i2c_multiplexer_select_vid_channel(u8 channel)
-{
- return 0;
-}
-
-/*
- * Compensate for a board specific voltage drop between regulator and SoC
- * return a value in mV
- */
-int __weak board_vdd_drop_compensation(void)
-{
- return 0;
-}
-
-/*
- * Board specific settings for specific voltage value
- */
-int __weak board_adjust_vdd(int vdd)
-{
- return 0;
-}
-
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
-/*
- * Get the i2c address configuration for the IR regulator chip
- *
- * There are some variance in the RDB HW regarding the I2C address configuration
- * for the IR regulator chip, which is likely a problem of external resistor
- * accuracy. So we just check each address in a hopefully non-intrusive mode
- * and use the first one that seems to work
- *
- * The IR chip can show up under the following addresses:
- * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
- * 0x09 (Verified on T1040RDB-PA)
- * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
- */
-static int find_ir_chip_on_i2c(void)
-{
- int i2caddress;
- int ret;
- u8 byte;
- int i;
- const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-#endif
-
- /* Check all the address */
- for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
- i2caddress = ir_i2c_addr[i];
-#ifndef CONFIG_DM_I2C
- ret = i2c_read(i2caddress,
- IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
- sizeof(byte));
-#else
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
- (void *)&byte, sizeof(byte));
-#endif
- if ((ret >= 0) && (byte == IR36021_MFR_ID))
- return i2caddress;
- }
- return -1;
-}
-#endif
-
-/* Maximum loop count waiting for new voltage to take effect */
-#define MAX_LOOP_WAIT_NEW_VOL 100
-/* Maximum loop count waiting for the voltage to be stable */
-#define MAX_LOOP_WAIT_VOL_STABLE 100
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for WAIT_FOR_ADC before
- * another reading
- */
-#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
-
-/* If an INA220 chip is available, we can use it to read back the voltage
- * as it may have a higher accuracy than the IR chip for the same purpose
- */
-#ifdef CONFIG_VOL_MONITOR_INA220
-#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
-#define ADC_MIN_ACCURACY 4
-#else
-#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
-#define ADC_MIN_ACCURACY 4
-#endif
-
-#ifdef CONFIG_VOL_MONITOR_INA220
-static int read_voltage_from_INA220(int i2caddress)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
- u8 buf[2];
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-#endif
-
- for (i = 0; i < NUM_READINGS; i++) {
-#ifndef CONFIG_DM_I2C
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
- (void *)&buf, 2);
-#else
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
- (void *)&buf, 2);
-#endif
- if (ret) {
- printf("VID: failed to read core voltage\n");
- return ret;
- }
- vol_mon = (buf[0] << 8) | buf[1];
- if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%04x\n", vol_mon);
- /* LSB = 4mv */
- voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
- udelay(WAIT_FOR_ADC);
- }
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- return voltage_read;
-}
-#endif
-
-/* read voltage from IR */
-#ifdef CONFIG_VOL_MONITOR_IR36021_READ
-static int read_voltage_from_IR(int i2caddress)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
- u8 buf;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-#endif
-
- for (i = 0; i < NUM_READINGS; i++) {
-#ifndef CONFIG_DM_I2C
- ret = i2c_read(i2caddress,
- IR36021_LOOP1_VOUT_OFFSET,
- 1, (void *)&buf, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
- (void *)&buf, 1);
-#endif
- if (ret) {
- printf("VID: failed to read vcpu\n");
- return ret;
- }
- vol_mon = buf;
- if (!vol_mon) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%02x\n", vol_mon);
- /* Resolution is 1/128V. We scale up here to get 1/128mV
- * and divide at the end
- */
- voltage_read += vol_mon * 1000;
- udelay(WAIT_FOR_ADC);
- }
- /* Scale down to the real mV as IR resolution is 1/128V, rounding up */
- voltage_read = DIV_ROUND_UP(voltage_read, 128);
-
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- /* Compensate for a board specific voltage drop between regulator and
- * SoC before converting into an IR VID value
- */
- voltage_read -= board_vdd_drop_compensation();
-
- return voltage_read;
-}
-#endif
-
-#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
-/* read the current value of the LTC Regulator Voltage */
-static int read_voltage_from_LTC(int i2caddress)
-{
- int ret, vcode = 0;
- u8 chan = PWM_CHANNEL0;
-
-#ifndef CONFIG_DM_I2C
- /* select the PAGE 0 using PMBus commands PAGE for VDD*/
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_PAGE, 1, &chan, 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret)
- ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
-#endif
- if (ret) {
- printf("VID: failed to select VDD Page 0\n");
- return ret;
- }
-
-#ifndef CONFIG_DM_I2C
- /*read the output voltage using PMBus command READ_VOUT*/
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
-#else
- ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
- if (ret) {
- printf("VID: failed to read the volatge\n");
- return ret;
- }
-#endif
- if (ret) {
- printf("VID: failed to read the volatge\n");
- return ret;
- }
-
- /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
- vcode = DIV_ROUND_UP(vcode * 1000, 4096);
-
- return vcode;
-}
-#endif
-
-static int read_voltage(int i2caddress)
-{
- int voltage_read;
-#ifdef CONFIG_VOL_MONITOR_INA220
- voltage_read = read_voltage_from_INA220(i2caddress);
-#elif defined CONFIG_VOL_MONITOR_IR36021_READ
- voltage_read = read_voltage_from_IR(i2caddress);
-#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
- voltage_read = read_voltage_from_LTC(i2caddress);
-#else
- return -1;
-#endif
- return voltage_read;
-}
-
-#ifdef CONFIG_VOL_MONITOR_IR36021_SET
-/*
- * We need to calculate how long before the voltage stops to drop
- * or increase. It returns with the loop count. Each loop takes
- * several readings (WAIT_FOR_ADC)
- */
-static int wait_for_new_voltage(int vdd, int i2caddress)
-{
- int timeout, vdd_current;
-
- vdd_current = read_voltage(i2caddress);
- /* wait until voltage starts to reach the target. Voltage slew
- * rates by typical regulators will always lead to stable readings
- * within each fairly long ADC interval in comparison to the
- * intended voltage delta change until the target voltage is
- * reached. The fairly small voltage delta change to any target
- * VID voltage also means that this function will always complete
- * within few iterations. If the timeout was ever reached, it would
- * point to a serious failure in the regulator system.
- */
- for (timeout = 0;
- abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
- timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
- vdd_current = read_voltage(i2caddress);
- }
- if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
- printf("VID: Voltage adjustment timeout\n");
- return -1;
- }
- return timeout;
-}
-
-/*
- * this function keeps reading the voltage until it is stable or until the
- * timeout expires
- */
-static int wait_for_voltage_stable(int i2caddress)
-{
- int timeout, vdd_current, vdd;
-
- vdd = read_voltage(i2caddress);
- udelay(NUM_READINGS * WAIT_FOR_ADC);
-
- /* wait until voltage is stable */
- vdd_current = read_voltage(i2caddress);
- /* The maximum timeout is
- * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
- */
- for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
- abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
- timeout > 0; timeout--) {
- vdd = vdd_current;
- udelay(NUM_READINGS * WAIT_FOR_ADC);
- vdd_current = read_voltage(i2caddress);
- }
- if (timeout == 0)
- return -1;
- return vdd_current;
-}
-
-/* Set the voltage to the IR chip */
-static int set_voltage_to_IR(int i2caddress, int vdd)
-{
- int wait, vdd_last;
- int ret;
- u8 vid;
-
- /* Compensate for a board specific voltage drop between regulator and
- * SoC before converting into an IR VID value
- */
- vdd += board_vdd_drop_compensation();
-#ifdef CONFIG_FSL_LSCH2
- vid = DIV_ROUND_UP(vdd - 265, 5);
-#else
- vid = DIV_ROUND_UP(vdd - 245, 5);
-#endif
-
-#ifndef CONFIG_DM_I2C
- ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
- 1, (void *)&vid, sizeof(vid));
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
- (void *)&vid, sizeof(vid));
-
-#endif
- if (ret) {
- printf("VID: failed to write VID\n");
- return -1;
- }
- wait = wait_for_new_voltage(vdd, i2caddress);
- if (wait < 0)
- return -1;
- debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
-
- vdd_last = wait_for_voltage_stable(i2caddress);
- if (vdd_last < 0)
- return -1;
- debug("VID: Current voltage is %d mV\n", vdd_last);
- return vdd_last;
-}
-
-#endif
-
-#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
-/* this function sets the VDD and returns the value set */
-static int set_voltage_to_LTC(int i2caddress, int vdd)
-{
- int ret, vdd_last, vdd_target = vdd;
- int count = 100, temp = 0;
- unsigned char value;
-
- /* Scale up to the LTC resolution is 1/4096V */
- vdd = (vdd * 4096) / 1000;
-
- /* 5-byte buffer which needs to be sent following the
- * PMBus command PAGE_PLUS_WRITE.
- */
- u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
- vdd & 0xFF, (vdd & 0xFF00) >> 8};
-
- /* Write the desired voltage code to the regulator */
-#ifndef CONFIG_DM_I2C
- /* Check write protect state */
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_WRITE_PROTECT, 1,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
-
- if (value != EN_WRITE_ALL_CMD) {
- value = EN_WRITE_ALL_CMD;
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_WRITE_PROTECT, 1,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
- }
-
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_PAGE_PLUS_WRITE, 1,
- (void *)&buff, sizeof(buff));
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret) {
- /* Check write protect state */
- ret = dm_i2c_read(dev,
- PMBUS_CMD_WRITE_PROTECT,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
-
- if (value != EN_WRITE_ALL_CMD) {
- value = EN_WRITE_ALL_CMD;
- ret = dm_i2c_write(dev,
- PMBUS_CMD_WRITE_PROTECT,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
- }
-
- ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
- (void *)&buff, sizeof(buff));
- }
-#endif
-exit:
- if (ret) {
- printf("VID: I2C failed to write to the volatge regulator\n");
- return -1;
- }
-
- /* Wait for the volatge to get to the desired value */
- do {
- vdd_last = read_voltage_from_LTC(i2caddress);
- if (vdd_last < 0) {
- printf("VID: Couldn't read sensor abort VID adjust\n");
- return -1;
- }
- count--;
- temp = vdd_last - vdd_target;
- } while ((abs(temp) > 2) && (count > 0));
-
- return vdd_last;
-}
-#endif
-
-static int set_voltage(int i2caddress, int vdd)
-{
- int vdd_last = -1;
-
-#ifdef CONFIG_VOL_MONITOR_IR36021_SET
- vdd_last = set_voltage_to_IR(i2caddress, vdd);
-#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
- vdd_last = set_voltage_to_LTC(i2caddress, vdd);
-#else
- #error Specific voltage monitor must be defined
-#endif
- return vdd_last;
-}
-
-#ifdef CONFIG_FSL_LSCH3
-int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 fusesr;
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
- u8 vid, buf;
-#else
- u8 vid;
-#endif
- int vdd_target, vdd_current, vdd_last;
- int ret, i2caddress = 0;
- unsigned long vdd_string_override;
- char *vdd_string;
-#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
- static const u16 vdd[32] = {
- 8250,
- 7875,
- 7750,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 8000,
- 8125,
- 8250,
- 0, /* reserved */
- 8500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-#else
-#ifdef CONFIG_ARCH_LS1088A
- static const uint16_t vdd[32] = {
- 10250,
- 9875,
- 9750,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 9000,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-
-#else
- static const uint16_t vdd[32] = {
- 10500,
- 0, /* reserved */
- 9750,
- 0, /* reserved */
- 9500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 9000, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 10000, /* 1.0000V */
- 0, /* reserved */
- 10250,
- 0, /* reserved */
- 10500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-#endif
-#endif
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- debug("VID: I2C failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
- ret = find_ir_chip_on_i2c();
- if (ret < 0) {
- printf("VID: Could not find voltage regulator on I2C.\n");
- ret = -1;
- goto exit;
- } else {
- i2caddress = ret;
- debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
- }
-
- /* check IR chip work on Intel mode*/
-#ifndef CONFIG_DM_I2C
- ret = i2c_read(i2caddress,
- IR36021_INTEL_MODE_OOFSET,
- 1, (void *)&buf, 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
- (void *)&buf, 1);
-#endif
- if (ret) {
- printf("VID: failed to read IR chip mode.\n");
- ret = -1;
- goto exit;
- }
-
- if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
- printf("VID: IR Chip is not used in Intel mode.\n");
- ret = -1;
- goto exit;
- }
-#endif
-
- /* get the voltage ID from fuse status register */
- fusesr = in_le32(&gur->dcfg_fusesr);
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
- }
- vdd_target = vdd[vid];
-
- /* check override variable for overriding VDD */
- vdd_string = env_get(CONFIG_VID_FLS_ENV);
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
-
- if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
-
- /* divide and round up by 10 to get a value in mV */
- vdd_target = DIV_ROUND_UP(vdd_target, 10);
- if (vdd_target == 0) {
- debug("VID: VID not used\n");
- ret = 0;
- goto exit;
- } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
- /* Check vdd_target is in valid range */
- printf("VID: Target VID %d mV is not in range.\n",
- vdd_target);
- ret = -1;
- goto exit;
- } else {
- debug("VID: vid = %d mV\n", vdd_target);
- }
-
- /*
- * Read voltage monitor to check real voltage.
- */
- vdd_last = read_voltage(i2caddress);
- if (vdd_last < 0) {
- printf("VID: Couldn't read sensor abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
- vdd_current = vdd_last;
- debug("VID: Core voltage is currently at %d mV\n", vdd_last);
-
-#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
- /* Set the target voltage */
- vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
-#else
- /*
- * Adjust voltage to at or one step above target.
- * As measurements are less precise than setting the values
- * we may run through dummy steps that cancel each other
- * when stepping up and then down.
- */
- while (vdd_last > 0 &&
- vdd_last < vdd_target) {
- vdd_current += IR_VDD_STEP_UP;
- vdd_last = set_voltage(i2caddress, vdd_current);
- }
- while (vdd_last > 0 &&
- vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
- vdd_current -= IR_VDD_STEP_DOWN;
- vdd_last = set_voltage(i2caddress, vdd_current);
- }
-
-#endif
- if (board_adjust_vdd(vdd_target) < 0) {
- ret = -1;
- goto exit;
- }
-
- if (vdd_last > 0)
- printf("VID: Core voltage after adjustment is at %d mV\n",
- vdd_last);
- else
- ret = -1;
-exit:
- if (re_enable)
- enable_interrupts();
- i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
- return ret;
-}
-#else /* !CONFIG_FSL_LSCH3 */
-int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2)
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#else
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
- u32 fusesr;
- u8 vid, buf;
- int vdd_target, vdd_current, vdd_last;
- int ret, i2caddress;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- debug("VID: I2C failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
- ret = find_ir_chip_on_i2c();
- if (ret < 0) {
- printf("VID: Could not find voltage regulator on I2C.\n");
- ret = -1;
- goto exit;
- } else {
- i2caddress = ret;
- debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
- }
-
- /* check IR chip work on Intel mode*/
-#ifndef CONFIG_DM_I2C
- ret = i2c_read(i2caddress,
- IR36021_INTEL_MODE_OOFSET,
- 1, (void *)&buf, 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
- (void *)&buf, 1);
-#endif
- if (ret) {
- printf("VID: failed to read IR chip mode.\n");
- ret = -1;
- goto exit;
- }
- if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
- printf("VID: IR Chip is not used in Intel mode.\n");
- ret = -1;
- goto exit;
- }
-#endif
-
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- /*
- * VID is used according to the table below
- * ---------------------------------------
- * | DA_V |
- * |-------------------------------------|
- * | 5b00000 | 5b00001-5b11110 | 5b11111 |
- * ---------------+---------+-----------------+---------|
- * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
- * | A |----------+---------+-----------------+---------|
- * | _ | 5b00001 |VID = | VID = |VID = |
- * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
- * | _ | 5b11110 | | | |
- * | A |----------+---------+-----------------+---------|
- * | L | 5b11111 | No VID | VID = DA_V | NO VID |
- * | T | | | | |
- * ------------------------------------------------------
- */
-#ifdef CONFIG_FSL_LSCH2
- vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
- }
-#else
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- }
-#endif
- vdd_target = vdd[vid];
-
- /* check override variable for overriding VDD */
- vdd_string = env_get(CONFIG_VID_FLS_ENV);
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
- if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
- if (vdd_target == 0) {
- debug("VID: VID not used\n");
- ret = 0;
- goto exit;
- } else {
- /* divide and round up by 10 to get a value in mV */
- vdd_target = DIV_ROUND_UP(vdd_target, 10);
- debug("VID: vid = %d mV\n", vdd_target);
- }
-
- /*
- * Read voltage monitor to check real voltage.
- */
- vdd_last = read_voltage(i2caddress);
- if (vdd_last < 0) {
- printf("VID: Couldn't read sensor abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
- vdd_current = vdd_last;
- debug("VID: Core voltage is currently at %d mV\n", vdd_last);
- /*
- * Adjust voltage to at or one step above target.
- * As measurements are less precise than setting the values
- * we may run through dummy steps that cancel each other
- * when stepping up and then down.
- */
- while (vdd_last > 0 &&
- vdd_last < vdd_target) {
- vdd_current += IR_VDD_STEP_UP;
- vdd_last = set_voltage(i2caddress, vdd_current);
- }
- while (vdd_last > 0 &&
- vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
- vdd_current -= IR_VDD_STEP_DOWN;
- vdd_last = set_voltage(i2caddress, vdd_current);
- }
-
- if (vdd_last > 0)
- printf("VID: Core voltage after adjustment is at %d mV\n",
- vdd_last);
- else
- ret = -1;
-exit:
- if (re_enable)
- enable_interrupts();
-
- i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
-
- return ret;
-}
-#endif
-
-static int print_vdd(void)
-{
- int vdd_last, ret, i2caddress = 0;
-
- ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- debug("VID : I2c failed to switch channel\n");
- return -1;
- }
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
- ret = find_ir_chip_on_i2c();
- if (ret < 0) {
- printf("VID: Could not find voltage regulator on I2C.\n");
- goto exit;
- } else {
- i2caddress = ret;
- debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
- }
-#endif
-
- /*
- * Read voltage monitor to check real voltage.
- */
- vdd_last = read_voltage(i2caddress);
- if (vdd_last < 0) {
- printf("VID: Couldn't read sensor abort VID adjustment\n");
- goto exit;
- }
- printf("VID: Core voltage is at %d mV\n", vdd_last);
-exit:
- i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
-
- return ret < 0 ? -1 : 0;
-
-}
-
-static int do_vdd_override(cmd_tbl_t *cmdtp,
- int flag, int argc,
- char * const argv[])
-{
- ulong override;
- int ret = 0;
- if (argc < 2)
- return CMD_RET_USAGE;
-
- if (!strict_strtoul(argv[1], 10, &override)) {
- ret = adjust_vdd(override); /* the value is checked by callee */
- if (ret < 0)
- return CMD_RET_FAILURE;
- } else
- return CMD_RET_USAGE;
- return 0;
-}
-
-static int do_vdd_read(cmd_tbl_t *cmdtp,
- int flag, int argc,
- char * const argv[])
-{
- if (argc < 1)
- return CMD_RET_USAGE;
- print_vdd();
-
- return 0;
-}
-
-U_BOOT_CMD(
- vdd_override, 2, 0, do_vdd_override,
- "override VDD",
- " - override with the voltage specified in mV, eg. 1050"
-);
-
-U_BOOT_CMD(
- vdd_read, 1, 0, do_vdd_read,
- "read VDD",
- " - Read the voltage specified in mV"
-)
diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c
new file mode 120000
index 0000000000..99ed8aa2e5
--- /dev/null
+++ b/board/solidrun/common/vid.c
@@ -0,0 +1 @@
+../../freescale/common/vid.c
\ No newline at end of file
diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
deleted file mode 100644
index 9669e828a0..0000000000
--- a/board/solidrun/common/vid.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2020 NXP
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __VID_H_
-#define __VID_H_
-
-#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
-#define IR36021_LOOP1_VOUT_OFFSET 0x9A
-#define IR36021_MFR_ID_OFFSET 0x92
-#define IR36021_MFR_ID 0x43
-#define IR36021_INTEL_MODE_OOFSET 0x14
-#define IR36021_MODE_MASK 0x20
-#define IR36021_INTEL_MODE 0x00
-#define IR36021_AMD_MODE 0x20
-
-/* step the IR regulator in 5mV increments */
-#define IR_VDD_STEP_DOWN 5
-#define IR_VDD_STEP_UP 5
-
-/* LTC3882 */
-#define PMBUS_CMD_WRITE_PROTECT 0x10
-/*
- * WRITE_PROTECT command supported values
- * 0x80: Disable all writes except WRITE_PROTECT, PAGE,
- * STORE_USER_ALL and MFR_EE_UNLOCK commands.
- * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
- * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
- * Individual faults can also be cleared by writing a 1 to the
- * respective status bit.
- * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
- * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
- * and VOUT_COMMAND commands. Individual faults can be cleared by
- * writing a 1 to the respective status bit.
- * 0x00: Enables write to all commands
- */
-#define EN_WRITE_ALL_CMD (0)
-
-int adjust_vdd(ulong vdd_override);
-
-#endif /* __VID_H_ */
diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h
new file mode 120000
index 0000000000..5087631eb0
--- /dev/null
+++ b/board/solidrun/common/vid.h
@@ -0,0 +1 @@
+../../freescale/common/vid.h
\ No newline at end of file
--
2.25.1
patches/u-boot-LSDK-21.08/0034-lx2160acex7-support-u-boot-in-LSDK-21.08.patch 0 → 100644
View file @ a393e2e7
From a6d95d9072fc780289675f2a876059b8542f1464 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 16:01:48 +0200
Subject: [PATCH] lx2160acex7: support u-boot in LSDK-21.08
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-lx2160a-cex7.dts | 21 +++
board/solidrun/lx2160a/ddr.c | 1 +
board/solidrun/lx2160a/eth_lx2160acex7.c | 209 ++++++++++++++++-------
board/solidrun/lx2160a/lx2160a.c | 67 ++++----
common/board_r.c | 2 +-
configs/lx2160acex7_tfa_defconfig | 35 +++-
include/configs/lx2160a_common.h | 2 +
include/configs/lx2160acex7.h | 2 +
9 files changed, 239 insertions(+), 103 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3559b5e0ee..861346835b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -425,7 +425,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2162a-qds-17-x.dtb\
fsl-lx2162a-qds-18-x.dtb\
fsl-lx2162a-qds-20-x.dtb\
- fsl-lx2160a-cex7.dtb
+ fsl-lx2160a-cex7.dtb \
+ fsl-lx2162a-som.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
index 04adbcf64e..c8c0877e3d 100644
--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
+++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
@@ -21,6 +21,27 @@
};
};
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ cortina_phy: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
&fspi {
bus-num = <0>;
status = "okay";
diff --git a/board/solidrun/lx2160a/ddr.c b/board/solidrun/lx2160a/ddr.c
index 9c7bd10475..c2f424d4be 100644
--- a/board/solidrun/lx2160a/ddr.c
+++ b/board/solidrun/lx2160a/ddr.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 211de59971..eddc449bcd 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -12,11 +12,13 @@
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <asm/global_data.h>
#include <i2c.h>
#include <tlv_eeprom.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-layerscape/svr.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <fsl-mc/fsl_mc_private.h>
@@ -113,70 +115,6 @@ void setup_retimer_25g(int chnum)
}
}
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FSL_MC_ENET)
- struct memac_mdio_info mdio_info;
- struct memac_mdio_controller *reg;
- int i, interface;
- struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the EMI 1 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
- switch (srds_s1) {
- case 8:
- setup_retimer_25g(0);
- break;
- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 21:
- /* Setup 25gb retimer on lanes e,f,g,h */
- setup_retimer_25g(4);
- break;
- case 18:
- case 19:
- /* Setup 25gb retimer on lanes e,f and 10g on g,h */
- setup_retimer_25g(2);
- break;
-
- default:
- printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
- srds_s1);
- }
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- interface = wriop_get_enet_if(WRIOP1_DPMAC17);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(WRIOP1_DPMAC17, dev);
- }
-
- mac_read_from_eeprom();
- cpu_eth_init(bis);
-#endif /* CONFIG_FSL_MC_ENET */
-
- return pci_eth_init(bis);
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
@@ -194,3 +132,146 @@ int fdt_fixup_board_phy(void *fdt)
return ret;
}
+
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+ u8 serdes_block;
+ u32 serdes_protocol;
+ bool dts_needed;
+} supported_protocols[] = {
+ /* Serdes block #1 */
+ {1, 2, true},
+ {1, 3, true},
+ {1, 8, true},
+ {1, 15, true},
+ {1, 17, true},
+ {1, 18, true},
+ {1, 20, true},
+
+ /* Serdes block #2 */
+ {2, 2, false},
+ {2, 3, false},
+ {2, 5, false},
+ {2, 10, false},
+ {2, 11, true},
+ {2, 12, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol)
+ return true;
+ }
+
+ return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol) {
+ if (serdes_conf.dts_needed == true)
+ sprintf(str, "%u", protocol);
+ else
+ sprintf(str, "x");
+ return;
+ }
+ }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (get_svr() & 0x800) {
+ if (strncmp(name, "fsl-lx2162-som", 14)) return 1;
+ } else {
+ if (strncmp(name, "fsl-lx2160a-cex7", 16)) return 1;
+ }
+
+ return 0;
+}
+
+int fsl_board_late_init(void) {
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcw_status = in_le32(&gur->rcwsr[28]);
+ char srds_s1_str[2], srds_s2_str[2];
+ u32 srds_s1, srds_s2;
+ char expected_dts[100];
+
+ if (env_get("fdtfile"))
+ return 0;
+
+ srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+
+ /* Check for supported protocols. The default DTS will be used
+ * in this case
+ */
+ if (!protocol_supported(1, srds_s1) ||
+ !protocol_supported(2, srds_s2))
+ return -1;
+
+ get_str_protocol(1, srds_s1, srds_s1_str);
+ get_str_protocol(2, srds_s2, srds_s2_str);
+
+ if (get_svr() & 0x800) { /* LX2162A SOM variants */
+ sprintf(expected_dts, "fsl-lx2162a-som-%s-%s.dtb",
+ srds_s1_str, srds_s2_str);
+ } else {
+ switch (srds_s1) {
+ case 8:
+ setup_retimer_25g(0);
+ break;
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 17:
+ case 21:
+ /* Setup 25gb retimer on lanes e,f,g,h */
+ setup_retimer_25g(4);
+ break;
+ case 18:
+ case 19:
+ /* Setup 25gb retimer on lanes e,f and 10g on g,h */
+ setup_retimer_25g(2);
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
+ srds_s1);
+ }
+ sprintf(expected_dts, "fsl-lx2160a-clearfog-cx.dtb");
+ }
+ env_set("fdtfile", expected_dts);
+ return 0;
+}
+#endif
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index 8f9251c294..e078ae5c68 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -6,6 +6,8 @@
#include <common.h>
#include <clock_legacy.h>
#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
#include <i2c.h>
#include <malloc.h>
@@ -15,7 +17,9 @@
#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
+#include <linux/bitops.h>
#include <linux/libfdt.h>
+#include <linux/delay.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <efi_loader.h>
@@ -28,6 +32,7 @@
#include "../../freescale/common/vid.h"
#include <fsl_immap.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
+//#include "lx2160a.h"
#include <asm/gic-v3.h>
#ifdef CONFIG_EMC2301
@@ -37,7 +42,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pl01x_serial_platdata serial0 = {
+static struct pl01x_serial_plat serial0 = {
#if CONFIG_CONS_INDEX == 0
.base = CONFIG_SYS_SERIAL0,
#elif CONFIG_CONS_INDEX == 1
@@ -48,26 +53,26 @@ static struct pl01x_serial_platdata serial0 = {
.type = TYPE_PL011,
};
-U_BOOT_DEVICE(nxp_serial0) = {
+U_BOOT_DRVINFO(nxp_serial0) = {
.name = "serial_pl01x",
- .platdata = &serial0,
+ .plat = &serial0,
};
-static struct pl01x_serial_platdata serial1 = {
+static struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
};
-U_BOOT_DEVICE(nxp_serial1) = {
+U_BOOT_DRVINFO(nxp_serial1) = {
.name = "serial_pl01x",
- .platdata = &serial1,
+ .plat = &serial1,
};
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
@@ -111,9 +116,8 @@ int board_early_init_f(void)
#ifdef CONFIG_OF_BOARD_FIXUP
int board_fix_fdt(void *fdt)
{
- char *reg_name, *old_str, *new_str;
- const char *reg_names;
- int names_len, old_str_len, new_str_len, remaining_str_len;
+ char *reg_names, *reg_name;
+ int names_len, old_name_len, new_name_len, remaining_names_len;
struct str_map {
char *old_str;
char *new_str;
@@ -121,7 +125,7 @@ int board_fix_fdt(void *fdt)
{ "ccsr", "dbi" },
{ "pf_ctrl", "ctrl" }
};
- int off = -1, i;
+ int off = -1, i = 0;
if (IS_SVR_REV(get_svr(), 1, 0))
return 0;
@@ -131,39 +135,41 @@ int board_fix_fdt(void *fdt)
fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
strlen("fsl,ls-pcie") + 1);
- reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
+ reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
+ &names_len);
if (!reg_names)
continue;
- reg_name = (char *)reg_names;
- remaining_str_len = names_len - (reg_name - reg_names);
+ reg_name = reg_names;
+ remaining_names_len = names_len - (reg_name - reg_names);
i = 0;
- while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
- old_str = reg_names_map[i].old_str;
- new_str = reg_names_map[i].new_str;
- old_str_len = strlen(old_str);
- new_str_len = strlen(new_str);
- if (memcmp(reg_name, old_str, old_str_len) == 0) {
+ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
+ old_name_len = strlen(reg_names_map[i].old_str);
+ new_name_len = strlen(reg_names_map[i].new_str);
+ if (memcmp(reg_name, reg_names_map[i].old_str,
+ old_name_len) == 0) {
/* first only leave required bytes for new_str
* and copy rest of the string after it
*/
- memcpy(reg_name + new_str_len,
- reg_name + old_str_len,
- remaining_str_len - old_str_len);
+ memcpy(reg_name + new_name_len,
+ reg_name + old_name_len,
+ remaining_names_len - old_name_len);
/* Now copy new_str */
- memcpy(reg_name, new_str, new_str_len);
- names_len -= old_str_len;
- names_len += new_str_len;
+ memcpy(reg_name, reg_names_map[i].new_str,
+ new_name_len);
+ names_len -= old_name_len;
+ names_len += new_name_len;
i++;
}
- reg_name = memchr(reg_name, '\0', remaining_str_len);
+ reg_name = memchr(reg_name, '\0', remaining_names_len);
if (!reg_name)
break;
reg_name += 1;
- remaining_str_len = names_len - (reg_name - reg_names);
+ remaining_names_len = names_len -
+ (reg_name - reg_names);
}
fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
@@ -238,6 +244,9 @@ int board_init(void)
sec_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
return 0;
}
@@ -297,7 +306,7 @@ void board_quiesce_devices(void)
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
int i;
bool mc_memory_bank = false;
diff --git a/common/board_r.c b/common/board_r.c
index aa0fe6b57d..6e7500cd7e 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -755,7 +755,7 @@ static init_fnc_t init_sequence_r[] = {
#endif
INIT_FUNC_WATCHDOG_RESET
cpu_secondary_init_r,
-#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
+#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) || defined(CONFIG_CMD_TLV_EEPROM)
mac_read_from_eeprom,
#endif
INIT_FUNC_WATCHDOG_RESET
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 8c2a6b338b..ba35686463 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -1,16 +1,20 @@
CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
CONFIG_TARGET_LX2160ACEX7=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
CONFIG_AHCI=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -21,9 +25,12 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_OPTEE_RPMB=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
@@ -33,24 +40,29 @@ CONFIG_CMD_NVME=y
CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_BOARD_FIXUP=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+CONFIG_OF_LIST="fsl-lx2160a-cex7 fsl-lx2162a-som"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
-CONFIG_I2C_EEPROM=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MTD=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -70,21 +82,30 @@ CONFIG_CMD_DHCP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_TLV_EEPROM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PHY_ATHEROS=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
+CONFIG_RTC_MCP79411=y
CONFIG_CMD_POWEROFF=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
CONFIG_NXP_FSPI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -100,5 +121,3 @@ CONFIG_GIC_V3_ITS=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_TA_AVB=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_CMD_OPTEE_RPMB=y
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 4a9c28858f..44580f6501 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -117,6 +117,7 @@
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
+#if 0
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
@@ -124,6 +125,7 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#endif
/* QSFP/SFP module EEPROMs */
#define I2C_SFP_EEPROM_ADDR 0x50
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index d2ef78a243..6e1e4b45a2 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -77,6 +77,8 @@
"bootm $load_addr#$BOARD\0"
#include <asm/fsl_secure_boot.h>
+#undef CONFIG_SYS_MEMTEST_START
+#undef CONFIG_SYS_MEMTEST_END
#define CONFIG_SYS_MEMTEST_START 0x2080000000
#define CONFIG_SYS_MEMTEST_END 0x2400000000
--
2.25.1
patches/u-boot-LSDK-21.08/0035-lx2162a-som-add-lx2162-som-support.patch 0 → 100644
View file @ a393e2e7
From 7a3099c659002fb3a41d64d2179875bcedb43abc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 29 Nov 2021 16:03:19 +0200
Subject: [PATCH] lx2162a-som: add lx2162-som support
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/fsl-lx2162a-som.dts | 12 +++++
arch/arm/dts/fsl-lx2162a-som.dtsi | 86 +++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 arch/arm/dts/fsl-lx2162a-som.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-som.dtsi
diff --git a/arch/arm/dts/fsl-lx2162a-som.dts b/arch/arm/dts/fsl-lx2162a-som.dts
new file mode 100644
index 0000000000..3be70a0e49
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2162a-som.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2162A based SOM - DPMAC17
+ *
+ * Copyright 2021 SoldRun ltd (rabeeh@solid-run.com)
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2162a-som.dtsi"
+
diff --git a/arch/arm/dts/fsl-lx2162a-som.dtsi b/arch/arm/dts/fsl-lx2162a-som.dtsi
new file mode 100644
index 0000000000..8271fad8d6
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2162a-som.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2160ACEX7 device tree source
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * Copyright 2021 SolidRun ltd.
+ *
+ */
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2162A based System On Module";
+ compatible = "fsl,lx2160asom", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+ };
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ cortina_phy: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: MT35XU512ABA1G12@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ rtc@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+ };
+};
--
2.25.1
patches/u-boot-LSDK-21.08/0036-lx2160acex7-correctly-set-dt-and-add-retimer.patch 0 → 100644
View file @ a393e2e7
From 828f8da93793da0c83a1db53c81121b90d5ada00 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 30 Nov 2021 13:53:00 +0200
Subject: [PATCH] lx2160acex7: correctly set dt, and add retimer
1. Correctly set device tree for multi dtb support
2. Setup the single retimer device in the SolidNet carrier board
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 91 ++++++++++++++++++++++--
1 file changed, 86 insertions(+), 5 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index eddc449bcd..abca006d22 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -115,6 +115,61 @@ void setup_retimer_25g(int chnum)
}
}
+void setup_retimer_lx2162_25g(int speed_is_25g)
+{
+ int i, ret;
+ u8 reg;
+ struct udevice *dev;
+
+ select_i2c_ch_pca9547(0xb); /* SMB_CLK / DATA interface */
+ /*
+ * Retimer on address 0x22; first two channels are LX TX.
+ */
+ ret = i2c_get_chip_for_busnum(0, 0x22, 1, &dev);
+ if (ret) {
+ /*
+ * On HoneyComb and ClearFog CX ver 1.1 / 1.2 there is no retimer
+ * assembled; silently return.
+ */
+ return;
+ }
+ ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
+ if (ret) {
+ printf ("ERROR: Could not get retimer device ID\n");
+ return;
+ }
+ if (reg != 0x10) {
+ printf ("ERROR : DS250DF410 retimer not found\n");
+ return;
+ }
+ printf ("Setting up retimer channels as %s\n",speed_is_25g?"25Gbps":"10Gbps");
+
+ dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
+ /*
+ * Setup 25Gbps channel on 0..chnum.
+ * Notice that the ingress retimer is mirrorly mapped with the SERDES
+ * number, so SERDES #0 is connected to channel #3, SERDES 1 to channel
+ * #2 ...
+ */
+ if (speed_is_25g) for (i = 0 ; i < 4; i++) { /* Setup all channels as 25g */
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+ dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
+ dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
+ /* Set post-cursor of channel #0 to -4 */
+ dm_i2c_reg_write(dev, 0x3f, 0x44);
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+ else for (i = 0 ; i < 4; i++) {
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+ dm_i2c_reg_write(dev, 0x2f, 0x04); /* Set rate to 10.3125 Gbps */
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+}
+
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
@@ -153,15 +208,18 @@ static struct serdes_configuration {
bool dts_needed;
} supported_protocols[] = {
/* Serdes block #1 */
+ {1, 0, false},
{1, 2, true},
{1, 3, true},
{1, 8, true},
{1, 15, true},
{1, 17, true},
{1, 18, true},
+ {1, 19, true},
{1, 20, true},
/* Serdes block #2 */
+ {2, 0, false},
{2, 2, false},
{2, 3, false},
{2, 5, false},
@@ -208,12 +266,14 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
if (get_svr() & 0x800) {
- if (strncmp(name, "fsl-lx2162-som", 14)) return 1;
+ if (!strncmp(name, "fsl-lx2162a-som", 15)) {
+ return 0;
+ }
} else {
- if (strncmp(name, "fsl-lx2160a-cex7", 16)) return 1;
+ if (!strncmp(name, "fsl-lx2160a-cex7", 16)) return 0;
}
- return 0;
+ return -1;
}
int fsl_board_late_init(void) {
@@ -223,6 +283,7 @@ int fsl_board_late_init(void) {
u32 srds_s1, srds_s2;
char expected_dts[100];
+ printf ("fsl_board_late_init\n");
if (env_get("fdtfile"))
return 0;
@@ -238,13 +299,33 @@ int fsl_board_late_init(void) {
*/
if (!protocol_supported(1, srds_s1) ||
!protocol_supported(2, srds_s2))
- return -1;
+ return 0;
get_str_protocol(1, srds_s1, srds_s1_str);
get_str_protocol(2, srds_s2, srds_s2_str);
if (get_svr() & 0x800) { /* LX2162A SOM variants */
- sprintf(expected_dts, "fsl-lx2162a-som-%s-%s.dtb",
+ switch (srds_s1) {
+ case 8:
+ setup_retimer_lx2162_25g(0);
+ break;
+ case 15:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 21:
+ /* Setup 25gb retimer on lanes e,f,g,h */
+ setup_retimer_lx2162_25g(1);
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LX2160A-SOM\n",
+ srds_s1);
+ }
+ if ((srds_s1 == 18) && ((srds_s2 == 2) || (srds_s2 == 3)))
+ /* SolidNet device tree */
+ sprintf(expected_dts, "fsl-lx2162a-solidnet.dtb");
+ else sprintf(expected_dts, "fsl-lx2162a-som-%s-%s.dtb",
srds_s1_str, srds_s2_str);
} else {
switch (srds_s1) {
--
2.25.1
runme.sh
View file @ a393e2e7
......@@ -12,7 +12,7 @@ BUILDROOT_VERSION=2020.02.1
###############################################################################
# Misc
###############################################################################
RELEASE=${RELEASE:-LSDK-20.12}
RELEASE=${RELEASE:-LSDK-21.08}
DDR_SPEED=${DDR_SPEED:-3200}
SERDES=${SERDES:-8_5_2}
UEFI_RELEASE=${UEFI_RELEASE:-RELEASE}
......@@ -36,7 +36,7 @@ mkdir -p build images
ROOTDIR=`pwd`
PARALLEL=$(getconf _NPROCESSORS_ONLN) # Amount of parallel jobs for the builds
SPEED=2000_700_${DDR_SPEED}
TOOLS="tar git make 7z dd mkfs.ext4 parted mkdosfs mcopy dtc iasl mkimage e2cp truncate qemu-system-aarch64 cpio rsync bc bison flex python unzip"
TOOLS="tar git make 7z dd mkfs.ext4 parted mkdosfs mcopy dtc iasl mkimage e2cp truncate qemu-system-aarch64 cpio rsync bc bison flex python unzip pandoc meson ninja"
BL2=bl2_auto
export PATH=$ROOTDIR/build/toolchain/gcc-linaro-7.4.1-2019.02-x86_64_aarch64-linux-gnu/bin:$PATH
......@@ -47,6 +47,14 @@ REPO_PREFIX=`git log -1 --pretty=format:%h`
echo "Repository prefix for images is $REPO_PREFIX"
case "${SERDES}" in
0_*)
DPC=dpc-8_x_usxgmii.dtb
DPL=dpl-eth.8x10g.19.dtb
;;
8_9_*)
DPC=dpc-8_x_usxgmii_8_x_sgmii.dtb
DPL=dpl-eth.8x10g.8x1g.19.dtb
;;
2_*)
DPC=dpc-8_x_usxgmii.dtb
DPL=dpl-eth.8x10g.19.dtb
......@@ -71,6 +79,14 @@ case "${SERDES}" in
DPC=dpc-quad-25g.dtb
DPL=dpl-eth.quad-25g.19.dtb
;;
18_*)
DPC=dpc-sd1-18.dtb
DPL=dpl-sd1-18.dtb
;;
19_*)
DPC=dpc-quad-25g.dtb
DPL=dpl-eth.quad-25g.19.dtb
;;
20_*)
DPC=dpc-dual-40g.dtb
DPL=dpl-eth.dual-40g.19.dtb
......@@ -98,7 +114,7 @@ for i in $TOOLS; do
if [ "x$TOOL_PATH" == "x" ]; then
echo "Tool $i is not installed"
echo "If running under apt based package management you can run -"
echo "sudo apt install build-essential git dosfstools e2fsprogs parted sudo mtools p7zip p7zip-full device-tree-compiler acpica-tools u-boot-tools e2tools qemu-system-arm libssl-dev cpio rsync bc bison flex python unzip"
echo "sudo apt install build-essential git dosfstools e2fsprogs parted sudo mtools p7zip p7zip-full device-tree-compiler acpica-tools u-boot-tools e2tools qemu-system-arm libssl-dev cpio rsync bc bison flex python unzip pandoc meson ninja-build"
exit -1
fi
done
......@@ -155,11 +171,10 @@ for i in $QORIQ_COMPONENTS; do
make
./fiptool create --ddr-immem-udimm-1d ddr-phy-binary/lx2160a/ddr4_pmu_train_imem.bin --ddr-immem-udimm-2d ddr-phy-binary/lx2160a/ddr4_2d_pmu_train_imem.bin --ddr-dmmem-udimm-1d ddr-phy-binary/lx2160a/ddr4_pmu_train_dmem.bin --ddr-dmmem-udimm-2d ddr-phy-binary/lx2160a/ddr4_2d_pmu_train_dmem.bin --ddr-immem-rdimm-1d ddr-phy-binary/lx2160a/ddr4_rdimm_pmu_train_imem.bin --ddr-immem-rdimm-2d ddr-phy-binary/lx2160a/ddr4_rdimm2d_pmu_train_imem.bin --ddr-dmmem-rdimm-1d ddr-phy-binary/lx2160a/ddr4_rdimm_pmu_train_dmem.bin --ddr-dmmem-rdimm-2d ddr-phy-binary/lx2160a/ddr4_rdimm2d_pmu_train_dmem.bin fip_ddr_all.bin
fi
if [[ -d $ROOTDIR/patches/$i/ ]]; then
git am $ROOTDIR/patches/$i/*.patch
fi
if [[ -d $ROOTDIR/patches/$i-$RELEASE/ ]]; then
git am $ROOTDIR/patches/$i-$RELEASE/*.patch
elif [[ -d $ROOTDIR/patches/$i/ ]]; then
git am $ROOTDIR/patches/$i/*.patch
fi
if [[ $RELEASE == *"-update"* ]]; then
# Check extract the LSDK name up to the '-update-...'
......@@ -286,7 +301,8 @@ if [ "x$SECURE" == "xtrue" ]; then
cp tools/fiptool/ddr-phy-binary/lx2160a/*.bin .
make -j${PARALLEL} PLAT=lx2160acex7 all fip fip_ddr_sec fip_fuse pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=1 CST_DIR=$ROOTDIR/build/cst/ GENERATE_COT=0 BOOT_MODE=${BOOT_MODE_VAR} SECURE_BOOT=yes FUSE_PROG=1 FUSE_PROV_FILE=$ROOTDIR/build/cst/fuse_scr.bin $ATF_DEBUG
else
make -j${PARALLEL} PLAT=lx2160acex7 all fip pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=0 GENERATE_COT=0 BOOT_MODE=auto SECURE_BOOT=false
make -j${PARALLEL} PLAT=lx2160acex7 all fip pbl RCW=$ROOTDIR/build/rcw/lx2160acex7/RCW/template.bin TRUSTED_BOARD_BOOT=0 GENERATE_COT=0 BOOT_MODE=auto SECURE_BOOT=false $ATF_DEBUG
# DDR_PHY_DEBUG=yes DDR_DEBUG=yes # DEBUG_PHY_IO=yes
fi
echo "Building mc-utils"
......@@ -319,7 +335,7 @@ cat > kernel2160cex7.its << EOF
};
initrd {
description = "initrd for arm64";
data = /incbin/("../../patches/linux-${RELEASE}/ramdisk_rootfs_arm64.ext4.gz");
data = /incbin/("../../patches/ramdisk_rootfs_arm64.ext4.gz");
type = "ramdisk";
arch = "arm64";
os = "linux";
......@@ -332,7 +348,7 @@ cat > kernel2160cex7.its << EOF
};
lx2160acex7-dtb {
description = "lx2160acex7-dtb";
data = /incbin/("arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtb");
data = /incbin/("arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dtb");
type = "flat_dt";
arch = "arm64";
os = "linux";
......@@ -360,7 +376,7 @@ mkdir -p $ROOTDIR/images/tmp/
mkdir -p $ROOTDIR/images/tmp/boot
make INSTALL_MOD_PATH=$ROOTDIR/images/tmp/ INSTALL_MOD_STRIP=1 modules_install
cp $ROOTDIR/build/linux/arch/arm64/boot/Image $ROOTDIR/images/tmp/boot
cp $ROOTDIR/build/linux/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtb $ROOTDIR/images/tmp/boot
cp $ROOTDIR/build/linux/arch/arm64/boot/dts/freescale/fsl-lx216*.dtb $ROOTDIR/images/tmp/boot
......@@ -370,10 +386,8 @@ export CROSS=$CROSS_COMPILE
export RTE_SDK=$ROOTDIR/build/dpdk
export DESTDIR=$ROOTDIR/build/dpdk/install
export RTE_TARGET=arm64-dpaa-linuxapp-gcc
#make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n clean
make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n install
make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l2fwd install
make -j32 T=arm64-dpaa-linuxapp-gcc CONFIG_RTE_KNI_KMOD=n CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -C examples/l3fwd install
meson arm64-dpaa-build -Dexamples=all --cross-file config/arm/arm64_dpaa_linux_gcc
ninja -C arm64-dpaa-build
###############################################################################
......@@ -383,13 +397,13 @@ echo "Assembling kernel and rootfs image"
cd $ROOTDIR
mkdir -p $ROOTDIR/images/tmp/extlinux/
cat > $ROOTDIR/images/tmp/extlinux/extlinux.conf << EOF
TIMEOUT 30
DEFAULT linux
MENU TITLE linux-lx2160a boot options
LABEL primary
MENU LABEL primary kernel
LINUX /boot/Image
FDT /boot/fsl-lx2160a-cex7.dtb
timeout 30
default linux
menu title linux-lx2160a boot options
label primary
menu label primary kernel
linux /boot/Image
fdtdir /boot/
APPEND console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf root=PARTUUID=30303030-01 rw rootwait
EOF
......@@ -399,7 +413,7 @@ e2mkdir -G 0 -O 0 $ROOTDIR/images/tmp/ubuntu-core.ext4:extlinux
e2cp -G 0 -O 0 $ROOTDIR/images/tmp/extlinux/extlinux.conf $ROOTDIR/images/tmp/ubuntu-core.ext4:extlinux/
e2mkdir -G 0 -O 0 $ROOTDIR/images/tmp/ubuntu-core.ext4:boot
e2cp -G 0 -O 0 $ROOTDIR/images/tmp/boot/Image $ROOTDIR/images/tmp/ubuntu-core.ext4:boot/
e2cp -G 0 -O 0 $ROOTDIR/images/tmp/boot/fsl-lx2160a-cex7.dtb $ROOTDIR/images/tmp/ubuntu-core.ext4:boot/
e2cp -G 0 -O 0 $ROOTDIR/images/tmp/boot/fsl-lx216*.dtb $ROOTDIR/images/tmp/ubuntu-core.ext4:boot/
# Copy over kernel image
echo "Copying kernel modules"
......@@ -475,7 +489,7 @@ if [ "x$RELEASE" == "xLSDK-20.04" ]; then
MC=mc_10.24.0_lx2160a.itb
dd if=$ROOTDIR/build/qoriq-mc-binary/lx2160a/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
else
MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/ | cut -f1`
MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/ | grep -v sha256sum | cut -f1`
dd if=$ROOTDIR/build/qoriq-mc-binary/lx216xa/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
fi
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7