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lx2160a_build
Commit c32dee74 authored by Rabeeh Khoury's avatar Rabeeh Khoury
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Added LSDK 20.04 support 

Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent a0f760f5
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README.md
View file @ c32dee74
......@@ -7,6 +7,9 @@ They are used in SolidRun to quickly build images for development where those im
The sources are pulled from NXP's codeaurora repository and patched after being clone using the patches in the patches/ directory
The build script builds the u-boot, atf, rcw and linux components, integrate it with Ubuntu rootfs bootstrapped with multistrap. Buildroot is also built aside for future use.
## Build with Docker
A docker image providing a consistent build environment can be used as below. Since some steps require mounting a loopback device, you need to grant permission for the container to do so when launching:
......@@ -51,3 +54,28 @@ For SD card bootable images, plug in a micro SD into your machine and run the fo
For SPI boot, boot thru SD card and then load the _xspi_ images to system memory and flash it using the `sf probe` and `sf update` commands. An example below loads the image through TFTP prototocl, flashes and then verifies the image -
`sf probe; setenv ipaddr 192.168.15.223; setenv serverip 192.168.15.3; tftp 0xa0000000 lx2160acex7_xspi_2000_700_2600_8_5_2_xspi.img;sf update 0xa0000000 0 $filesize; sf read 0xa4000000 0 $filesize; cmp 0xa0000000 0xa4000000 $filesize`
And then set boot DIP switch on COM to off/off/off/off from numbers 1 to 4 (dip number 5 is not used. Notice the marking 'ON' on the DIP switch)
For eMMC boot (supported only thru LX2160A silicon rev 2 which is LX2160A COM Express type 7 rev 1.5 and newer) -
`load mmc 0:1 0xa4000000 ubuntu-core.img`
`mmc dev 1`
`mmc write 0xa4000000 0 0xd2000`
And then set boot DIP switch on COM to off/on/on/off from numbers 1 to 4 (dip number 5 is not used, notice the marking 'ON' on the DIP switch)
After booting Ubuntu you must resize the boot partition; for instance if booted under eMMC then login as root/root; then fdisk /dev/mmcblk1; delete first partition and then recreate it starting from 131072 (64MByte) to the end of the volume.
Do not remove the signaute since it indicates for the kernel which partition ID to use.
After resizing the partition; resize the ext4 boot volume by running 'resize2fs /dev/mmcblk1p1'
Afterwards run update the RTC and update the repository -
`dhclient -i eth0; ntpdate pool.ntp.org; apt update`
If using a GPU then install the linux-firmware package that contains GPU firmwares -
`apt install linux-firmware`
patches/linux-LSDK-20.04/0001-arm64-dts-lx2160a-add-lx2160acex7-device-tree-build.patch 0 → 100644
View file @ c32dee74
From 0038ae610ef69f00adf358d915ae618a83ac63cb Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 4 May 2020 17:33:28 +0300
Subject: [PATCH] arm64: dts: lx2160a: add lx2160acex7 device tree build
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 5e05e0be3aeb..7d342cffb87e 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex7.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \
imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \
--
2.17.1
patches/linux-LSDK-20.04/0002-arm64-dts-lx2160a-add-lx2160acex7-device-tree.patch 0 → 100644
View file @ c32dee74
From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 14:21:06 +0300
Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
The device tree enables the following features -
1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
2. 2x MDIO busses
3. 2x USB 3.0 controllers
4. 4x SATA ports
5. MT35X 512Mb SPI flash
6. Temperature sensor on i2c0 channel 3
7. AMC6821 temperature and PWM fan controller
The module supports AMC6821 and EMC2301 PWM controllers where either can
be assembled, but not both together since the PWM and TACH signals are
shared between them.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 190 ++++++++++++++++++
1 file changed, 190 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
new file mode 100644
index 000000000000..872fcf9e724d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160A-CEx7
+//
+// Copyright 2019 SolidRun ltd.
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160A COM express type 7 module";
+ compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "RT7290";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+
+/*
+i2c busses are -
+/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
+/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
+/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
+
+I2C switch -
+/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
+/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
+/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
+/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
+/dev/i2c7 - CH4 - SFP #0 I2C
+/dev/i2c8 - CH5 - SFP #1 I2C
+/dev/i2c9 - CH6 - SFP #2 I2C
+/dev/i2c10 - CH7 - SFP #3 I2C
+
+
+*/
+
+
+
+&i2c0 {
+ status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@48 {
+ compatible = "nxp,sa56004";
+ reg = <0x48>;
+ vcc-supply = <&sb_3v3>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ // IRQ10_B
+ interrupts = <0 150 0x4>;
+ };
+};
+
+&fspi {
+ status = "okay";
+ flash0: mt35xu512aba@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emdio1 {
+ status = "okay";
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&dpmac17 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
--
2.17.1
patches/linux-LSDK-20.04/0005-arm64-dts-lx2160a-cex7-add-ltc3882-support.patch 0 → 100644
View file @ c32dee74
From cca2439ac83136b9ed85f8519931018d4f5385e6 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 12 Jan 2020 14:24:47 +0200
Subject: [PATCH] arm64: dts: lx2160a-cex7: add ltc3882 support
ltc3882 is lx2 cortex-a72 core voltage.
this patch adds it to the device tree support; the driver is in
drivers/hwmon/pmbus/ltc2978.c
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
index 872fcf9e724d..1c1a0d47897d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -94,6 +94,15 @@ I2C switch -
#cooling-cells = <2>;
};
};
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ ltc3882@5c {
+ compatible = "ltc3882";
+ reg = <0x5c>;
+ };
+ };
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
patches/linux-LSDK-20.04/0006-arm64-dts-lx2160a-cex7-add-on-module-eeproms.patch 0 → 100644
View file @ c32dee74
From 05acb6ecc8eb7426c4664a1e8fd22ad69256d541 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 26 Jan 2020 15:36:07 +0200
Subject: [PATCH] arm64: dts: lx2160a-cex7: add on-module eeproms
This patch adds 4 eeprom support on i2c mux channel #0 -
1. Bootable 512Kbit eeprom at address 0x50.
2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53.
3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing
data.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 22 ++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
index 1c1a0d47897d..2b8f1118b37a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -81,7 +81,27 @@ I2C switch -
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
-
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ 24aa512@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+ spd1@51 {
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+ spd2@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
patches/linux-LSDK-20.04/0007-pci-hotplug-declare-IDT-bridge-as-hotpluggabl-bridge.patch 0 → 100644
View file @ c32dee74
From 927a01dffed9eb439bc9bf6df0b6548380bc84a7 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 10 Feb 2020 10:47:45 +0200
Subject: [PATCH] pci: hotplug: declare IDT bridge as hotpluggabl bridge
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
drivers/pci/quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 55870dd42b4d..bfac025931e0 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2915,6 +2915,7 @@ static void quirk_hotplug_bridge(struct pci_dev *dev)
dev->is_hotplug_bridge = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IDT, 0x808c, quirk_hotplug_bridge);
/*
* This is a quirk for the Ricoh MMC controller found as a part of some
--
2.17.1
patches/linux-LSDK-20.04/0008-pci-spr2803-quirk-to-fix-class-ID.patch 0 → 100644
View file @ c32dee74
From bba6ebb2daac17bd2268c97b7255e477c2b15b52 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 26 Feb 2020 17:57:54 +0200
Subject: [PATCH] pci: spr2803: quirk to fix class ID
spr2803 class is 0x0, this quirk modifies that to multimedia class in
order to allocate memory to it's bars.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
drivers/pci/quirks.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 28c64f84bfe7..4ddf7e43d531 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3068,6 +3068,18 @@ static void fixup_ti816x_class(struct pci_dev *dev)
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
+static void fixup_spr2803_class(struct pci_dev *dev)
+{
+ u32 class = dev->class;
+
+ /* spr2803 does not have class code */
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
+ pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
+ class, dev->class);
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1e00, 0x2803,
+ PCI_CLASS_NOT_DEFINED, 8, fixup_spr2803_class);
+
/*
* Some PCIe devices do not work reliably with the claimed maximum
* payload size supported.
--
2.17.1
patches/rcw-LSDK-20.04/0001-lx2160acex7-misc-RCW-files.patch 0 → 100644
View file @ c32dee74
This diff is collapsed.
patches/rcw-LSDK-20.04/0002-Set-io-pads-as-GPIO.patch 0 → 100644
View file @ c32dee74
From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 30 Oct 2019 11:43:37 +0200
Subject: [PATCH 2/2] Set io pads as GPIO
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 6fd65ec..dbc843f 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1
HWA_CGB_M1_CLK_SEL=7
BOOT_LOC=26
SYSCLK_FREQ=600
-IIC2_PMUX=6
+IIC2_PMUX=1
IIC3_PMUX=0
IIC4_PMUX=2
USB3_CLK_FSEL=39
SRDS_DIV_PEX_S1=1
SRDS_DIV_PEX_S2=3
SRDS_DIV_PEX_S3=1
-
+SDHC1_DIR_PMUX=1
+IRQ03_00_PMUX=1
+IRQ07_04_PMUX=1
+IRQ11_08_PMUX=1
+EVT20_PMUX=1
+EVT43_PMUX=1
--
2.17.1
patches/rcw-LSDK-20.04/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch 0 → 100644
View file @ c32dee74
From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 5 Nov 2019 10:35:32 +0200
Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28
Serdes group 2 enable PCIe gen 3
XSPI increase divisor to 28 - this fixes UEFI SPI flash detection.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index dbc843f..3ea7683 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -14,7 +14,7 @@ IIC3_PMUX=0
IIC4_PMUX=2
USB3_CLK_FSEL=39
SRDS_DIV_PEX_S1=1
-SRDS_DIV_PEX_S2=3
+SRDS_DIV_PEX_S2=1
SRDS_DIV_PEX_S3=1
SDHC1_DIR_PMUX=1
IRQ03_00_PMUX=1
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index eecc314..28310c9 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -14,4 +14,4 @@
#include <../lx2160asi/common.rcw>
/* Modify FlexSPI Clock Divisor value */
-#include <../lx2160asi/flexspi_divisor_24.rcw>
+#include <../lx2160asi/flexspi_divisor_28.rcw>
--
2.17.1
patches/rcw-LSDK-20.04/0004-refactor-a009531-a008851-and-a011270.patch 0 → 100644
View file @ c32dee74
From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:16:13 +0200
Subject: [PATCH 4/4] refactor a009531, a008851 and a011270
1. Add 'load conditional', 'jump condidional' and 'jump' to PBI
instructions.
2. Use SVR register to execute the PCIe workarounds on the relevant rev
of the device.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++
lx2160asi/a011270.rcw | 6 +++
rcw.py | 28 ++++++++++
3 files changed, 130 insertions(+)
create mode 100644 lx2160asi/a009531_a008851.rcw
diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw
new file mode 100644
index 0000000..0eb7051
--- /dev/null
+++ b/lx2160asi/a009531_a008851.rcw
@@ -0,0 +1,96 @@
+/*
+ * Work-around for erratum A-009531
+ *
+ * Description:
+ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO)
+ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer
+ * is permitted to set IDO only if the IDO Completion Enable bit in the Device
+ * Control 2 Register is set. It is not required to copy the value of IDO from
+ * the Request into the Completion(s) for that Request".
+ *
+ * However, the PCI Express controller as the completer sets the IDO bit in the
+ * completion packet header, in response to non-posted requests (memory read) with
+ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the
+ * Device Control 2 Register is not set.
+ *
+ * Impact:
+ * The PCI Express controller as the completer sends completion packets with IDO
+ * bit set in packet header even when the IDO Completion Enable bit is cleared in
+ * the controller’s Device Control 2 Register.
+ * Applicable for SNP PCIe controller
+ */
+
+/*
+ * Work-around for erratum A-008851
+ *
+ * Invalid transmitter/receiver preset values are used in Gen3 equalization
+ * phases during link training for RC mode
+ * This errata is valid only for PCI gen3.
+ * Workaround:
+ * write 0x00000001 to MISC_CONTROL_1_OFF
+ * write 0x4747 to Lane Equalization Control register for each lane
+ * Applicable for SNP PCIe controller
+ */
+
+.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+
+/* If it is rev 2, skip the following jump command */
+jumpc 0x00000014,0x00000020
+
+/* Jump all the below instructions */
+jump 0x190 /* All instruction below including the jump are 0x190 bytes */
+
+loadc 0x01ea1080,0x70000000
+jumpc 0x00000034,0x00000000
+write 0x03400098,0x00000000
+write 0x034008bc,0x00000001
+write 0x03400154,0x47474747
+write 0x03400158,0x47474747
+write 0x034008bc,0x00000000
+
+loadc 0x01ea1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03500098,0x00000000
+write 0x035008bc,0x00000001
+write 0x03500154,0x47474747
+write 0x03500158,0x47474747
+write 0x035008bc,0x00000000
+
+loadc 0x01eb1080,0x70000000
+jumpc 0x00000044,0x00000000
+write 0x03600098,0x00000000
+write 0x036008bc,0x00000001
+write 0x03600164,0x47474747
+write 0x03600168,0x47474747
+write 0x0360016c,0x47474747
+write 0x03600170,0x47474747
+write 0x036008bc,0x00000000
+
+loadc 0x01eb1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03700098,0x00000000
+write 0x037008bc,0x00000001
+write 0x03700154,0x47474747
+write 0x03700158,0x47474747
+write 0x037008bc,0x00000000
+
+loadc 0x01ec1080,0x70000000
+jumpc 0x00000044,0x00000000
+write 0x03800098,0x00000000
+write 0x038008bc,0x00000001
+write 0x03800164,0x47474747
+write 0x03800168,0x47474747
+write 0x0380016c,0x47474747
+write 0x03800170,0x47474747
+write 0x038008bc,0x00000000
+
+loadc 0x01ec1080,0x00700000
+jumpc 0x00000034,0x00000000
+write 0x03900098,0x00000000
+write 0x039008bc,0x00000001
+write 0x03900154,0x47474747
+write 0x03900158,0x47474747
+write 0x039008bc,0x00000000
+.end
diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw
index 0dc774d..5bd5558 100644
--- a/lx2160asi/a011270.rcw
+++ b/lx2160asi/a011270.rcw
@@ -4,6 +4,12 @@
*/
.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+/* If it is rev 1, skip the following jump command */
+jumpc 0x00000014,0x00000010
+/* Skip the following instructions by jumping to the end */
+jump 0x38
write 0x03400688,0x00000001
write 0x03500688,0x00000001
write 0x03600688,0x00000001
diff --git a/rcw.py b/rcw.py
index 863f755..c2d06f6 100755
--- a/rcw.py
+++ b/rcw.py
@@ -328,6 +328,34 @@ def build_pbi(lines):
v2 = struct.pack(endianess + 'L', p2)
subsection += v1
subsection += v2
+ elif op == 'loadc':
+ if p1 == None or p2 == None:
+ print('Error: "loadc" instruction requires two parameters')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80140000)
+ v2 = struct.pack(endianess + 'L', p1)
+ v3 = struct.pack(endianess + 'L', p2)
+ subsection += v1
+ subsection += v2
+ subsection += v3
+ elif op == 'jumpc':
+ if p1 == None or p2 == None:
+ print('Error: "jumpc" instruction requires two parameters')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80850000)
+ v2 = struct.pack(endianess + 'L', p1)
+ v3 = struct.pack(endianess + 'L', p2)
+ subsection += v1
+ subsection += v2
+ subsection += v3
+ elif op == 'jump':
+ if p1 == None:
+ print('Error: "jump" instruction requires a parameter')
+ return ''
+ v1 = struct.pack(endianess + 'L', 0x80840000)
+ v2 = struct.pack(endianess + 'L', p1)
+ subsection += v1
+ subsection += v2
elif op == 'awrite':
if p1 == None or p2 == None:
print('Error: "awrite" instruction requires two parameters')
--
2.17.1
patches/rcw-LSDK-20.04/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch 0 → 100644
View file @ c32dee74
From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:35:04 +0200
Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160asi/a050234.rcw | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw
index 72a40e4..2130709 100644
--- a/lx2160asi/a050234.rcw
+++ b/lx2160asi/a050234.rcw
@@ -4,6 +4,12 @@
*/
.pbi
+/* Load condition SVR register mask major ID */
+loadc 0x01e000a4,0x000000f0
+/* If it is rev 1, skip the following jump command */
+jumpc 0x00000014,0x00000010
+/* Skip the following instructions by jumping to the end */
+jump 0xc8
write 0x1ea1200,0x20081004
write 0x1ea1240,0x20081004
write 0x1ea1280,0x20081004
--
2.17.1
patches/rcw-LSDK-20.04/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch 0 → 100644
View file @ c32dee74
From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:36:20 +0200
Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed
1. Moves calling the workarounds to the _defaults.rcwi
2. Toggle fan-full-speed GPIO. The fan controller starts throttling when
a driver exists (i.e. kernel); in order to avoid overheating until then
enable full speed.
3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox
ConnectX-5 NICs
4. Run a009531 and a00885 on rev2.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++----
lx2160acex7/configs/lx2160a_sdboot.rcwi | 6 ------
lx2160acex7/configs/lx2160a_xspiboot.rcwi | 6 ------
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 3ea7683..7af1f5b 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -1,10 +1,6 @@
#include <../lx2160asi/lx2160a.rcwi>
MEM_PLL_CFG=3
MEM2_PLL_CFG=3
-C5_PLL_SEL=0
-C6_PLL_SEL=0
-C7_PLL_SEL=0
-C8_PLL_SEL=0
HWA_CGA_M1_CLK_SEL=1
HWA_CGB_M1_CLK_SEL=7
BOOT_LOC=26
@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1
IRQ11_08_PMUX=1
EVT20_PMUX=1
EVT43_PMUX=1
+
+/* Drive the fan full speed pin */
+.pbi
+write 0x2320000,0x20000000
+.end
+
+/* Errata for SATA controller */
+#include <../lx2160asi/a010554.rcw>
+
+/* Errata for rev 1 PCIe controller */
+#include <../lx2160asi/a011270.rcw>
+
+/* Errata a050234 - fix elastic buffer threshold in rev 1 */
+#include <../lx2160asi/a050234.rcw>
+
+/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
+#include <../lx2160asi/a009531_a008851.rcw>
diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
index d537ea5..9086ffc 100644
--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000
/* Boot Location Pointer */
#include <../lx2160asi/bootlocptr_sd.rcw>
-/* Errata for SATA controller */
-#include <../lx2160asi/a010554.rcw>
-
-/* Errata for PCIe controller */
-#include <../lx2160asi/a011270.rcw>
-
/* common PBI commands */
#include <../lx2160asi/common.rcw>
diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
index 28310c9..fa092c9 100644
--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
@@ -4,12 +4,6 @@
/* Boot Location Pointer */
#include <../lx2160asi/bootlocptr_nor.rcw>
-/* Errata for SATA controller */
-#include <../lx2160asi/a010554.rcw>
-
-/* Errata for PCIe controller */
-#include <../lx2160asi/a011270.rcw>
-
/* common PBI commands */
#include <../lx2160asi/common.rcw>
--
2.17.1
patches/rcw-LSDK-20.04/0008-lx2160a-add-generic-bootloc-section.patch 0 → 100644
View file @ c32dee74
From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 24 Mar 2020 03:42:14 +0200
Subject: [PATCH 8/8] lx2160a: add generic bootloc section
The generic bootloc section does conditional blockcopy from SD/eMMC and
SPI with some predefined addresses.
Later on if ATF is used; those addresses are modified with ATF's
create_pbl.c
With this method a single boot image is unified for all the 3 different
boot methods.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++
lx2160asi/bootlocptr.rcw | 62 +++++++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100644 lx2160asi/bootlocptr.rcw
diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
index 7af1f5b..7997d49 100644
--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
+++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
@@ -35,3 +35,15 @@ write 0x2320000,0x20000000
/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
#include <../lx2160asi/a009531_a008851.rcw>
+
+/* Unified boot location copy */
+#include <../lx2160asi/bootlocptr.rcw>
+
+/* Errata to write on scratch reg for validation */
+#include <../lx2160asi/scratchrw1.rcw>
+
+/* common PBI commands */
+#include <../lx2160asi/common.rcw>
+
+/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
+#include <../lx2160asi/flexspi_divisor_28.rcw>
diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw
new file mode 100644
index 0000000..645182f
--- /dev/null
+++ b/lx2160asi/bootlocptr.rcw
@@ -0,0 +1,62 @@
+/*
+ * Generic code for auto booting.
+ * For each section blockcopy followed by write to bootlocl then bootloch must
+ * be followed in each section since when using ATF with create_pbl script in
+ * auto mode; it counts on the sequence of to be in that order.
+ */
+
+/* Boot from SD - copy SPL Uboot to Ocram */
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0x8 << 23 then skip the following jump command */
+jumpc 0x00000014,0x04000000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 40 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x1800a000
+write 0x01e00404,0x00000000
+.end
+
+/* Boot from eMMC - copy SPL Uboot to Ocram */
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0x9 << 23 then skip the following jump command */
+jumpc 0x00000014,0x04800000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 40 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x09,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x1800a000
+write 0x01e00404,0x00000000
+.end
+
+/* XSPI boot Location Pointer */
+/*
+ * Set the boot location pointer to the NOR flash boot area.
+ */
+
+.pbi
+/* Load condition PORSR1 and mask RCW_SRC */
+loadc 0x01e00000,0x07800000
+
+/* If it is 0xf << 23 then skip the following jump command */
+jumpc 0x00000014,0x07800000
+
+/* Jump all the below instructions */
+jump 0x28 /* All instruction below including the jump are 0x190 bytes */
+
+/* blockcopy must be followed by two writes to bootlocl and bootloch */
+blockcopy 0x0f,0x00100000,0x1800a000,0x00020000
+write 0x01e00400,0x20100000
+write 0x01e00404,0x00000000
+.end
+
--
2.17.1
patches/u-boot-LSDK-20.04/0001-armv8-add-lx2160acex7-build-inclusion.patch 0 → 100644
View file @ c32dee74
From 94e3a159d46ffb7f3e3186486dd74293cc33326f Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:26:45 +0300
Subject: [PATCH 1/6] armv8: add lx2160acex7 build inclusion
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/Kconfig | 13 +++++++++++++
arch/arm/cpu/armv8/Kconfig | 2 +-
arch/arm/dts/Makefile | 3 ++-
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 958d048971..d439d42a4a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1101,6 +1101,18 @@ config TARGET_LX2160ARDB
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2160ACEX7
+ bool "Support lx2160acex7"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ help
+ Support for SolidRun LX2160A based com express type 7 module and
+ platform. The lx2160acex7 high-performance platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
config TARGET_LX2160AQDS
bool "Support lx2160aqds"
select ARCH_LX2160A
@@ -1635,6 +1647,7 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
+source "board/solidrun/lx2160a/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 92a2b58ed4..9df6ebdc1b 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -109,7 +109,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
- !TARGET_LX2160AQDS && \
+ !TARGET_LX2160AQDS && !TARGET_LX2160ACEX7 && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b9f34113ea..c5be9a52cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -347,7 +347,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
- fsl-lx2160a-qds.dtb
+ fsl-lx2160a-qds.dtb \
+ fsl-lx2160a-cex7.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
--
2.17.1
patches/u-boot-LSDK-20.04/0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch 0 → 100644
View file @ c32dee74
From dc622cf48bed312045d6a7762d166803db28dff3 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:27:46 +0300
Subject: [PATCH 2/6] armv8: lx2160acex: misc hacks to get the sources built
those hacks will be sorted out nicer in the future and this patch will
not be needed anymore
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 -
drivers/mmc/fsl_esdhc.c | 2 +-
include/configs/lx2160a_common.h | 4 ++--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 8c47d81f7f..9236be05c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -225,7 +225,6 @@ config ARCH_LX2160A
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
- select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 53277c9216..1ec74bd6ba 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -989,7 +989,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->non_removable = 0;
}
- priv->wp_enable = 1;
+ priv->wp_enable = 0;
if (IS_ENABLED(CONFIG_CLK)) {
/* Assigned clock already set clock */
--
2.17.1
patches/u-boot-LSDK-20.04/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch 0 → 100644
View file @ c32dee74
From 62af256d25d61136913a739b14452b6d35eff3dc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:29:31 +0300
Subject: [PATCH 3/6] armv8: lx2160acex7: defconfig and main platform include
This patch add lx2160acex7 main defconfig and main include file.
Notice that the defconfig doesn't support the secured boot mode where a
follow up patch will cover this.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++
include/configs/lx2160acex7.h | 85 +++++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 configs/lx2160acex7_tfa_defconfig
create mode 100644 include/configs/lx2160acex7.h
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
new file mode 100644
index 0000000000..d59de7d054
--- /dev/null
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ACEX7=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_EMC2301=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MICRON=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT2=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_E1000=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+# CONFIG_SYS_NXP_FSPI_AHB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
new file mode 100644
index 0000000000..478cd8242f
--- /dev/null
+++ b/include/configs/lx2160acex7.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#ifndef __LX2_CEX7_H
+#define __LX2_CEX7_H
+
+#include "lx2160a_common.h"
+
+/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0x2
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x5c
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160acex7_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 700
+#define VDD_MV_MAX 855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
+
+#define RGMII_PHY_ADDR1 0x01
+
+#endif
+
+/* EMC2301 */
+#define I2C_MUX_CH_EMC2301 0x01
+#define I2C_EMC2301_ADDR 0x2f
+#define I2C_EMC2301_CMD 0x40
+#define I2C_EMC2301_PWM 0x80
+
+/* EEPROM */
+#undef CONFIG_ID_EEPROM /* Fixme */
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160acex7_vdd_mv=800\0" \
+ "BOARD=lx2160acex7\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_CEX7_H */
--
2.17.1
patches/u-boot-LSDK-20.04/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch 0 → 100644
View file @ c32dee74
From f8ac0b82bf2af732251419f05b9058e78ca2dbec Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:37:22 +0300
Subject: [PATCH 5/6] armv8: lx2160acex7: lx2160acex device tree
Based on NXP's LX2160ARDB device tree; it defines -
1. MX35X based SPI flash
2. SDHC0 (SD card) and SDHC1 (eMMC)
3. 4 SATA ports that depending on SERDES configuration they can get
connected to external SATA drives
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
new file mode 100644
index 0000000000..4fbcaafb0e
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2160ACEX7 device tree source
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * Copyright 2019 SolidRun ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160ACEX7 COM express type 7 based board";
+ compatible = "fsl,lx2160acex7", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+ };
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: MT35XU512ABA1G12@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
--
2.17.1
patches/u-boot-LSDK-20.04/0007-lx2160a-load-dpl-into-0x80001000-instead-of-0x80d000.patch 0 → 100644
View file @ c32dee74
From bd927e8c93fa6fa674f0bb38b00ac0bf7dc98f44 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 4 May 2020 23:09:52 +0300
Subject: [PATCH] lx2160a: load dpl into 0x80001000 instead of 0x80d00000
and enlarge the image size to 0x1000 blocks
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160a_common.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 43198f19f8..8983e615d1 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -284,21 +284,21 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
#define SD_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80d00000 0x6800 0x800; " \
+ "mmc read 0x80001000 0x6800 0x1000; " \
"env exists mcinitcmd && env exists secureboot " \
" && mmc read 0x806C0000 0x3600 0x20 " \
"&& esbc_validate 0x806C0000;env exists mcinitcmd " \
- "&& fsl_mc lazyapply dpl 0x80d00000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#define SD2_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80d00000 0x6800 0x800; " \
+ "mmc read 0x80001000 0x6800 0x1000; " \
"env exists mcinitcmd && env exists secureboot " \
" && mmc read 0x80780000 0x3C00 0x20 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc lazyapply dpl 0x80d00000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run emmc_bootcmd;" \
"env exists secureboot && esbc_halt;"
--
2.17.1
patches/u-boot-LSDK-20.04/0008-uboot-add-nvme-commands-and-for-distroboot.patch 0 → 100644
View file @ c32dee74
From a1fddcaae71a95bd4b9963c9000b9c88b6d152d5 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 11 Nov 2019 23:45:31 +0200
Subject: [PATCH] uboot - add nvme commands and for distroboot
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
configs/lx2160acex7_tfa_defconfig | 2 ++
include/configs/lx2160a_common.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index d59de7d054..3891d2a7c4 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_NVME=y
+CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 34cc29685d..7c2d749a9e 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -306,6 +306,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(SCSI, scsi, 0) \
+ func(NVME, nvme, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
--
2.17.1
patches/u-boot-LSDK-20.04/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch 0 → 100644
View file @ c32dee74
From 4a5e1552f13acc1e8ee91b456ea37e9d39bdae01 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 13:32:09 +0200
Subject: [PATCH] armv8: lx2160acex7: Fix booting from NVMe drives
Currently NVMe is not initialized so u-boot fails to read kernel from
NVMe drive. This patch modifies default environment so it initializes
NVMe as part of default startup script...
Credit to Damjan Marion <dmarion@me.com> on fixing that on LSDK-19.09.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
include/configs/lx2160a_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index bacad51bfb..cee462ef63 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -248,6 +248,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
BOOTENV \
"mcmemsize=0x70000000\0" \
XSPI_MC_INIT_CMD \
+ "nvme_need_init=true\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
--
2.17.1
patches/u-boot-LSDK-20.04/0012-nvme-add-accessor-to-namespace-id-and-eui64.patch 0 → 100644
View file @ c32dee74
From 89eaac0cd956214260038ed39be675f9a3af220a Mon Sep 17 00:00:00 2001
From: Patrick Wildt <patrick@blueri.se>
Date: Thu, 3 Oct 2019 13:48:47 +0200
Subject: [PATCH 3/5] nvme: add accessor to namespace id and eui64
This adds a function which can be used by e.g. EFI to retrieve
the namespace identifier and EUI64. For that it adds the EUI64
to its driver internal namespace structure and copies the EUI64
during namespace identification.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit c50b2883dfc1ce355dc37238741ef97cd2c5d000)
Signed-off-by: Olof Johansson <olof@lixom.net>
---
drivers/nvme/nvme.c | 13 +++++++++++++
drivers/nvme/nvme.h | 1 +
include/nvme.h | 12 ++++++++++++
3 files changed, 26 insertions(+)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 47f101e280..ee6b581d9e 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -621,6 +621,18 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
return 0;
}
+int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64)
+{
+ struct nvme_ns *ns = dev_get_priv(udev);
+
+ if (ns_id)
+ *ns_id = ns->ns_id;
+ if (eui64)
+ memcpy(eui64, ns->eui64, sizeof(ns->eui64));
+
+ return 0;
+}
+
int nvme_scan_namespace(void)
{
struct uclass *uc;
@@ -657,6 +669,7 @@ static int nvme_blk_probe(struct udevice *udev)
if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
return -EIO;
+ memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64));
flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
ns->flbas = flbas;
ns->lba_shift = id->lbaf[flbas].ds;
diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h
index 922f7abfe8..0e8cb221a7 100644
--- a/drivers/nvme/nvme.h
+++ b/drivers/nvme/nvme.h
@@ -637,6 +637,7 @@ struct nvme_ns {
struct list_head list;
struct nvme_dev *dev;
unsigned ns_id;
+ u8 eui64[8];
int devnum;
int lba_shift;
u8 flbas;
diff --git a/include/nvme.h b/include/nvme.h
index 2c3d14d241..2cdf8ce320 100644
--- a/include/nvme.h
+++ b/include/nvme.h
@@ -78,4 +78,16 @@ int nvme_scan_namespace(void);
*/
int nvme_print_info(struct udevice *udev);
+/**
+ * nvme_get_namespace_id - return namespace identifier
+ *
+ * This returns the namespace identifier.
+ *
+ * @udev: NVMe controller device
+ * @ns_id: Place where to put the name space identifier
+ * @eui64: Place where to put the IEEE Extended Unique Identifier
+ * @return: 0 on success, -ve on error
+ */
+int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64);
+
#endif /* __NVME_H__ */
--
2.22.GIT
patches/u-boot-LSDK-20.04/0013-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch 0 → 100644
View file @ c32dee74
From 7846531d2ad011cb2d025aac92aeefb3dffec429 Mon Sep 17 00:00:00 2001
From: Patrick Wildt <patrick@blueri.se>
Date: Wed, 16 Oct 2019 23:22:50 +0200
Subject: [PATCH 4/5] nvme: flush dcache on both r/w, and the prp list
It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
before. Thus we need to make sure to flush it also on reads, since
it's possible that the cache is automatically flused to memory after
the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
data. Also add a missing dcache flush for the prp list.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit 8c403402ca691c967516481b6bc2c879d683a73d)
Signed-off-by: Olof Johansson <olof@lixom.net>
---
drivers/nvme/nvme.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index ee6b581d9e..53ff6e89aa 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -123,6 +123,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
}
*prp2 = (ulong)dev->prp_pool;
+ flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
+ dev->prp_entry_num * sizeof(u64));
+
return 0;
}
@@ -705,9 +708,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
u64 total_lbas = blkcnt;
- if (!read)
- flush_dcache_range((unsigned long)buffer,
- (unsigned long)buffer + total_len);
+ flush_dcache_range((unsigned long)buffer,
+ (unsigned long)buffer + total_len);
c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
c.rw.flags = 0;
--
2.22.GIT
patches/u-boot-LSDK-20.04/0014-nvme-use-page-aligned-buffer-for-identify-command.patch 0 → 100644
View file @ c32dee74
From 489ce106e10a3df390ea19267729e4102e88a63a Mon Sep 17 00:00:00 2001
From: Patrick Wildt <patrick@blueri.se>
Date: Wed, 16 Oct 2019 08:42:04 +0200
Subject: [PATCH 5/5] nvme: use page-aligned buffer for identify command
Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers. Even though the spec
seems to allow having admin queue commands on non page-aligned
buffers, it seems to not be possible on my i.MX8MQ board with a
a Silicon Power P34A80. Since all of the NVMe drivers I have seen
always do admin commands on a page-aligned buffer, which does work
on my system, it makes sense for us to do that as well.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit 2f83481dff9c4f253a6ac341911d78d4984ca07b)
Signed-off-by: Olof Johansson <olof@lixom.net>
---
drivers/nvme/nvme.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 53ff6e89aa..f915817aaa 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -583,14 +583,19 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
static int nvme_get_info_from_identify(struct nvme_dev *dev)
{
- ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl));
- struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf;
+ struct nvme_id_ctrl *ctrl;
int ret;
int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
+ ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl));
+ if (!ctrl)
+ return -ENOMEM;
+
ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
- if (ret)
+ if (ret) {
+ free(ctrl);
return -EIO;
+ }
dev->nn = le32_to_cpu(ctrl->nn);
dev->vwc = ctrl->vwc;
@@ -621,6 +626,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
dev->max_transfer_shift = 20;
}
+ free(ctrl);
return 0;
}
@@ -661,16 +667,21 @@ static int nvme_blk_probe(struct udevice *udev)
struct blk_desc *desc = dev_get_uclass_platdata(udev);
struct nvme_ns *ns = dev_get_priv(udev);
u8 flbas;
- ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns));
- struct nvme_id_ns *id = (struct nvme_id_ns *)buf;
struct pci_child_platdata *pplat;
+ struct nvme_id_ns *id;
+
+ id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
+ if (!id)
+ return -ENOMEM;
memset(ns, 0, sizeof(*ns));
ns->dev = ndev;
/* extract the namespace id from the block device name */
ns->ns_id = trailing_strtol(udev->name) + 1;
- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
+ if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) {
+ free(id);
return -EIO;
+ }
memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64));
flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
@@ -689,6 +700,7 @@ static int nvme_blk_probe(struct udevice *udev)
memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
+ free(id);
return 0;
}
--
2.22.GIT
patches/u-boot-LSDK-20.04/0016-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch 0 → 100644
View file @ c32dee74
From d2e368b0df941fe8958df4f44dd2c7cfc32d0fb8 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 23 Mar 2020 12:53:48 +0200
Subject: [PATCH 16/16] lx2160acex7: pcie fixup and boot from eMMC print
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/lx2160a.c | 66 +++++++++++++++++++++++++++++++
configs/lx2160acex7_tfa_defconfig | 3 +-
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
index 3713e91351..b7211a2d5c 100644
--- a/board/solidrun/lx2160a/lx2160a.c
+++ b/board/solidrun/lx2160a/lx2160a.c
@@ -20,6 +20,8 @@
#include <efi_loader.h>
#include <asm/arch/mmu.h>
#include <hwconfig.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/config.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include "../../freescale/common/vid.h"
@@ -106,6 +108,66 @@ int board_early_init_f(void)
#ifdef CONFIG_OF_BOARD_FIXUP
int board_fix_fdt(void *fdt)
{
+ char *reg_name, *old_str, *new_str;
+ const char *reg_names;
+ int names_len, old_str_len, new_str_len, remaining_str_len;
+ struct str_map {
+ char *old_str;
+ char *new_str;
+ } reg_names_map[] = {
+ { "ccsr", "dbi" },
+ { "pf_ctrl", "ctrl" }
+ };
+ int off = -1, i;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ return 0;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
+ strlen("fsl,ls-pcie") + 1);
+
+ reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
+ if (!reg_names)
+ continue;
+
+ reg_name = (char *)reg_names;
+ remaining_str_len = names_len - (reg_name - reg_names);
+ i = 0;
+ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
+ old_str = reg_names_map[i].old_str;
+ new_str = reg_names_map[i].new_str;
+ old_str_len = strlen(old_str);
+ new_str_len = strlen(new_str);
+ if (memcmp(reg_name, old_str, old_str_len) == 0) {
+ /* first only leave required bytes for new_str
+ * and copy rest of the string after it
+ */
+ memcpy(reg_name + new_str_len,
+ reg_name + old_str_len,
+ remaining_str_len - old_str_len);
+ /* Now copy new_str */
+ memcpy(reg_name, new_str, new_str_len);
+ names_len -= old_str_len;
+ names_len += new_str_len;
+ i++;
+ }
+
+ reg_name = memchr(reg_name, '\0', remaining_str_len);
+ if (!reg_name)
+ break;
+
+ reg_name += 1;
+
+ remaining_str_len = names_len - (reg_name - reg_names);
+ }
+
+ fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie");
+ }
+
return 0;
}
#endif
@@ -135,6 +197,10 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
+ } else {
+ puts("FlexSPI DEV#0\n");
}
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index 89a47adb23..2a3441d263 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LX2160ACEX7=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -58,7 +59,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
-CONFIG_PHY_ATHEROS=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_E1000=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
--
2.17.1
runme.sh
View file @ c32dee74
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