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Commit c9a2a04d authored by Josua Mayer's avatar Josua Mayer
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linux: add preview device-tree for cex6 internal reference platform

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patches/linux-LSDK-21.08/0075-arm64-dts-add-solidrun-lx2160a-cex6-evaluation-board.patch 0 → 100644
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From 03682a069de99113495db38995144d46e89b76be Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 27 Aug 2023 13:57:42 +0200
Subject: [PATCH] arm64: dts: add solidrun lx2160a-cex6 evaluation board
preview
The CEX6 is an internal evaluation platform.
Current support is incomplete and should be cleaned up, including
correct split between module and carrier dts.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/fsl-lx2160a-cex6.dts | 158 +++++++++
.../boot/dts/freescale/fsl-lx2160a-cex6.dtsi | 324 ++++++++++++++++++
3 files changed, 483 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 3896283a75cd..35339b4af372 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex6.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dts
new file mode 100644
index 000000000000..833699cb7f8a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dts
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160A-CEx6 (internal) evaluation board
+//
+// Copyright 2019-2023 SolidRun Ltd.
+
+#include "fsl-lx2160a-cex6.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "SolidRun LX2160A FLIR Carrier";
+ compatible = "solidrun,lx2160a-cex6", "fsl,lx2160a";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+/*
+ key {
+ label = "power";
+ linux,can-disable;
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ };
+*/
+ };
+
+ sfp1: sfp-1 { // J67
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c3_bb>;
+ mod-def0-gpio = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp2: sfp-2 { // J49
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ mod-def0-gpio = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp3: sfp-3 { // J69
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp2_i2c>;
+ mod-def0-gpio = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ i2c3_bb: i2c-3-bb {
+ compatible = "i2c-gpio";
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+};
+
+&dpmac3 {
+ status = "okay";
+ phys = <&serdes_1 7>;
+ phy-names = "serdes";
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "10gbase-r";
+};
+
+&dpmac4 {
+ status = "okay";
+ phys = <&serdes_1 6>;
+ phy-names = "serdes";
+ managed = "in-band-status";
+ sfp = <&sfp2>;
+};
+
+&dpmac5 {
+ status = "okay";
+ phys = <&serdes_1 5>;
+ phy-names = "serdes";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+};
+
+&dpmac6 {
+ status = "okay";
+ phys = <&serdes_1 4>;
+ phy-names = "serdes";
+ managed = "in-band-status";
+ sfp = <&sfp3>;
+};
+
+&esdhc0 {
+ no-1-8-v;
+ status = "okay";
+};
+
+&pcs_mdio3 {
+ status = "okay";
+};
+
+&pcs_mdio4 {
+ status = "okay";
+};
+
+&pcs_mdio5 {
+ status = "okay";
+};
+
+&pcs_mdio6 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
+&serdes_1 {
+ /* disable driver for lanes A-D */
+ fsl,unmanaged-lanes = <0x0f>;
+ status = "okay";
+};
+
+&serdes_2 {
+ status = "disabled";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
new file mode 100644
index 000000000000..7c21206eb7e3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160A-CEx7
+//
+// Copyright 2019-2023 SolidRun Ltd.
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160A COM Express Type 6 module";
+ compatible = "solidrun,lx2160a-cex6", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ };
+
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "RT7290";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&can0 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&dpmac17 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <1>;
+ qca,smarteee-tw-us-1g = <24>;
+ };
+
+ aquantia_phy1: ethernet-phy@8 {
+ /* AQR113 PHY */
+ compatible = "ethernet-phy-ieee802.3-c45";
+// interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x8>;
+ };
+
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ i2c-switch@77 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ /* SPD DDR CH1 */
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+
+ eeprom@53 {
+ /* SPD DDR CH2 */
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* not assembled by default */
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ regulator@5c {
+ compatible = "lltc,ltc3882";
+ reg = <0x5c>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ current-mon@40 { //GVDD 1.2V
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@44 { //SD_SVDD 0.9V
+ compatible = "ti,ina220";
+ reg = <0x44>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@41 { //SD_OVDD 1.8V
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@45 { //OVDD 1.8V
+ compatible = "ti,ina220";
+ reg = <0x45>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@42 { //0.7V AQR113 PHY
+ compatible = "ti,ina220";
+ reg = <0x48>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@48 { //5V
+ compatible = "ti,ina220";
+ reg = <0x49>;
+ shunt-resistor = <1500>;
+ };
+
+ current-mon@4C { //3.3V
+ compatible = "ti,ina220";
+ reg = <0x4D>;
+ shunt-resistor = <1500>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ rtc_wd@d0 {
+ compatible = "st,m41t0";
+ reg = <0xd0>;
+ };
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* not assembled */
+ pca9536: gpio@41 {
+ compatible = "nxp,pca9534";
+ reg = <0x41>;
+ gpio-controller;
+ pinctrl-names = "default";
+ };
+ };
+
+ sfp2_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pca9655: gpio@40 {
+ compatible = "nxp,pca9655";
+ reg = <0x40>;
+ gpio-controller;
+ pinctrl-names = "default";
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+};
+
+&i2c3 {
+ status = "disabled";
+};
+
+&fspi {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
+ };
+
+ mt35xu512aba1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
+ };
+
+};
+&dspi2 {
+ status = "okay";
+
+ w25q32fvzpig0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ };
+
+ w25q32fvzpig1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ };
+
+ w25q32fvzpig2: flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <2>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ };
+
+ w25q32fvzpig3: dflash@3 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <3>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
2.35.3
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