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Commit ccce7bb0 authored by Rabeeh Khoury's avatar Rabeeh Khoury
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Added TI 25/100Gbps retimer support, and restructure RCW SD config 

1. Added TI based retimer initialization on 25Gbp SERDES configuration.
Note that those retimers are available on ClearFog CX revision 1.3 and
newer
2. Restructure SERDES configuration files
Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent cd56147f
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patches/mc-utils/0003-lx2160acex7-add-single-100Gbps-support.patch 0 → 100644
View file @ ccce7bb0
From a8aff1e0a111da4df0fc9eac0d5d809507edcf18 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 17:01:15 +0200
Subject: [PATCH] lx2160acex7: add single 100Gbps support
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
config/lx2160a/CEX7/dpc-single-100g.dts | 82 +++
.../lx2160a/CEX7/dpl-eth.single-100g.19.dts | 500 ++++++++++++++++++
2 files changed, 582 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-single-100g.dts
create mode 100644 config/lx2160a/CEX7/dpl-eth.single-100g.19.dts
diff --git a/config/lx2160a/CEX7/dpc-single-100g.dts b/config/lx2160a/CEX7/dpc-single-100g.dts
new file mode 100644
index 0000000..e3e76c3
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-single-100g.dts
@@ -0,0 +1,82 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@1 {
+ link_type = "MAC_LINK_TYPE_FIXED";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-eth.single-100g.19.dts b/config/lx2160a/CEX7/dpl-eth.single-100g.19.dts
new file mode 100644
index 0000000..86a945b
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-eth.single-100g.19.dts
@@ -0,0 +1,500 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ dpl-version = <0xa>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+ dprc@1 {
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
+ /* ------------ DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0x0>;
+ };
+
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x1 0x11>;
+ };
+
+
+ /* ------------ DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0x0 0x1>;
+ };
+
+ /* ------------ DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+
+ /* ------------ DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+
+ /* ------------ DPCON --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ obj@700 {
+ obj_name = "dpseci@0";
+ };
+
+ /* ------------ DPRTC --------------*/
+ obj@800 {
+ obj_name="dprtc@0";
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ /* ------------ DPNI --------------*/
+ dpni@0 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@1 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@2 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@3 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@4 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@5 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@6 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@7 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpni@8 {
+ options = "DPNI_OPT_HAS_KEY_MASKING";
+ num_queues = <0x10>;
+ num_tcs = <0x1>;
+ };
+ dpmac@1 {
+ };
+ dpmac@2 {
+ };
+
+ dpmac@17 {
+ };
+
+ /* ------------ DPBP --------------*/
+ dpbp@0 {
+ };
+
+ dpbp@1 {
+ };
+
+
+ /* ------------ DPIO --------------*/
+ dpio@0 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ /* ------------ DPMCP --------------*/
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+
+ /* ------------ DPCON --------------*/
+ dpcon@0 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ num_priorities = <0x2>;
+ };
+ dpcon@16 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ num_priorities = <0x2>;
+ };
+
+ /* ------------ DPSECI --------------*/
+ dpseci@0 {
+ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
+ options = "DPSECI_OPT_HAS_CG";
+ };
+
+ /* ------------ DPRTC --------------*/
+ dprtc@0 {
+ compatible="fsl,dprtc";
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ connection@1 {
+ endpoint1 = "dpni@0";
+ endpoint2 = "dpmac@17";
+ };
+/* connection@2 {
+ endpoint1 = "dpni@1";
+ endpoint2 = "dpmac@1";
+ };
+*/
+ };
+};
+
--
2.25.1
patches/rcw-LSDK-20.04/0011-lx210acex7-25Gbps-retimer-and-restructure-config.patch 0 → 100644
View file @ ccce7bb0
From d4a721d712d8fd9f03be2965e0b37bcd33148bdc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 16:44:35 +0200
Subject: [PATCH] lx210acex7: 25Gbps retimer and restructure config
1. Split SERDES configuration files that each SERDES block from the
available 3 can be separately configured.
2. Added SD1 lanes e,f,g,h include files that configures the SERDES
lanes to suppoer 25Gbps rate with external retimer (using ClearFog CX
revision 1.3 and newer).
3. Added bus speeds 750 and 800MHz which are required to get wire speed
DPDK performance on a 100Gbps link.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_13_5_2.rcwi | 3 ---
lx2160acex7/configs/lx2160a_17_4_2.rcwi | 7 ------
.../configs/lx2160a_2000_750_3200.rcwi | 9 +++++++
.../configs/lx2160a_2000_800_3200.rcwi | 9 +++++++
lx2160acex7/configs/lx2160a_8_5_0.rcwi | 7 ------
lx2160acex7/configs/lx2160a_SD1_13.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_14.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_17.rcwi | 3 +++
lx2160acex7/configs/lx2160a_SD1_2.rcwi | 4 +++
...x2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} | 2 --
...{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} | 3 ---
lx2160acex7/configs/lx2160a_SD2_5.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_0.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_2.rcwi | 1 +
lx2160acex7/configs/lx2160a_SD3_3.rcwi | 1 +
.../lx2160a_cex7_hc_sd1_lanes_e_f.rcwi | 24 ++++++++++++++++++
.../lx2160a_cex7_hc_sd1_lanes_g_h.rcwi | 25 +++++++++++++++++++
17 files changed, 84 insertions(+), 22 deletions(-)
delete mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
delete mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
delete mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_13.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_14.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_17.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD1_2.rcwi
rename lx2160acex7/configs/{lx2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} (78%)
rename lx2160acex7/configs/{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} (79%)
create mode 100644 lx2160acex7/configs/lx2160a_SD2_5.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_0.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_2.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_SD3_3.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
deleted file mode 100644
index 76f44bc..0000000
--- a/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+++ /dev/null
@@ -1,3 +0,0 @@
-SRDS_PRTCL_S1=13
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
deleted file mode 100644
index 358972d..0000000
--- a/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+++ /dev/null
@@ -1,7 +0,0 @@
-SRDS_PRTCL_S1=17
-SRDS_PRTCL_S2=4
-SRDS_PRTCL_S3=2
-
-/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
-/*SRDS_PLL_REF_CLK_SEL_S1=2*/
-
diff --git a/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
new file mode 100644
index 0000000..84d544d
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
@@ -0,0 +1,9 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=15
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
diff --git a/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
new file mode 100644
index 0000000..31d7cfd
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
@@ -0,0 +1,9 @@
+CGA_PLL1_RAT=20
+CGA_PLL2_RAT=20
+CGB_PLL1_RAT=20
+CGB_PLL2_RAT=9
+
+SYS_PLL_RAT=16
+
+MEM_PLL_RAT=32
+MEM2_PLL_RAT=32
diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
deleted file mode 100644
index 62ff153..0000000
--- a/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+++ /dev/null
@@ -1,7 +0,0 @@
-SRDS_PRTCL_S1=8 /* should be 8 */
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=0
-
-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
-SRDS_PLL_REF_CLK_SEL_S1=2
-SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_SD1_13.rcwi b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
new file mode 100644
index 0000000..61b1eea
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=13
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_14.rcwi b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
new file mode 100644
index 0000000..75e3fab
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=14
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_17.rcwi b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
new file mode 100644
index 0000000..5504271
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
@@ -0,0 +1,3 @@
+SRDS_PRTCL_S1=17
+#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
+#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
diff --git a/lx2160acex7/configs/lx2160a_SD1_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
new file mode 100644
index 0000000..0f013e6
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
@@ -0,0 +1,4 @@
+SRDS_PRTCL_S1=2
+
+SRDS_PLL_REF_CLK_SEL_S1=0
+SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
similarity index 78%
rename from lx2160acex7/configs/lx2160a_20_5_2.rcwi
rename to lx2160acex7/configs/lx2160a_SD1_20.rcwi
index c2c7bea..053aee7 100644
--- a/lx2160acex7/configs/lx2160a_20_5_2.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
@@ -1,6 +1,4 @@
SRDS_PRTCL_S1=20
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
similarity index 79%
rename from lx2160acex7/configs/lx2160a_8_5_2.rcwi
rename to lx2160acex7/configs/lx2160a_SD1_8.rcwi
index d7d707a..abd6dfd 100644
--- a/lx2160acex7/configs/lx2160a_8_5_2.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
@@ -1,7 +1,4 @@
SRDS_PRTCL_S1=8 /* should be 8 */
-SRDS_PRTCL_S2=5
-SRDS_PRTCL_S3=2
-
SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
SRDS_PLL_REF_CLK_SEL_S1=2
SRDS_PLL_PD_PLL1=1
diff --git a/lx2160acex7/configs/lx2160a_SD2_5.rcwi b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
new file mode 100644
index 0000000..559a90c
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S2=5
diff --git a/lx2160acex7/configs/lx2160a_SD3_0.rcwi b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
new file mode 100644
index 0000000..1904856
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=0
diff --git a/lx2160acex7/configs/lx2160a_SD3_2.rcwi b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
new file mode 100644
index 0000000..b9c3e6f
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=2
diff --git a/lx2160acex7/configs/lx2160a_SD3_3.rcwi b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
new file mode 100644
index 0000000..4695755
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
@@ -0,0 +1 @@
+SRDS_PRTCL_S3=3
diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
new file mode 100644
index 0000000..d870a4b
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
@@ -0,0 +1,24 @@
+/*
+ * SERDES tuning based on the following hardware -
+ * - SolidRun COM express type 7 revision 1.7 and newer
+ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
+ */
+
+.pbi
+/* Lane E (SD1 TX/RX 3) */
+write 0x01EA0C28,0x00000000
+write 0x01EA0C30,0x20868120
+write 0x01EA0C34,0x23000000
+write 0x01EA0C68,0x80000000
+write 0x01EA0C74,0x00002020
+write 0x01EA0C80,0x00008000
+
+/* Lane F (SD1 TX/RX 2)*/
+write 0x01EA0D28,0x00000000
+write 0x01EA0D30,0x20868120
+write 0x01EA0D34,0x23000000
+write 0x01EA0D68,0x80000000
+write 0x01EA0D74,0x00002020
+write 0x01EA0D80,0x00008000
+.end
+
diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
new file mode 100644
index 0000000..4097b77
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
@@ -0,0 +1,25 @@
+/*
+ * SERDES tuning based on the following hardware -
+ * - SolidRun COM express type 7 revision 1.7 and newer
+ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
+ */
+
+.pbi
+/* Lane G (SD1 TX/RX 1)*/
+write 0x01EA0E28,0x00000000
+write 0x01EA0E30,0x20818120
+write 0x01EA0E34,0x23000000
+write 0x01EA0E68,0x80000000
+write 0x01EA0E74,0x00002020
+write 0x01EA0E80,0x00008000
+
+/* Lane H (SD1 TX/RX 0)*/
+write 0x01EA0F28,0x00000000
+write 0x01EA0F30,0x20818120
+write 0x01EA0F34,0x23000000
+write 0x01EA0F68,0x80000000
+write 0x01EA0F74,0x00002020
+write 0x01EA0F80,0x00008000
+
+.end
+
--
2.25.1
patches/u-boot-LSDK-20.04/0023-lx2160acex7-add-25Gbps-TI-retimer-configuration.patch 0 → 100644
View file @ ccce7bb0
From ae9bf5e00231fb5957e81f1e16289a9eae707f03 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 19:24:35 +0200
Subject: [PATCH] lx2160acex7: add 25Gbps TI retimer configuration
ClearFog CX revision 1.3 and newer adds two TI 4 channels retimers on
egress and ingress.
On egress the retimer is configured to be on I2C address 0x22 and the
other on I2C address 0x23.
This patch configures the egress retimer pre and post key and the
amplitude.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 110 +++++++++++++++++------
include/configs/lx2160acex7.h | 2 +-
2 files changed, 85 insertions(+), 27 deletions(-)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 97e414838f..f335b4207a 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -12,6 +12,7 @@
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <i2c.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
@@ -20,6 +21,65 @@
DECLARE_GLOBAL_DATA_PTR;
+int select_i2c_ch_pca9547(u8 ch);
+
+void setup_retimer_25g(int chnum)
+{
+ int i, ret;
+ u8 reg;
+ struct udevice *dev;
+
+ select_i2c_ch_pca9547(0xb); /* SMB_CLK / DATA interface */
+ /*
+ * Assumption is that LX2 TX --> RT1 RX is at 0x22 and
+ * RT2 TX --> LX2 RX is at 0x23.
+ */
+ ret = i2c_get_chip_for_busnum(0, 0x23, 1, &dev);
+ if (ret) {
+ /*
+ * On HoneyComb and ClearFog CX ver 1.1 / 1.2 there is no retimer
+ * assembled; silently return.
+ */
+ return;
+ }
+ ret = dm_i2c_read(dev, 0xf1, &reg, 1); /* Get full device ID */
+ if (ret) {
+ printf ("ERROR: Could not get retimer device ID\n");
+ return;
+ }
+ if (reg != 0x10) {
+ printf ("ERROR : DS250DF410 retimer not found\n");
+ return;
+ }
+ printf ("Found retimer... Setting up channels 0..%d as 25Gbps\n",chnum - 1);
+ dm_i2c_reg_write(dev, 0xff, 0x1); /* Enable channel specific access */
+ /*
+ * Setup 25Gbps channel on 0..chnum.
+ * Notice that the ingress retimer is mirrorly mapped with the SERDES
+ * number, so SERDES #0 is connected to channel #3, SERDES 1 to channel
+ * #2 ...
+ */
+ for (i = 0 ; i < chnum; i++) { /* Setup channels 0..chnum as 25g */
+ dm_i2c_reg_write(dev, 0xfc, 1 << i);
+ dm_i2c_reg_write(dev, 0x00, 0x4); /* Reset channel registers */
+ dm_i2c_reg_write(dev, 0x0a, 0xc); /* Assert CDR reset */
+
+ printf ("Setting main cursor to 0xf\n");
+ dm_i2c_reg_write(dev, 0x3d, 0x8f); /* Enable pre/post and set main cursor to 0xf */
+ dm_i2c_reg_write(dev, 0x3e, 0x44); /* Set pre-cursor to -4 */
+ if (i == 0)
+ /* Set post-cursor of channel #0 to -4 */
+ dm_i2c_reg_write(dev, 0x3f, 0x44);
+ else
+ /* Set all other channels pre-cursor to -1 */
+ dm_i2c_reg_write(dev, 0x3f, 0x41);
+ printf ("Releasing CDR\n");
+ dm_i2c_reg_write(dev, 0x0a, 0x00); /* Release CDR */
+ }
+
+ /* TODO: Setup other channels as 10Gbps */
+}
+
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
@@ -45,35 +105,33 @@ int board_eth_init(bd_t *bis)
RGMII_PHY_ADDR1);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
switch (srds_s1) {
- case 3:
- case 5:
- case 8:
- case 13:
- case 14:
- case 15:
- case 17:
- case 20:
- case 23:
- wriop_set_phy_address(WRIOP1_DPMAC17, 0,
- RGMII_PHY_ADDR1);
- break;
-
- default:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 17:
+ case 21:
+ /* Setup 25gb retimer on lanes e,f,g,h */
+ setup_retimer_25g(4);
+ break;
+ case 18:
+ case 19:
+ /* Setup 25gb retimer on lanes e,f and 10g on g,h */
+ setup_retimer_25g(2);
+ break;
+
+ default:
printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
srds_s1);
- goto next;
}
- for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ interface = wriop_get_enet_if(WRIOP1_DPMAC17);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(WRIOP1_DPMAC17, dev);
}
next:
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
index 310168db47..de075eaeaa 100644
--- a/include/configs/lx2160acex7.h
+++ b/include/configs/lx2160acex7.h
@@ -11,7 +11,7 @@
/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
/* VID */
-#define I2C_MUX_CH_VOL_MONITOR 0x2
+#define I2C_MUX_CH_VOL_MONITOR 0xa /* Channel 2 */
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x5c
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
--
2.25.1
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