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Commit db443a11 authored by Josua Mayer's avatar Josua Mayer
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linux: backport serdes protocol switching driver from mainline 

Signed-off-by: default avatarJosua Mayer <josua@solid-run.com>
parent 33cddb76
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Showing with 2570 additions and 6 deletions
configs/linux/lx2k_additions.config
View file @ db443a11
......@@ -43,7 +43,7 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_SFP=y
CONFIG_PHY_FSL_SERDES_28G=y
CONFIG_PHY_FSL_LYNX_28G=y
CONFIG_I40E=y
CONFIG_I40EVF=y
CONFIG_IAVF=y
......
patches/linux-LSDK-21.08/0033-Revert-serdes-driver.patch 0 → 100644
View file @ db443a11
From 2bff56857b59ae848f8d186845eb1c51b815caaf Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 10:20:12 +0200
Subject: [PATCH 33/45] Revert serdes driver
Revert "dpaa2-eth: configure MAC XIF_MODE register appropriately for rgmii modes"
Revert "dpaa2-eth: configure the MAC XIF_MODE register on protocol change"
Revert "dpaa2-eth: configure the SerDes phy on a protocol change"
Revert "phy: add support for the Layerscape SerDes 28G"
Revert "arm64: dts: lx2160a: describe the SerDes block #1"
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 -
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 42 --
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 103 ++--
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 3 -
drivers/phy/freescale/Kconfig | 8 -
drivers/phy/freescale/Makefile | 1 -
drivers/phy/freescale/phy-fsl-serdes-28g.c | 521 ------------------
7 files changed, 34 insertions(+), 648 deletions(-)
delete mode 100644 drivers/phy/freescale/phy-fsl-serdes-28g.c
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 440e94f24c25..74ae703e0f53 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -63,25 +63,21 @@ sfp3: sfp-3 {
&dpmac7 {
sfp = <&sfp0>;
managed = "in-band-status";
- phys = <&serdes1_lane_d>;
};
&dpmac8 {
sfp = <&sfp1>;
managed = "in-band-status";
- phys = <&serdes1_lane_c>;
};
&dpmac9 {
sfp = <&sfp2>;
managed = "in-band-status";
- phys = <&serdes1_lane_b>;
};
&dpmac10 {
sfp = <&sfp3>;
managed = "in-band-status";
- phys = <&serdes1_lane_a>;
};
&emdio2 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 53e5881afd36..fd14b4c5b9fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -613,48 +613,6 @@ soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
- serdes_1: serdes_phy@1ea0000 {
- compatible = "fsl,serdes-28g";
- reg = <0x00 0x1ea0000 0x0 0x1e30>;
- #address-cells = <1>;
- #size-cells = <0>;
- #phy-cells = <1>;
-
- serdes1_lane_a: phy@0 {
- reg = <0>;
- #phy-cells = <0>;
- };
- serdes1_lane_b: phy@1 {
- reg = <1>;
- #phy-cells = <0>;
- };
- serdes1_lane_c: phy@2 {
- reg = <2>;
- #phy-cells = <0>;
- };
- serdes1_lane_d: phy@3 {
- reg = <3>;
- #phy-cells = <0>;
- };
- serdes1_lane_e: phy@4 {
- reg = <4>;
- #phy-cells = <0>;
- };
- serdes1_lane_f: phy@5 {
- reg = <5>;
- #phy-cells = <0>;
- };
- serdes1_lane_g: phy@6 {
- reg = <6>;
- #phy-cells = <0>;
- };
- serdes1_lane_h: phy@7 {
- reg = <7>;
- #phy-cells = <0>;
- };
- };
-
-
serdes_2: serdes_phy@1eb0000 {
compatible = "fsl,serdes-28g";
reg = <0x00 0x1eb0000 0x0 0x1e30>;
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index 2ec4c940dc99..b4d8dcb5e74b 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -4,7 +4,6 @@
#include <linux/fsl/mc.h>
#include <linux/msi.h>
#include <linux/acpi.h>
-#include <linux/phy/phy.h>
#include <linux/property.h>
#include <linux/leds.h>
@@ -108,12 +107,46 @@ static int dpaa2_mac_get_if_mode(struct fwnode_handle *dpmac_node,
return err;
}
+static bool dpaa2_mac_phy_mode_mismatch(struct dpaa2_mac *mac,
+ phy_interface_t interface)
+{
+ switch (interface) {
+ /* We can switch between SGMII and 1000BASE-X at runtime with
+ * pcs-lynx
+ */
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ if (mac->pcs &&
+ (mac->if_mode == PHY_INTERFACE_MODE_SGMII ||
+ mac->if_mode == PHY_INTERFACE_MODE_1000BASEX))
+ return false;
+ return interface != mac->if_mode;
+
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ return (interface != mac->if_mode);
+ default:
+ return true;
+ }
+}
+
static void dpaa2_mac_validate(struct phylink_config *config,
unsigned long *supported,
struct phylink_link_state *state)
{
+ struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ dpaa2_mac_phy_mode_mismatch(mac, state->interface)) {
+ goto empty_set;
+ }
+
phylink_set_port_modes(mask);
phylink_set(mask, Autoneg);
phylink_set(mask, Pause);
@@ -166,7 +199,6 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
{
struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
struct dpmac_link_state *dpmac_state = &mac->state;
- u32 if_mode = 0, orig, tmp;
int err;
if (state->an_enabled)
@@ -179,31 +211,6 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
if (err)
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
-
- switch (state->interface) {
- case PHY_INTERFACE_MODE_10GBASER:
- case PHY_INTERFACE_MODE_USXGMII:
- if_mode = 0x1;
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- if_mode = 0x3;
- break;
- default:
- netdev_err(mac->net_dev, "%s: unhandled link mode %i, expect rx/tx errors!\n", __func__, state->interface);
- break;
- }
-
- orig = ioread32(mac->if_mode_reg);
- tmp = orig & ~0x3;
- tmp |= if_mode;
- iowrite32(tmp, mac->if_mode_reg);
-
- err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface);
- if (err)
- netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err);
}
static void dpaa2_mac_link_up(struct phylink_config *config,
@@ -263,37 +270,11 @@ static void dpaa2_mac_link_down(struct phylink_config *config,
led_set_brightness(mac->link_status_led, LED_OFF);
}
-static int dpaa2_mac_prepare(struct phylink_config *config, unsigned int mode,
- phy_interface_t interface)
-{
- struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
-
- dpaa2_mac_link_down(config, mode, interface);
-
- if (mac->serdes_phy)
- phy_power_off(mac->serdes_phy);
-
- return 0;
-}
-
-static int dpaa2_mac_finish(struct phylink_config *config, unsigned int mode,
- phy_interface_t interface)
-{
- struct dpaa2_mac *mac = phylink_to_dpaa2_mac(config);
-
- if (mac->serdes_phy)
- phy_power_on(mac->serdes_phy);
-
- return 0;
-}
-
static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
.validate = dpaa2_mac_validate,
.mac_config = dpaa2_mac_config,
.mac_link_up = dpaa2_mac_link_up,
.mac_link_down = dpaa2_mac_link_down,
- .mac_prepare = dpaa2_mac_prepare,
- .mac_finish = dpaa2_mac_finish,
};
static int dpaa2_pcs_create(struct dpaa2_mac *mac,
@@ -347,7 +328,6 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
{
struct net_device *net_dev = mac->net_dev;
struct fwnode_handle *dpmac_node;
- struct phy *serdes_phy = NULL;
struct phylink *phylink;
int err;
@@ -364,14 +344,6 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
return -EINVAL;
mac->if_mode = err;
- if (!phy_interface_mode_is_rgmii(mac->if_mode) &&
- is_of_node(dpmac_node)) {
- serdes_phy = of_phy_get(to_of_node(dpmac_node), NULL);
- if (IS_ERR(serdes_phy))
- return -EPROBE_DEFER;
- }
- mac->serdes_phy = serdes_phy;
-
/* The MAC does not have the capability to add RGMII delays so
* error out if the interface mode requests them and there is no PHY
* to act upon them
@@ -441,7 +413,6 @@ int dpaa2_mac_open(struct dpaa2_mac *mac)
{
struct fsl_mc_device *dpmac_dev = mac->mc_dev;
struct net_device *net_dev = mac->net_dev;
- unsigned long if_mode_addr;
int err;
err = dpmac_open(mac->mc_io, 0, dpmac_dev->obj_desc.id,
@@ -464,12 +435,6 @@ int dpaa2_mac_open(struct dpaa2_mac *mac)
mac->fw_node = dpaa2_mac_get_node(&mac->mc_dev->dev, mac->attr.id);
net_dev->dev.of_node = to_of_node(mac->fw_node);
- if_mode_addr = 0x8c07080 + 0x4000 * (dpmac_dev->obj_desc.id - 1);
- mac->if_mode_reg = ioremap(if_mode_addr, 4);
- if (!mac->if_mode_reg) {
- netdev_err(net_dev, "ioremap on if_mode failed\n");
- }
-
return 0;
err_close_dpmac:
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
index 60086fc9c985..bb37a78d08a4 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
@@ -27,9 +27,6 @@ struct dpaa2_mac {
struct lynx_pcs *pcs;
struct fwnode_handle *fw_node;
- struct phy *serdes_phy;
- void __iomem *if_mode_reg;
-
struct led_classdev *link_status_led;
};
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index b46c28672dc2..29b05925e1c5 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -39,11 +39,3 @@ config PHY_FSL_IMX_PCIE
help
Enable this to add support for the PCIE PHY as found on i.MX
family of SOCs.
-
-config PHY_FSL_SERDES_28G
- tristate "Freescale Layerscape SerDes PHY support"
- depends on OF
- select GENERIC_PHY
- help
- Enable this to add support for the SerDes 28G PHY as found on NXP's
- Layerscape platform such as LX2160A.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index 380809d3f34c..0675f155c47d 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -4,4 +4,3 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
obj-$(CONFIG_PHY_FSL_IMX_PCIE) += phy-fsl-imx8-pcie.o
-obj-$(CONFIG_PHY_FSL_SERDES_28G) += phy-fsl-serdes-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-serdes-28g.c b/drivers/phy/freescale/phy-fsl-serdes-28g.c
deleted file mode 100644
index 841edf6c0477..000000000000
--- a/drivers/phy/freescale/phy-fsl-serdes-28g.c
+++ /dev/null
@@ -1,521 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright (c) 2021 NXP. */
-
-#include <linux/module.h>
-#include <linux/phy.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
-
-#define SERDES28G_NUM_LANE 8
-#define SERDES28G_NUM_PLL 2
-
-/* General registers per SerDes block */
-#define SERDES28G_PCC8 0x10a0
-#define SERDES28G_PCC8_SGMII 0x1
-#define SERDES28G_PCC8_SGMII_DIS 0x0
-
-#define SERDES28G_PCCC 0x10b0
-#define SERDES28G_PCCC_10GBASER 0x9
-#define SERDES28G_PCCC_USXGMII 0x1
-#define SERDES28G_PCCC_SXGMII_DIS 0x0
-
-/* Per PLL registers */
-#define SERDES28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
-#define SERDES28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
-#define SERDES28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
-
-#define SERDES28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
-#define SERDES28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20,16)))
-#define SERDES28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
-#define SERDES28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
-#define SERDES28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
-#define SERDES28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
-#define SERDES28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
-
-#define SERDES28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
-#define SERDES28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28,24)))
-#define SERDES28G_PLLnCR1_FRATE_5G_10GVCO 0x0
-#define SERDES28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
-#define SERDES28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
-
-/* Per SerDes lane registers */
-/* Lane a General Control Register */
-#define SERDES28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
-#define SERDES28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7,3)
-#define SERDES28G_LNaGCR0_PROTO_SEL_SGMII 0x8
-#define SERDES28G_LNaGCR0_PROTO_SEL_XFI 0x50
-#define SERDES28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2,0)
-#define SERDES28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
-#define SERDES28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
-
-/* Lane a Tx Reset Control Register */
-#define SERDES28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
-#define SERDES28G_LNaTRSTCTL_HLT_REQ BIT(27)
-#define SERDES28G_LNaTRSTCTL_RST_DONE BIT(30)
-#define SERDES28G_LNaTRSTCTL_RST_REQ BIT(31)
-
-/* Lane a Tx General Control Register */
-#define SERDES28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
-#define SERDES28G_LNaTGCR0_USE_PLLF 0x0
-#define SERDES28G_LNaTGCR0_USE_PLLS BIT(28)
-#define SERDES28G_LNaTGCR0_USE_PLL_MSK BIT(28)
-#define SERDES28G_LNaTGCR0_N_RATE_FULL 0x0
-#define SERDES28G_LNaTGCR0_N_RATE_HALF 0x1000000
-#define SERDES28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
-#define SERDES28G_LNaTGCR0_N_RATE_MSK GENMASK(26,24)
-
-/* Lane a Rx Reset Control Register */
-#define SERDES28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
-#define SERDES28G_LNaRRSTCTL_HLT_REQ BIT(27)
-#define SERDES28G_LNaRRSTCTL_RST_DONE BIT(30)
-#define SERDES28G_LNaRRSTCTL_RST_REQ BIT(31)
-
-/* Lane a Rx General Control Register */
-#define SERDES28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
-#define SERDES28G_LNaRGCR0_USE_PLLF 0x0
-#define SERDES28G_LNaRGCR0_USE_PLLS BIT(28)
-#define SERDES28G_LNaRGCR0_USE_PLL_MSK BIT(28)
-#define SERDES28G_LNaRGCR0_N_RATE_MSK GENMASK(26,24)
-#define SERDES28G_LNaRGCR0_N_RATE_FULL 0x0
-#define SERDES28G_LNaRGCR0_N_RATE_HALF 0x1000000
-#define SERDES28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
-#define SERDES28G_LNaRGCR0_N_RATE_MSK GENMASK(26,24)
-
-#define SERDES28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
-#define SERDES28G_SGMIIaCR1_SGPCS_EN BIT(11)
-#define SERDES28G_SGMIIaCR1_SGPCS_DIS 0x0
-#define SERDES28G_SGMIIaCR1_SGPCS_MSK BIT(11)
-
-struct serdes28g_pll {
- struct serdes28g_priv *priv;
- u32 rstctl, cr0, cr1;
- int id;
- DECLARE_PHY_INTERFACE_MASK(supported);
-};
-
-struct serdes28g_priv {
- void __iomem *base;
- struct device *dev;
- struct serdes28g_pll pll[SERDES28G_NUM_PLL];
-};
-
-struct serdes28g_lane {
- struct serdes28g_priv *priv;
- bool powered_up;
- unsigned id;
-};
-
-static void serdes28g_rmw(struct serdes28g_priv *priv, unsigned long off,
- u32 val, u32 mask)
-{
- void __iomem *reg = priv->base + off;
- u32 orig, tmp;
-
- orig = ioread32(reg);
- tmp = orig & ~mask;
- tmp |= val;
- iowrite32(tmp, reg);
-}
-
-#define serdes28g_lane_rmw(lane, reg, val, mask) \
- serdes28g_rmw((lane)->priv, SERDES28G_##reg(lane->id), SERDES28G_##reg##_##val, SERDES28G_##reg##_##mask)
-
-#define serdes28g_lane_read(lane, reg) \
- ioread32((lane)->priv->base + SERDES28G_##reg((lane)->id))
-#define serdes28g_pll_read(pll, reg) \
- ioread32((pll)->priv->base + SERDES28G_##reg((pll)->id))
-
-static bool serdes28g_supports_interface(struct serdes28g_priv *priv, int intf)
-{
- int i;
-
- for (i = 0; i < SERDES28G_NUM_PLL; i++)
- if (test_bit(intf, priv->pll[i].supported))
- return true;
-
- return false;
-}
-
-static struct serdes28g_pll *serdes28g_pll_get(struct serdes28g_priv *priv,
- phy_interface_t intf)
-{
- struct serdes28g_pll *pll;
- int i;
-
- for (i = 0; i < SERDES28G_NUM_PLL; i++) {
- pll = &priv->pll[i];
- if (test_bit(intf, pll->supported))
- return pll;
- }
-
- return NULL;
-}
-
-static void serdes28g_lane_set_nrate(struct serdes28g_lane *lane,
- struct serdes28g_pll *pll,
- phy_interface_t intf)
-{
- switch (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
- case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
- switch (intf) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- serdes28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK);
- serdes28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK);
- break;
- default:
- break;
- }
- break;
- case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
- switch (intf) {
- case PHY_INTERFACE_MODE_10GBASER:
- case PHY_INTERFACE_MODE_USXGMII:
- serdes28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK);
- serdes28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK);
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-}
-
-static void serdes28g_lane_set_pll(struct serdes28g_lane *lane,
- struct serdes28g_pll *pll)
-{
- if (pll->id == 0) {
- serdes28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK);
- serdes28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK);
- } else {
- serdes28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK);
- serdes28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK);
- }
-}
-
-static int serdes28g_lane_set_sgmii(struct serdes28g_lane *lane)
-{
- struct serdes28g_priv *priv = lane->priv;
- struct serdes28g_pll *pll;
- u32 lane_mask, lane_offset;
-
- lane_offset = (4 * (SERDES28G_NUM_LANE - lane->id - 1));
- lane_mask = GENMASK(3,0) << lane_offset;
-
- /* Disable the SXGMII lane */
- serdes28g_rmw(priv, SERDES28G_PCCC,
- SERDES28G_PCCC_SXGMII_DIS << lane_offset, lane_mask);
-
- /* This lane runs in SGMII mode */
- serdes28g_rmw(priv, SERDES28G_PCC8,
- SERDES28G_PCC8_SGMII << lane_offset, lane_mask);
-
- /* Setup the protocol select and SerDes parallel interface width */
- serdes28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK);
- serdes28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK);
-
- /* Switch to the PLL that works with this interface type */
- pll = serdes28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
- serdes28g_lane_set_pll(lane, pll);
-
- /* Choose the portion of clock net to be used on this lane */
- serdes28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
-
- /* Enable the SGMII PCS */
- serdes28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
-
- return 0;
-}
-
-static int serdes28g_lane_set_10gbaser(struct serdes28g_lane *lane)
-{
- struct serdes28g_priv *priv = lane->priv;
- u32 lane_mask, lane_offset;
- struct serdes28g_pll *pll;
-
- lane_offset = (4 * (SERDES28G_NUM_LANE - lane->id - 1));
- lane_mask = GENMASK(3,0) << lane_offset;
-
- /* Stop the lane from running in SGMII/1000Base-x/1000Base-KX mode */
- serdes28g_rmw(priv, SERDES28G_PCC8,
- SERDES28G_PCC8_SGMII_DIS << lane_offset, lane_mask);
-
- /* Enable the SXGMII lane */
- serdes28g_rmw(priv, SERDES28G_PCCC,
- SERDES28G_PCCC_10GBASER << lane_offset, lane_mask);
-
- /* Setup the protocol select and SerDes parallel interface width */
- serdes28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK);
- serdes28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK);
-
- /* Switch to the PLL that works with this interface type */
- pll = serdes28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
- serdes28g_lane_set_pll(lane, pll);
-
- /* Choose the portion of clock net to be used on this lane */
- serdes28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
-
- /* Disable the SGMII PCS */
- serdes28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
-
- return 0;
-}
-
-static int serdes28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
-{
- struct serdes28g_lane *lane = phy_get_drvdata(phy);
- struct serdes28g_priv *priv = lane->priv;
- int err;
-
- if (mode != PHY_MODE_ETHERNET)
- return -EOPNOTSUPP;
-
- if (!serdes28g_supports_interface(priv, submode))
- return -EOPNOTSUPP;
-
- switch (submode) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- err = serdes28g_lane_set_sgmii(lane);
- break;
- case PHY_INTERFACE_MODE_10GBASER:
- err = serdes28g_lane_set_10gbaser(lane);
- break;
- default:
- return -EOPNOTSUPP;
- }
-
- return err;
-}
-
-static int serdes28g_power_off(struct phy *phy)
-{
- struct serdes28g_lane *lane = phy_get_drvdata(phy);
- u32 trstctl, rrstctl;
-
- if (!lane->powered_up)
- return 0;
-
- /* Issue a halt request */
- serdes28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ);
- serdes28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ);
-
- /* Wait until the halting process is complete */
- do {
- trstctl = serdes28g_lane_read(lane, LNaTRSTCTL);
- rrstctl = serdes28g_lane_read(lane, LNaRRSTCTL);
- } while ((trstctl & SERDES28G_LNaTRSTCTL_HLT_REQ) ||
- (rrstctl & SERDES28G_LNaRRSTCTL_HLT_REQ));
-
- lane->powered_up = false;
-
- return 0;
-}
-
-static int serdes28g_power_on(struct phy *phy)
-{
- struct serdes28g_lane *lane = phy_get_drvdata(phy);
- u32 trstctl, rrstctl;
-
- if (lane->powered_up)
- return 0;
-
- /* Issue a reset request on the lane */
- serdes28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ);
- serdes28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
-
- /* Wait until the reset sequence is completed */
- do {
- trstctl = serdes28g_lane_read(lane, LNaTRSTCTL);
- rrstctl = serdes28g_lane_read(lane, LNaRRSTCTL);
- } while (!(trstctl & SERDES28G_LNaTRSTCTL_RST_DONE) ||
- !(rrstctl & SERDES28G_LNaRRSTCTL_RST_DONE));
-
- lane->powered_up = true;
-
- return 0;
-}
-
-static const struct phy_ops serdes28g_ops = {
- .power_on = serdes28g_power_on,
- .power_off = serdes28g_power_off,
- .set_mode = serdes28g_set_mode,
- .owner = THIS_MODULE,
-};
-
-static void serdes26_pll_dump(struct serdes28g_pll *pll)
-{
- struct serdes28g_priv *priv = pll->priv;
- bool dis, lock;
- u32 refclk, frate;
- int intf;
-
- dis = SERDES28G_PLLnRSTCTL_DIS(pll->rstctl) != 0 ? true : false;
- lock = SERDES28G_PLLnRSTCTL_LOCK(pll->rstctl) != 0 ? true : false;
- refclk = SERDES28G_PLLnCR0_REFCLK_SEL(pll->cr0);
- frate = (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1));
-
- dev_err(priv->dev, "PLL%c: %sabled, %slocked\n",
- pll->id == 0 ? 'F' : 'S',
- dis ? "dis" : "en",
- lock ? "" : "un");
-
- switch (refclk) {
- case SERDES28G_PLLnCR0_REFCLK_SEL_100MHZ:
- dev_err(priv->dev, "\tReference clock: 100MHz\n");
- break;
- case SERDES28G_PLLnCR0_REFCLK_SEL_125MHZ:
- dev_err(priv->dev, "\tReference clock: 125MHz\n");
- break;
- case SERDES28G_PLLnCR0_REFCLK_SEL_156MHZ:
- dev_err(priv->dev, "\tReference clock: 156.25MHz\n");
- break;
- case SERDES28G_PLLnCR0_REFCLK_SEL_150MHZ:
- dev_err(priv->dev, "\tReference clock: 150MHz\n");
- break;
- case SERDES28G_PLLnCR0_REFCLK_SEL_161MHZ:
- dev_err(priv->dev, "\tReference clock: 161.1328125MHz\n");
- break;
- default:
- break;
- }
-
- switch (frate) {
- case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
- case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
- dev_err(priv->dev, "\tclock net: 5GHz\n");
- break;
- case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
- dev_err(priv->dev, "\tclock net: 10.3125GHz\n");
- break;
- default:
- /* 6GHz, 12.890625GHz, 8GHz */
- break;
- }
-
- dev_err(priv->dev, "\tSupported interfaces:\n");
- for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) {
- if (test_bit(intf, pll->supported))
- dev_err(priv->dev, "\t\t%s\n", phy_modes(intf));
- }
-}
-
-static void serdes28g_pll_read_configuration(struct serdes28g_priv *priv)
-{
- struct serdes28g_pll *pll;
- int i;
-
- for (i = 0; i < SERDES28G_NUM_PLL; i++) {
- pll = &priv->pll[i];
- pll->priv = priv;
- pll->id = i;
-
- pll->rstctl = serdes28g_pll_read(pll, PLLnRSTCTL);
- pll->cr0 = serdes28g_pll_read(pll, PLLnCR0);
- pll->cr1 = serdes28g_pll_read(pll, PLLnCR1);
-
- switch (SERDES28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case SERDES28G_PLLnCR1_FRATE_5G_10GVCO:
- case SERDES28G_PLLnCR1_FRATE_5G_25GVCO:
- /* 5GHz clock net */
- __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
- __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
- __set_bit(PHY_INTERFACE_MODE_QSGMII, pll->supported);
- break;
- case SERDES28G_PLLnCR1_FRATE_10G_20GVCO:
- /* 10.3125GHz clock net */
- __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
- __set_bit(PHY_INTERFACE_MODE_USXGMII, pll->supported);
- break;
- default:
- /* 6GHz, 12.890625GHz, 8GHz */
- break;
- }
-
- serdes26_pll_dump(pll);
- }
-}
-
-static int serdes28g_probe(struct platform_device *pdev)
-{
- struct phy_provider *provider;
- struct serdes28g_priv *priv;
- struct device_node *child;
- int err;
-
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
- priv->dev = &pdev->dev;
-
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
-
- serdes28g_pll_read_configuration(priv);
-
- for_each_available_child_of_node(pdev->dev.of_node, child) {
- struct serdes28g_lane *lane;
- struct phy *phy;
- u32 val;
-
- err = of_property_read_u32(child, "reg", &val);
- if (err < 0) {
- dev_err(&pdev->dev, "missing 'reg' property (%d)\n", err);
- continue;
- }
-
- if (val >= SERDES28G_NUM_LANE) {
- dev_err(&pdev->dev, "invalid 'reg' property\n");
- continue;
- }
-
- lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
- if (!lane) {
- of_node_put(child);
- return -ENOMEM;
- }
-
- phy = devm_phy_create(&pdev->dev, child, &serdes28g_ops);
- if (IS_ERR(phy)) {
- of_node_put(child);
- return PTR_ERR(phy);
- }
-
- lane->priv = priv;
- lane->id = val;
- lane->powered_up = true;
- phy_set_drvdata(phy, lane);
-
- phy_power_on(phy);
-
- dev_err(priv->dev, "created PHY for lane #%d\n", lane->id);
- }
-
- dev_set_drvdata(&pdev->dev, priv);
- provider = devm_of_phy_provider_register(&pdev->dev,
- of_phy_simple_xlate);
-
- return PTR_ERR_OR_ZERO(provider);
-}
-
-static const struct of_device_id serdes28g_of_match_table[] = {
- { .compatible = "fsl,serdes-28g" },
- { },
-};
-MODULE_DEVICE_TABLE(of, serdes28g_of_match_table);
-
-static struct platform_driver serdes28g_driver = {
- .probe = serdes28g_probe,
- .driver = {
- .name = "serdes-28g",
- .of_match_table = serdes28g_of_match_table,
- },
-};
-module_platform_driver(serdes28g_driver);
-
-MODULE_AUTHOR("Ioana Ciornei <ioana.ciornei@nxp.com>");
-MODULE_DESCRIPTION("SerDes 28G PHY driver for Layerscape SoCs");
--
2.38.1
patches/linux-LSDK-21.08/0034-arm64-dts-lx2160a-remove-serdes2-description.patch 0 → 100644
View file @ db443a11
From 7ff87b026321d30874de2866fb83cba65f7c0282 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 10:24:38 +0200
Subject: [PATCH 34/45] arm64: dts: lx2160a: remove serdes2 description
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 41 -------------------
1 file changed, 41 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fd14b4c5b9fb..23b48824b139 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -613,47 +613,6 @@ soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
- serdes_2: serdes_phy@1eb0000 {
- compatible = "fsl,serdes-28g";
- reg = <0x00 0x1eb0000 0x0 0x1e30>;
- #address-cells = <1>;
- #size-cells = <0>;
- #phy-cells = <1>;
-
- serdes2_lane_a: phy@0 {
- reg = <0>;
- #phy-cells = <0>;
- };
- serdes2_lane_b: phy@1 {
- reg = <1>;
- #phy-cells = <0>;
- };
- serdes2_lane_c: phy@2 {
- reg = <2>;
- #phy-cells = <0>;
- };
- serdes2_lane_d: phy@3 {
- reg = <3>;
- #phy-cells = <0>;
- };
- serdes2_lane_e: phy@4 {
- reg = <4>;
- #phy-cells = <0>;
- };
- serdes2_lane_f: phy@5 {
- reg = <5>;
- #phy-cells = <0>;
- };
- serdes2_lane_g: phy@6 {
- reg = <6>;
- #phy-cells = <0>;
- };
- serdes2_lane_h: phy@7 {
- reg = <7>;
- #phy-cells = <0>;
- };
- };
-
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.38.1
patches/linux-LSDK-21.08/0035-phy-add-support-for-the-Layerscape-SerDes-28G.patch 0 → 100644
View file @ db443a11
From d93638b558b6b1b3c16aa3ffaf170784a26297c3 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:21 +0200
Subject: [PATCH 35/45] phy: add support for the Layerscape SerDes 28G
This patch adds a new generic PHY driver to support the Lynx 28G SerDes
block found on some of the Layerscape SoCs such as LX2160A.
At the moment, only the following Ethernet protocols are supported:
SGMII/1000Base-X and 10GBaseR.
SerDes lanes which are not running an Ethernet protocol or a currently
supported Ethenet protocol will be left as it was configured through the
RCW (Reset Configuration Word) at boot time.
At probe time, the platform driver will read the current
configuration of both PLLs found on a SerDes block and will determine
what protocols are supported using that PLL.
For example, if a PLL is configured to generate a clock net (frate) of
5GHz the only protocols sustained by that PLL are SGMII/1000Base-X
(using a quarter of the full clock rate) and QSGMII using the full clock
net frequency on the lane.
On the .set_mode() callback, the PHY driver will first check if the
requested operating mode (protocol) is even supported by the current PLL
configuration and will error out if not.
Then, the lane is reconfigured to run on the requested protocol.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
MAINTAINERS | 6 +
drivers/phy/freescale/Kconfig | 10 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-lynx-28g.c | 624 +++++++++++++++++++++++
4 files changed, 641 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-lynx-28g.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 047a0469b056..009d36524bef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10381,6 +10381,12 @@ S: Maintained
W: http://linux-test-project.github.io/
T: git git://github.com/linux-test-project/ltp.git
+LYNX 28G SERDES PHY DRIVER
+M: Ioana Ciornei <ioana.ciornei@nxp.com>
+L: netdev@vger.kernel.org
+S: Supported
+F: drivers/phy/freescale/phy-fsl-lynx-28g.c
+
LYNX PCS MODULE
M: Ioana Ciornei <ioana.ciornei@nxp.com>
L: netdev@vger.kernel.org
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 29b05925e1c5..bd998f8f37de 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -39,3 +39,13 @@ config PHY_FSL_IMX_PCIE
help
Enable this to add support for the PCIE PHY as found on i.MX
family of SOCs.
+
+config PHY_FSL_LYNX_28G
+ tristate "Freescale Layerscape Lynx 28G SerDes PHY support"
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to add support for the Lynx SerDes 28G PHY as
+ found on NXP's Layerscape platforms such as LX2160A.
+ Used to change the protocol running on SerDes lanes at runtime.
+ Only useful for a restricted set of Ethernet protocols.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index 0675f155c47d..2c585b5c3df1 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
obj-$(CONFIG_PHY_FSL_IMX_PCIE) += phy-fsl-imx8-pcie.o
+obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
new file mode 100644
index 000000000000..a2b060e9e284
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2021-2022 NXP. */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <linux/workqueue.h>
+
+#define LYNX_28G_NUM_LANE 8
+#define LYNX_28G_NUM_PLL 2
+
+/* General registers per SerDes block */
+#define LYNX_28G_PCC8 0x10a0
+#define LYNX_28G_PCC8_SGMII 0x1
+#define LYNX_28G_PCC8_SGMII_DIS 0x0
+
+#define LYNX_28G_PCCC 0x10b0
+#define LYNX_28G_PCCC_10GBASER 0x9
+#define LYNX_28G_PCCC_USXGMII 0x1
+#define LYNX_28G_PCCC_SXGMII_DIS 0x0
+
+#define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+
+/* Per PLL registers */
+#define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
+#define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
+#define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
+
+#define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
+#define LYNX_28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
+#define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
+#define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
+#define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
+#define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
+#define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
+
+#define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
+#define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
+#define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0
+#define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
+#define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
+
+/* Per SerDes lane registers */
+/* Lane a General Control Register */
+#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
+#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
+#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
+#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
+#define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
+#define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
+#define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
+
+/* Lane a Tx Reset Control Register */
+#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
+#define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27)
+#define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30)
+#define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31)
+
+/* Lane a Tx General Control Register */
+#define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
+#define LYNX_28G_LNaTGCR0_USE_PLLF 0x0
+#define LYNX_28G_LNaTGCR0_USE_PLLS BIT(28)
+#define LYNX_28G_LNaTGCR0_USE_PLL_MSK BIT(28)
+#define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0
+#define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000
+#define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
+#define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
+
+#define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
+
+/* Lane a Rx Reset Control Register */
+#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
+#define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27)
+#define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30)
+#define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31)
+#define LYNX_28G_LNaRRSTCTL_CDR_LOCK BIT(12)
+
+/* Lane a Rx General Control Register */
+#define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
+#define LYNX_28G_LNaRGCR0_USE_PLLF 0x0
+#define LYNX_28G_LNaRGCR0_USE_PLLS BIT(28)
+#define LYNX_28G_LNaRGCR0_USE_PLL_MSK BIT(28)
+#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0
+#define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000
+#define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
+#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+
+#define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
+
+#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
+#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
+#define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
+
+#define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
+
+#define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
+#define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
+#define LYNX_28G_LNaPSS_TYPE_SGMII 0x4
+#define LYNX_28G_LNaPSS_TYPE_XFI 0x28
+
+#define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
+#define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11)
+#define LYNX_28G_SGMIIaCR1_SGPCS_DIS 0x0
+#define LYNX_28G_SGMIIaCR1_SGPCS_MSK BIT(11)
+
+struct lynx_28g_priv;
+
+struct lynx_28g_pll {
+ struct lynx_28g_priv *priv;
+ u32 rstctl, cr0, cr1;
+ int id;
+ DECLARE_PHY_INTERFACE_MASK(supported);
+};
+
+struct lynx_28g_lane {
+ struct lynx_28g_priv *priv;
+ struct phy *phy;
+ bool powered_up;
+ bool init;
+ unsigned int id;
+ phy_interface_t interface;
+};
+
+struct lynx_28g_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct lynx_28g_pll pll[LYNX_28G_NUM_PLL];
+ struct lynx_28g_lane lane[LYNX_28G_NUM_LANE];
+
+ struct delayed_work cdr_check;
+};
+
+static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
+ u32 val, u32 mask)
+{
+ void __iomem *reg = priv->base + off;
+ u32 orig, tmp;
+
+ orig = ioread32(reg);
+ tmp = orig & ~mask;
+ tmp |= val;
+ iowrite32(tmp, reg);
+}
+
+#define lynx_28g_lane_rmw(lane, reg, val, mask) \
+ lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
+ LYNX_28G_##reg##_##val, LYNX_28G_##reg##_##mask)
+#define lynx_28g_lane_read(lane, reg) \
+ ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
+#define lynx_28g_pll_read(pll, reg) \
+ ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
+
+static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
+{
+ int i;
+
+ for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
+ if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl))
+ continue;
+
+ if (test_bit(intf, priv->pll[i].supported))
+ return true;
+ }
+
+ return false;
+}
+
+static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
+ phy_interface_t intf)
+{
+ struct lynx_28g_pll *pll;
+ int i;
+
+ for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
+ pll = &priv->pll[i];
+
+ if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ continue;
+
+ if (test_bit(intf, pll->supported))
+ return pll;
+ }
+
+ return NULL;
+}
+
+static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
+ struct lynx_28g_pll *pll,
+ phy_interface_t intf)
+{
+ switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
+ case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (intf) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK);
+ break;
+ default:
+ break;
+ }
+ break;
+ case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ switch (intf) {
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK);
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
+ struct lynx_28g_pll *pll)
+{
+ if (pll->id == 0) {
+ lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK);
+ } else {
+ lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK);
+ }
+}
+
+static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
+{
+ u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
+ struct lynx_28g_priv *priv = lane->priv;
+
+ /* Cleanup the protocol configuration registers of the current protocol */
+ switch (lane->interface) {
+ case PHY_INTERFACE_MODE_10GBASER:
+ lynx_28g_rmw(priv, LYNX_28G_PCCC,
+ LYNX_28G_PCCC_SXGMII_DIS << lane_offset,
+ GENMASK(3, 0) << lane_offset);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lynx_28g_rmw(priv, LYNX_28G_PCC8,
+ LYNX_28G_PCC8_SGMII_DIS << lane_offset,
+ GENMASK(3, 0) << lane_offset);
+ break;
+ default:
+ break;
+ }
+}
+
+static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
+{
+ u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_28g_pll *pll;
+
+ lynx_28g_cleanup_lane(lane);
+
+ /* Setup the lane to run in SGMII */
+ lynx_28g_rmw(priv, LYNX_28G_PCC8,
+ LYNX_28G_PCC8_SGMII << lane_offset,
+ GENMASK(3, 0) << lane_offset);
+
+ /* Setup the protocol select and SerDes parallel interface width */
+ lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK);
+ lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK);
+
+ /* Switch to the PLL that works with this interface type */
+ pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
+ lynx_28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+ lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
+
+ /* Enable the SGMII PCS */
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
+
+ /* Configure the appropriate equalization parameters for the protocol */
+ iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
+ iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
+ iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
+ iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
+ iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+}
+
+static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
+{
+ u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_28g_pll *pll;
+
+ lynx_28g_cleanup_lane(lane);
+
+ /* Enable the SXGMII lane */
+ lynx_28g_rmw(priv, LYNX_28G_PCCC,
+ LYNX_28G_PCCC_10GBASER << lane_offset,
+ GENMASK(3, 0) << lane_offset);
+
+ /* Setup the protocol select and SerDes parallel interface width */
+ lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK);
+ lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK);
+
+ /* Switch to the PLL that works with this interface type */
+ pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
+ lynx_28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+ lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
+
+ /* Disable the SGMII PCS */
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
+
+ /* Configure the appropriate equalization parameters for the protocol */
+ iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
+ iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
+ iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
+ iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
+ iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+}
+
+static int lynx_28g_power_off(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ u32 trstctl, rrstctl;
+
+ if (!lane->powered_up)
+ return 0;
+
+ /* Issue a halt request */
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ);
+
+ /* Wait until the halting process is complete */
+ do {
+ trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+ } while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) ||
+ (rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ));
+
+ lane->powered_up = false;
+
+ return 0;
+}
+
+static int lynx_28g_power_on(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ u32 trstctl, rrstctl;
+
+ if (lane->powered_up)
+ return 0;
+
+ /* Issue a reset request on the lane */
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
+
+ /* Wait until the reset sequence is completed */
+ do {
+ trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+ } while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) ||
+ !(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+
+ lane->powered_up = true;
+
+ return 0;
+}
+
+static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ struct lynx_28g_priv *priv = lane->priv;
+ int powered_up = lane->powered_up;
+ int err = 0;
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EOPNOTSUPP;
+
+ if (lane->interface == PHY_INTERFACE_MODE_NA)
+ return -EOPNOTSUPP;
+
+ if (!lynx_28g_supports_interface(priv, submode))
+ return -EOPNOTSUPP;
+
+ /* If the lane is powered up, put the lane into the halt state while
+ * the reconfiguration is being done.
+ */
+ if (powered_up)
+ lynx_28g_power_off(phy);
+
+ switch (submode) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lynx_28g_lane_set_sgmii(lane);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ lynx_28g_lane_set_10gbaser(lane);
+ break;
+ default:
+ err = -EOPNOTSUPP;
+ goto out;
+ }
+
+ lane->interface = submode;
+
+out:
+ /* Power up the lane if necessary */
+ if (powered_up)
+ lynx_28g_power_on(phy);
+
+ return err;
+}
+
+static int lynx_28g_validate(struct phy *phy, enum phy_mode mode, int submode,
+ union phy_configure_opts *opts __always_unused)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ struct lynx_28g_priv *priv = lane->priv;
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EOPNOTSUPP;
+
+ if (!lynx_28g_supports_interface(priv, submode))
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static int lynx_28g_init(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+
+ /* Mark the fact that the lane was init */
+ lane->init = true;
+
+ /* SerDes lanes are powered on at boot time. Any lane that is managed
+ * by this driver will get powered down at init time aka at dpaa2-eth
+ * probe time.
+ */
+ lane->powered_up = true;
+ lynx_28g_power_off(phy);
+
+ return 0;
+}
+
+static const struct phy_ops lynx_28g_ops = {
+ .init = lynx_28g_init,
+ .power_on = lynx_28g_power_on,
+ .power_off = lynx_28g_power_off,
+ .set_mode = lynx_28g_set_mode,
+ .validate = lynx_28g_validate,
+ .owner = THIS_MODULE,
+};
+
+static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
+{
+ struct lynx_28g_pll *pll;
+ int i;
+
+ for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
+ pll = &priv->pll[i];
+ pll->priv = priv;
+ pll->id = i;
+
+ pll->rstctl = lynx_28g_pll_read(pll, PLLnRSTCTL);
+ pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0);
+ pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1);
+
+ if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ continue;
+
+ switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
+ case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ /* 5GHz clock net */
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
+ break;
+ case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ /* 10.3125GHz clock net */
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
+ break;
+ default:
+ /* 6GHz, 12.890625GHz, 8GHz */
+ break;
+ }
+ }
+}
+
+#define work_to_lynx(w) container_of((w), struct lynx_28g_priv, cdr_check.work)
+
+static void lynx_28g_cdr_lock_check(struct work_struct *work)
+{
+ struct lynx_28g_priv *priv = work_to_lynx(work);
+ struct lynx_28g_lane *lane;
+ u32 rrstctl;
+ int i;
+
+ for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
+ lane = &priv->lane[i];
+
+ if (!lane->init)
+ continue;
+
+ if (!lane->powered_up)
+ continue;
+
+ rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+ if (!(rrstctl & LYNX_28G_LNaRRSTCTL_CDR_LOCK)) {
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
+ do {
+ rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+ } while (!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+ }
+ }
+ queue_delayed_work(system_power_efficient_wq, &priv->cdr_check,
+ msecs_to_jiffies(1000));
+}
+
+static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
+{
+ u32 pss, protocol;
+
+ pss = lynx_28g_lane_read(lane, LNaPSS);
+ protocol = LYNX_28G_LNaPSS_TYPE(pss);
+ switch (protocol) {
+ case LYNX_28G_LNaPSS_TYPE_SGMII:
+ lane->interface = PHY_INTERFACE_MODE_SGMII;
+ break;
+ case LYNX_28G_LNaPSS_TYPE_XFI:
+ lane->interface = PHY_INTERFACE_MODE_10GBASER;
+ break;
+ default:
+ lane->interface = PHY_INTERFACE_MODE_NA;
+ }
+}
+
+static struct phy *lynx_28g_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct lynx_28g_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+
+ if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
+ return ERR_PTR(-EINVAL);
+
+ return priv->lane[idx].phy;
+}
+
+static int lynx_28g_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct lynx_28g_priv *priv;
+ int i;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ lynx_28g_pll_read_configuration(priv);
+
+ for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
+ struct lynx_28g_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->id = i;
+ phy_set_drvdata(phy, lane);
+ lynx_28g_lane_read_configuration(lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
+
+ queue_delayed_work(system_power_efficient_wq, &priv->cdr_check,
+ msecs_to_jiffies(1000));
+
+ dev_set_drvdata(&pdev->dev, priv);
+ provider = devm_of_phy_provider_register(&pdev->dev, lynx_28g_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id lynx_28g_of_match_table[] = {
+ { .compatible = "fsl,lynx-28g" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lynx_28g_of_match_table);
+
+static struct platform_driver lynx_28g_driver = {
+ .probe = lynx_28g_probe,
+ .driver = {
+ .name = "lynx-28g",
+ .of_match_table = lynx_28g_of_match_table,
+ },
+};
+module_platform_driver(lynx_28g_driver);
+
+MODULE_AUTHOR("Ioana Ciornei <ioana.ciornei@nxp.com>");
+MODULE_DESCRIPTION("Lynx 28G SerDes PHY driver for Layerscape SoCs");
+MODULE_LICENSE("GPL v2");
--
2.38.1
patches/linux-LSDK-21.08/0036-dt-bindings-phy-add-bindings-for-Lynx-28G-PHY.patch 0 → 100644
View file @ db443a11
From dbc6002ca885d1b7bf52c675cfde94256d17f2d9 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:22 +0200
Subject: [PATCH 36/45] dt-bindings: phy: add bindings for Lynx 28G PHY
Add device tree binding for the Lynx 28G SerDes PHY driver used on
Layerscape based SoCs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
.../devicetree/bindings/phy/fsl,lynx-28g.yaml | 40 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
new file mode 100644
index 000000000000..4d91e2f4f247
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,lynx-28g.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Lynx 28G SerDes PHY binding
+
+maintainers:
+ - Ioana Ciornei <ioana.ciornei@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,lynx-28g
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ serdes_1: phy@1ea0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 009d36524bef..4bbe6ba6cbfe 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10385,6 +10385,7 @@ LYNX 28G SERDES PHY DRIVER
M: Ioana Ciornei <ioana.ciornei@nxp.com>
L: netdev@vger.kernel.org
S: Supported
+F: Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
F: drivers/phy/freescale/phy-fsl-lynx-28g.c
LYNX PCS MODULE
--
2.38.1
patches/linux-LSDK-21.08/0037-dpaa2-mac-add-the-MC-API-for-retrieving-the-version.patch 0 → 100644
View file @ db443a11
From 7c4fb2f10a17f70c293082176f8ffb220722a5de Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:23 +0200
Subject: [PATCH 37/45] dpaa2-mac: add the MC API for retrieving the version
The dpmac_get_api_version command will be used in the next patches to
determine if the current firmware is capable or not to change the
Ethernet protocol running on the MAC.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
.../net/ethernet/freescale/dpaa2/dpmac-cmd.h | 7 +++++
drivers/net/ethernet/freescale/dpaa2/dpmac.c | 31 +++++++++++++++++++
drivers/net/ethernet/freescale/dpaa2/dpmac.h | 2 ++
3 files changed, 40 insertions(+)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h b/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
index 326b8b231f6e..b5c119cb5cb1 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
@@ -19,6 +19,8 @@
#define DPMAC_CMDID_CLOSE DPMAC_CMD(0x800)
#define DPMAC_CMDID_OPEN DPMAC_CMD(0x80c)
+#define DPMAC_CMDID_GET_API_VERSION DPMAC_CMD(0xa0c)
+
#define DPMAC_CMDID_GET_ATTR DPMAC_CMD(0x004)
#define DPMAC_CMDID_SET_IRQ_ENABLE DPMAC_CMD(0x012)
@@ -128,4 +130,9 @@ struct dpmac_rsp_get_link_cfg {
u64 advertising;
};
+struct dpmac_rsp_get_api_version {
+ __le16 major;
+ __le16 minor;
+};
+
#endif /* _FSL_DPMAC_CMD_H */
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac.c b/drivers/net/ethernet/freescale/dpaa2/dpmac.c
index 7d6649ae81ed..2a405f13b9d8 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac.c
@@ -451,3 +451,34 @@ int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
return 0;
}
+
+/**
+ * dpmac_get_api_version() - Get Data Path MAC version
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: Major version of data path mac API
+ * @minor_ver: Minor version of data path mac API
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ u16 *major_ver, u16 *minor_ver)
+{
+ struct dpmac_rsp_get_api_version *rsp_params;
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
+ cmd_flags,
+ 0);
+
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ rsp_params = (struct dpmac_rsp_get_api_version *)cmd.params;
+ *major_ver = le16_to_cpu(rsp_params->major);
+ *minor_ver = le16_to_cpu(rsp_params->minor);
+
+ return 0;
+}
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac.h b/drivers/net/ethernet/freescale/dpaa2/dpmac.h
index 6022d9108f1d..2042bdcf4f47 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac.h
@@ -298,4 +298,6 @@ int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
u8 irq_index,
u32 status);
+int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ u16 *major_ver, u16 *minor_ver);
#endif /* __FSL_DPMAC_H */
--
2.38.1
patches/linux-LSDK-21.08/0038-dpaa2-mac-add-the-MC-API-for-reconfiguring-the-proto.patch 0 → 100644
View file @ db443a11
From b030f5defb06f13583ebc85cf3035f2c090691b8 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:24 +0200
Subject: [PATCH 38/45] dpaa2-mac: add the MC API for reconfiguring the
protocol
The MC firmware gained recently a new command which can reconfigure the
running protocol on the underlying MAC. Add this new command which will
be used in the next patches in order to do a major reconfig on the
interface.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
.../net/ethernet/freescale/dpaa2/dpmac-cmd.h | 6 +++++
drivers/net/ethernet/freescale/dpaa2/dpmac.c | 23 +++++++++++++++++++
drivers/net/ethernet/freescale/dpaa2/dpmac.h | 3 +++
3 files changed, 32 insertions(+)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h b/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
index b5c119cb5cb1..587a8efc55c6 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h
@@ -34,6 +34,9 @@
#define DPMAC_CMDID_SET_LINK_STATE DPMAC_CMD_V2(0x0c3)
#define DPMAC_CMDID_GET_COUNTER DPMAC_CMD(0x0c4)
+
+#define DPMAC_CMDID_SET_PROTOCOL DPMAC_CMD(0x0c7)
+
/* Macros for accessing command fields smaller than 1byte */
#define DPMAC_MASK(field) \
GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
@@ -135,4 +138,7 @@ struct dpmac_rsp_get_api_version {
__le16 minor;
};
+struct dpmac_cmd_set_protocol {
+ u8 eth_if;
+};
#endif /* _FSL_DPMAC_CMD_H */
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac.c b/drivers/net/ethernet/freescale/dpaa2/dpmac.c
index 2a405f13b9d8..bd670fe87666 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac.c
@@ -482,3 +482,26 @@ int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
return 0;
}
+
+/**
+ * dpmac_set_protocol() - Reconfigure the DPMAC protocol
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @protocol: New protocol for the DPMAC to be reconfigured in.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_set_protocol(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+ enum dpmac_eth_if protocol)
+{
+ struct dpmac_cmd_set_protocol *cmd_params;
+ struct fsl_mc_command cmd = { 0 };
+
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_PROTOCOL,
+ cmd_flags, token);
+ cmd_params = (struct dpmac_cmd_set_protocol *)cmd.params;
+ cmd_params->eth_if = protocol;
+
+ return mc_send_command(mc_io, &cmd);
+}
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpmac.h b/drivers/net/ethernet/freescale/dpaa2/dpmac.h
index 2042bdcf4f47..86c2003db9ae 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpmac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpmac.h
@@ -300,4 +300,7 @@ int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 *major_ver, u16 *minor_ver);
+
+int dpmac_set_protocol(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
+ enum dpmac_eth_if protocol);
#endif /* __FSL_DPMAC_H */
--
2.38.1
patches/linux-LSDK-21.08/0039-dpaa2-mac-retrieve-API-version-and-detect-features.patch 0 → 100644
View file @ db443a11
From 045121b44b2f206194c8135e70bb8dad5267e074 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:25 +0200
Subject: [PATCH 39/45] dpaa2-mac: retrieve API version and detect features
Retrieve the API version running on the firmware and based on it detect
which features are available for usage.
The first one to be listed is the capability to change the MAC protocol
at runtime.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 30 +++++++++++++++++++
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index b4d8dcb5e74b..4d2a0160cc48 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -13,6 +13,28 @@
#define phylink_to_dpaa2_mac(config) \
container_of((config), struct dpaa2_mac, phylink_config)
+#define DPMAC_PROTOCOL_CHANGE_VER_MAJOR 4
+#define DPMAC_PROTOCOL_CHANGE_VER_MINOR 8
+
+#define DPAA2_MAC_FEATURE_PROTOCOL_CHANGE BIT(0)
+
+static int dpaa2_mac_cmp_ver(struct dpaa2_mac *mac,
+ u16 ver_major, u16 ver_minor)
+{
+ if (mac->ver_major == ver_major)
+ return mac->ver_minor - ver_minor;
+ return mac->ver_major - ver_major;
+}
+
+static void dpaa2_mac_detect_features(struct dpaa2_mac *mac)
+{
+ mac->features = 0;
+
+ if (dpaa2_mac_cmp_ver(mac, DPMAC_PROTOCOL_CHANGE_VER_MAJOR,
+ DPMAC_PROTOCOL_CHANGE_VER_MINOR) >= 0)
+ mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE;
+}
+
static int phy_mode(enum dpmac_eth_if eth_if, phy_interface_t *if_mode)
{
*if_mode = PHY_INTERFACE_MODE_NA;
@@ -429,6 +451,14 @@ int dpaa2_mac_open(struct dpaa2_mac *mac)
goto err_close_dpmac;
}
+ err = dpmac_get_api_version(mac->mc_io, 0, &mac->ver_major, &mac->ver_minor);
+ if (err) {
+ netdev_err(net_dev, "dpmac_get_api_version() = %d\n", err);
+ goto err_close_dpmac;
+ }
+
+ dpaa2_mac_detect_features(mac);
+
/* Find the device node representing the MAC device and link the device
* behind the associated netdev to it.
*/
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
index bb37a78d08a4..1d107b99053e 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
@@ -18,6 +18,8 @@ struct dpaa2_mac {
struct net_device *net_dev;
struct fsl_mc_io *mc_io;
struct dpmac_attr attr;
+ u16 ver_major, ver_minor;
+ unsigned long features;
struct phylink_config phylink_config;
struct phylink *phylink;
--
2.38.1
patches/linux-LSDK-21.08/0040-dpaa2-mac-configure-the-SerDes-phy-on-a-protocol-cha.patch 0 → 100644
View file @ db443a11
From 78d5e39c9155e89c41396160145fc3c9c8bd145f Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:27 +0200
Subject: [PATCH 40/45] dpaa2-mac: configure the SerDes phy on a protocol
change
This patch integrates the dpaa2-eth driver with the generic PHY
infrastructure in order to search, find and reconfigure the SerDes lanes
in case of a protocol change.
On the .mac_config() callback, the phy_set_mode_ext() API is called so
that the Lynx 28G SerDes PHY driver can change the lane's configuration.
In the same phylink callback the MC firmware is called so that it
reconfigures the MAC side to run using the new protocol.
The consumer drivers - dpaa2-eth and dpaa2-switch - are updated to call
the dpaa2_mac_start/stop functions newly added which will
power_on/power_off the associated SerDes lane.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
.../net/ethernet/freescale/dpaa2/dpaa2-eth.c | 5 +-
.../net/ethernet/freescale/dpaa2/dpaa2-mac.c | 67 +++++++++++++++++++
.../net/ethernet/freescale/dpaa2/dpaa2-mac.h | 5 ++
3 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
index ee5a22747455..430ab61f71dc 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
@@ -1830,8 +1830,10 @@ static int dpaa2_eth_open(struct net_device *net_dev)
goto enable_err;
}
- if (dpaa2_eth_is_type_phy(priv))
+ if (dpaa2_eth_is_type_phy(priv)) {
+ dpaa2_mac_start(priv->mac);
phylink_start(priv->mac->phylink);
+ }
return 0;
@@ -1906,6 +1908,7 @@ static int dpaa2_eth_stop(struct net_device *net_dev)
if (dpaa2_eth_is_type_phy(priv)) {
phylink_stop(priv->mac->phylink);
+ dpaa2_mac_stop(priv->mac);
} else {
netif_tx_stop_all_queues(net_dev);
netif_carrier_off(net_dev);
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index 4d2a0160cc48..815cd0018980 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -4,6 +4,8 @@
#include <linux/fsl/mc.h>
#include <linux/msi.h>
#include <linux/acpi.h>
+#include <linux/pcs-lynx.h>
+#include <linux/phy/phy.h>
#include <linux/property.h>
#include <linux/leds.h>
@@ -72,6 +74,29 @@ static bool dpaa2_mac_is_type_phy(struct dpaa2_mac *mac)
return false;
}
+static enum dpmac_eth_if dpmac_eth_if_mode(phy_interface_t if_mode)
+{
+ switch (if_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ return DPMAC_ETH_IF_RGMII;
+ case PHY_INTERFACE_MODE_USXGMII:
+ return DPMAC_ETH_IF_USXGMII;
+ case PHY_INTERFACE_MODE_QSGMII:
+ return DPMAC_ETH_IF_QSGMII;
+ case PHY_INTERFACE_MODE_SGMII:
+ return DPMAC_ETH_IF_SGMII;
+ case PHY_INTERFACE_MODE_10GBASER:
+ return DPMAC_ETH_IF_XFI;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ return DPMAC_ETH_IF_1000BASEX;
+ default:
+ return DPMAC_ETH_IF_MII;
+ }
+}
+
static struct fwnode_handle *dpaa2_mac_get_node(struct device *dev,
u16 dpmac_id)
{
@@ -233,6 +258,19 @@ static void dpaa2_mac_config(struct phylink_config *config, unsigned int mode,
if (err)
netdev_err(mac->net_dev, "%s: dpmac_set_link_state() = %d\n",
__func__, err);
+
+ if (!mac->serdes_phy)
+ return;
+
+ /* This happens only if we support changing of protocol at runtime */
+ err = dpmac_set_protocol(mac->mc_io, 0, mac->mc_dev->mc_handle,
+ dpmac_eth_if_mode(state->interface));
+ if (err)
+ netdev_err(mac->net_dev, "dpmac_set_protocol() = %d\n", err);
+
+ err = phy_set_mode_ext(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface);
+ if (err)
+ netdev_err(mac->net_dev, "phy_set_mode_ext() = %d\n", err);
}
static void dpaa2_mac_link_up(struct phylink_config *config,
@@ -346,10 +384,23 @@ static void dpaa2_pcs_destroy(struct dpaa2_mac *mac)
}
}
+void dpaa2_mac_start(struct dpaa2_mac *mac)
+{
+ if (mac->serdes_phy)
+ phy_power_on(mac->serdes_phy);
+}
+
+void dpaa2_mac_stop(struct dpaa2_mac *mac)
+{
+ if (mac->serdes_phy)
+ phy_power_off(mac->serdes_phy);
+}
+
int dpaa2_mac_connect(struct dpaa2_mac *mac)
{
struct net_device *net_dev = mac->net_dev;
struct fwnode_handle *dpmac_node;
+ struct phy *serdes_phy = NULL;
struct phylink *phylink;
int err;
@@ -366,6 +417,20 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac)
return -EINVAL;
mac->if_mode = err;
+ if (mac->features & DPAA2_MAC_FEATURE_PROTOCOL_CHANGE &&
+ !phy_interface_mode_is_rgmii(mac->if_mode) &&
+ is_of_node(dpmac_node)) {
+ serdes_phy = of_phy_get(to_of_node(dpmac_node), NULL);
+
+ if (serdes_phy == ERR_PTR(-ENODEV))
+ serdes_phy = NULL;
+ else if (IS_ERR(serdes_phy))
+ return PTR_ERR(serdes_phy);
+ else
+ phy_init(serdes_phy);
+ }
+ mac->serdes_phy = serdes_phy;
+
/* The MAC does not have the capability to add RGMII delays so
* error out if the interface mode requests them and there is no PHY
* to act upon them
@@ -429,6 +494,8 @@ void dpaa2_mac_disconnect(struct dpaa2_mac *mac)
rtnl_unlock();
phylink_destroy(mac->phylink);
dpaa2_pcs_destroy(mac);
+ of_phy_put(mac->serdes_phy);
+ mac->serdes_phy = NULL;
}
int dpaa2_mac_open(struct dpaa2_mac *mac)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
index 1d107b99053e..09163dd210be 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.h
@@ -28,6 +28,7 @@ struct dpaa2_mac {
enum dpmac_link_type if_link_type;
struct lynx_pcs *pcs;
struct fwnode_handle *fw_node;
+ struct phy *serdes_phy;
struct led_classdev *link_status_led;
};
@@ -49,4 +50,8 @@ void dpaa2_mac_get_strings(u8 *data);
void dpaa2_mac_get_ethtool_stats(struct dpaa2_mac *mac, u64 *data);
+void dpaa2_mac_start(struct dpaa2_mac *mac);
+
+void dpaa2_mac_stop(struct dpaa2_mac *mac);
+
#endif /* DPAA2_MAC_H */
--
2.38.1
patches/linux-LSDK-21.08/0041-HACK-dpaa2-mac-only-validate-link-modes-supported-by.patch 0 → 100644
View file @ db443a11
From 3fef5ab21bebab810df37f7b737889848651a986 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 13:56:44 +0200
Subject: [PATCH 41/45] HACK: dpaa2-mac: only validate link modes supported by
serdes phy
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
index 815cd0018980..4452a056b580 100644
--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
@@ -190,10 +190,17 @@ static void dpaa2_mac_validate(struct phylink_config *config,
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
if (state->interface != PHY_INTERFACE_MODE_NA &&
+ !mac->serdes_phy &&
dpaa2_mac_phy_mode_mismatch(mac, state->interface)) {
goto empty_set;
}
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ mac->serdes_phy &&
+ phy_validate(mac->serdes_phy, PHY_MODE_ETHERNET, state->interface, NULL)) {
+ goto empty_set;
+ }
+
phylink_set_port_modes(mask);
phylink_set(mask, Autoneg);
phylink_set(mask, Pause);
--
2.38.1
patches/linux-LSDK-21.08/0042-arch-arm64-dts-lx2160a-describe-the-SerDes-block-1.patch 0 → 100644
View file @ db443a11
From c29576ac49708fb4d783ea49e17edb4226c0c1d3 Mon Sep 17 00:00:00 2001
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: Fri, 11 Mar 2022 23:22:28 +0200
Subject: [PATCH 42/45] arch: arm64: dts: lx2160a: describe the SerDes block #1
Describe the SerDes block #1 using the generic phys infrastructure. This
way, the ethernet nodes can each reference their serdes lanes
individually using the 'phys' dts property.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 74ae703e0f53..e1c900b71f7d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -63,21 +63,25 @@ sfp3: sfp-3 {
&dpmac7 {
sfp = <&sfp0>;
managed = "in-band-status";
+ phys = <&serdes_1 3>;
};
&dpmac8 {
sfp = <&sfp1>;
managed = "in-band-status";
+ phys = <&serdes_1 2>;
};
&dpmac9 {
sfp = <&sfp2>;
managed = "in-band-status";
+ phys = <&serdes_1 1>;
};
&dpmac10 {
sfp = <&sfp3>;
managed = "in-band-status";
+ phys = <&serdes_1 0>;
};
&emdio2 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 23b48824b139..f78e478a094e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -613,6 +613,12 @@ soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ serdes_1: phy@1ea0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ };
+
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.38.1
patches/linux-LSDK-21.08/0043-arch-arm64-dts-lx2160a-describe-the-SerDes-block-2.patch 0 → 100644
View file @ db443a11
From 0cbebae9215bbbcd92fa101cd7d563c172b0b730 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 10:53:33 +0200
Subject: [PATCH 43/45] arch: arm64: dts: lx2160a: describe the SerDes block #2
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index f78e478a094e..23ade0a13ca6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -619,6 +619,12 @@ serdes_1: phy@1ea0000 {
#phy-cells = <1>;
};
+ serdes_2: phy@1eb0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ };
+
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.38.1
patches/linux-LSDK-21.08/0044-arm64-dts-lx2160a-half-twins-update-serdes-reference.patch 0 → 100644
View file @ db443a11
From a77f6bf8f2007426ab6c356e2377696a186dfa3e Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 11:02:26 +0200
Subject: [PATCH 44/45] arm64: dts: lx2160a-half-twins: update serdes
references for new driver
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../dts/freescale/fsl-lx2160a-half-twins.dts | 32 +++++++++----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
index e3175b5f5234..2dd8553ebd1f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -386,89 +386,89 @@ led_ht_c3_bb: led-ht-c3-bb {
&dpmac3 {
sfp = <&c1_at_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_h>;
+ phys = <&serdes_1 7>;
link-status-led = <&led_c1_at>;
};
&dpmac4 {
sfp = <&c1_bt_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_g>;
+ phys = <&serdes_1 6>;
link-status-led = <&led_c1_bt>;
};
&dpmac5 {
sfp = <&ht_c3_bt_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_f>;
+ phys = <&serdes_1 5>;
link-status-led = <&led_ht_c3_bt>;
};
&dpmac6 {
sfp = <&ht_c3_at_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_e>;
+ phys = <&serdes_1 4>;
link-status-led = <&led_ht_c3_at>;
};
&dpmac7 {
sfp = <&c2_at_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_d>;
+ phys = <&serdes_1 3>;
link-status-led = <&led_c2_at>;
};
&dpmac8 {
sfp = <&c2_bt_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_c>;
+ phys = <&serdes_1 2>;
link-status-led = <&led_c2_bt>;
};
&dpmac9 {
sfp = <&c3_at_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_b>;
+ phys = <&serdes_1 1>;
link-status-led = <&led_c3_at>;
};
&dpmac10 {
sfp = <&c3_bt_sfp>;
managed = "in-band-status";
- phys = <&serdes1_lane_a>;
+ phys = <&serdes_1 0>;
link-status-led = <&led_c3_bt>;
};
/* SD2 lanes #0.. #7 */
&dpmac11 {
sfp = <&ht_c3_ab_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_a>;
+ phys = <&serdes_2 0>;
link-status-led = <&led_ht_c3_ab>;
};
&dpmac12 {
sfp = <&c1_ab_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_b>;
+ phys = <&serdes_2 1>;
link-status-led = <&led_c1_ab>;
};
&dpmac13 { // ok
sfp = <&c3_ab_sfp>;
managed = "in-band-status";
phy-mode = "sgmii";
- phys = <&serdes2_lane_g>;
+ phys = <&serdes_2 6>;
link-status-led = <&led_c3_ab>;
};
&dpmac14 { // ok
sfp = <&c3_bb_sfp>;
managed = "in-band-status";
phy-mode = "sgmii";
- phys = <&serdes2_lane_h>;
+ phys = <&serdes_2 7>;
link-status-led = <&led_c3_bb>;
};
&dpmac15 {
sfp = <&ht_c3_bb_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_e>;
+ phys = <&serdes_2 4>;
link-status-led = <&led_ht_c3_bb>;
};
&dpmac16 {
sfp = <&c2_bb_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_f>;
+ phys = <&serdes_2 5>;
link-status-led = <&led_c2_bb>;
};
&dpmac17 {
@@ -476,13 +476,13 @@ &dpmac17 {
/delete-property/ phy-connection-type;
sfp = <&c1_bb_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_c>;
+ phys = <&serdes_2 2>;
link-status-led = <&led_c1_bb>;
};
&dpmac18 {
sfp = <&c2_ab_sfp>;
managed = "in-band-status";
- phys = <&serdes2_lane_d>;
+ phys = <&serdes_2 3>;
link-status-led = <&led_c2_ab>;
};
--
2.38.1
patches/linux-LSDK-21.08/0045-arm64-dts-lx2162-clearfog-update-serdes-references-f.patch 0 → 100644
View file @ db443a11
From 4a9b40732e43171cabc031ef2a8bacb5766a6680 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Nov 2022 11:05:30 +0200
Subject: [PATCH 45/45] arm64: dts: lx2162-clearfog: update serdes references
for new driver
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../dts/freescale/fsl-lx2162a-clearfog.dts | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index d21717592183..c949d260e3ae 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -190,7 +190,7 @@ pcieclk@6b {
/* upper 10G connector */
&dpmac3 {
status = "okay";
- phys = <&serdes1_lane_h>;
+ phys = <&serdes_1 7>;
managed = "in-band-status";
sfp = <&sfp_at>;
link-status-led = <&led_sfp_at>;
@@ -203,7 +203,7 @@ &pcs_mdio3 {
/* lower 10G connector */
&dpmac4 {
status = "okay";
- phys = <&serdes1_lane_g>;
+ phys = <&serdes_1 6>;
managed = "in-band-status";
sfp = <&sfp_ab>;
link-status-led = <&led_sfp_ab>;
@@ -215,7 +215,7 @@ &pcs_mdio4 {
&dpmac5 {
status = "okay";
- phys = <&serdes1_lane_f>;
+ phys = <&serdes_1 5>;
managed = "in-band-status";
sfp = <&sfp_bt>;
link-status-led = <&led_sfp_bt>;
@@ -227,7 +227,7 @@ &pcs_mdio5 {
&dpmac6 {
status = "okay";
- phys = <&serdes1_lane_e>;
+ phys = <&serdes_1 4>;
managed = "in-band-status";
sfp = <&sfp_bb>;
link-status-led = <&led_sfp_bb>;
@@ -288,7 +288,7 @@ &serdes_1 {
&dpmac11 {
status = "okay";
- phys = <&serdes2_lane_a>;
+ phys = <&serdes_2 0>;
phy-handle = <&ethernet_phy2>;
phy-mode = "rgmii";
};
@@ -299,7 +299,7 @@ &pcs_mdio11 {
&dpmac12 {
status = "okay";
- phys = <&serdes2_lane_b>;
+ phys = <&serdes_2 1>;
phy-handle = <&ethernet_phy0>;
phy-mode = "rgmii";
};
@@ -314,7 +314,7 @@ &dpmac17 {
/delete-property/ phy-connection-type;
status = "okay";
- phys = <&serdes2_lane_c>;
+ phys = <&serdes_2 2>;
phy-handle = <&ethernet_phy4>;
phy-mode = "rgmii";
};
@@ -325,7 +325,7 @@ &pcs_mdio17 {
&dpmac18 {
status = "okay";
- phys = <&serdes2_lane_d>;
+ phys = <&serdes_2 3>;
phy-handle = <&ethernet_phy6>;
phy-mode = "rgmii";
};
@@ -336,7 +336,7 @@ &pcs_mdio18 {
&dpmac15 {
status = "okay";
- phys = <&serdes2_lane_e>;
+ phys = <&serdes_2 4>;
phy-handle = <&ethernet_phy3>;
phy-mode = "rgmii";
};
@@ -347,7 +347,7 @@ &pcs_mdio15 {
&dpmac16 {
status = "okay";
- phys = <&serdes2_lane_f>;
+ phys = <&serdes_2 5>;
phy-handle = <&ethernet_phy1>;
phy-mode = "rgmii";
};
@@ -358,7 +358,7 @@ &pcs_mdio16 {
&dpmac13 {
status = "okay";
- phys = <&serdes2_lane_g>;
+ phys = <&serdes_2 6>;
phy-handle = <&ethernet_phy5>;
phy-mode = "rgmii";
};
@@ -369,7 +369,7 @@ &pcs_mdio13 {
&dpmac14 {
status = "okay";
- phys = <&serdes2_lane_h>;
+ phys = <&serdes_2 7>;
phy-handle = <&ethernet_phy7>;
phy-mode = "rgmii";
};
--
2.38.1
runme.sh
View file @ db443a11
......@@ -59,7 +59,7 @@ case "${SERDES}" in
DPL=dpl-eth.8x10g.8x1g.dtb
# MC 10.28.1 is incapable of mapping all 16 dpnis. 10.28.100 fixes that
if [ "x$RELEASE" == "xLSDK-21.08" ]; then
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
fi
;;
2_*)
......@@ -119,19 +119,19 @@ case "${SERDES}" in
DPC=LX2162-USOM/clearfog-s1_0-s2_7-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_7-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
;;
LX2162A_CLEARFOG_0_9_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_9-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_9-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
;;
LX2162A_CLEARFOG_0_11_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_11-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_11-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
MC_FORCE=patches/mc_10.28.100_lx2160a.itb
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
;;
LX2162A_CLEARFOG_3_0_*)
DPC=LX2162-USOM/clearfog-s1_3-s2_0-dpc.dtb
......@@ -640,7 +640,8 @@ if [ "x$RELEASE" == "xLSDK-20.04" ]; then
else
if [ "x$MC_FORCE" == "x" ]; then
MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/ | grep -v sha256sum | cut -f1`
dd if=$ROOTDIR/build/qoriq-mc-binary/lx216xa/${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
MC=`ls $ROOTDIR/build/qoriq-mc-binary/lx216?a/${MC}`
dd if=${MC} of=images/${IMG} bs=512 seek=20480 conv=notrunc
else
echo "Forcing MC firmware selection"
MC=$MC_FORCE
......
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