rcw: add commented examples for serdes protocols 1_13_3

patches/rcw-LSDK-21.08/0029-add-commented-examples-for-serdes-protocols-1_13_3.patch

+From 2c40e89325426990de287b09ae5e8543eb5215aa Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Thu, 24 Aug 2023 13:11:59 +0200
+Subject: [PATCH] add commented examples for serdes protocols 1_13_3
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_SD1_1.rcwi  | 21 +++++++++++++++++++++
+ lx2160acex7/configs/lx2160a_SD1_1S.rcwi | 25 +++++++++++++++++++++++++
+ lx2160acex7/configs/lx2160a_SD2_13.rcwi | 19 +++++++++++++++++++
+ lx2160acex7/configs/lx2160a_SD3_3.rcwi  | 20 ++++++++++++++++++++
+ 4 files changed, 85 insertions(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_1.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_1S.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD1_1.rcwi b/lx2160acex7/configs/lx2160a_SD1_1.rcwi
+new file mode 100644
+index 0000000..07b8f3d
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_1.rcwi
+@@ -0,0 +1,21 @@
++/* Serdes 1 Protocol 1: 2xPCI-e-x4 */
++SRDS_PRTCL_S1=1
++
++/* Disable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Don't use Serdes 1 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for pcie gen 3 (not available): Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 100MHz for pcie (not documented in RM): Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
++
++/* Configure Serdes 1 PCIe frequency divider for max. 5Gbps data rate (gen 1+2) */
++SRDS_DIV_PEX_S1=2
+diff --git a/lx2160acex7/configs/lx2160a_SD1_1S.rcwi b/lx2160acex7/configs/lx2160a_SD1_1S.rcwi
+new file mode 100644
+index 0000000..60af037
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_1S.rcwi
+@@ -0,0 +1,25 @@
++/* Serdes 1 Protocol 1: 2xPCI-e-x4 */
++SRDS_PRTCL_S1=1
++
++/* Enable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/*
++ * Use Serdes 1 PLLF for PLLS
++ *
++ * Note: PLLF reference clock must be 100MHz (assembly-option on CEX-7)
++ */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for pcie gen 3: Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 100MHz for pcie (not documented in RM): Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
++
++/* Configure Serdes 1 PCIe frequency divider for max. 8Gbps data rate (gen 1+2+3) */
++SRDS_DIV_PEX_S1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD2_13.rcwi b/lx2160acex7/configs/lx2160a_SD2_13.rcwi
+index 85c3687..0f04664 100644
+--- a/lx2160acex7/configs/lx2160a_SD2_13.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD2_13.rcwi
+@@ -1,2 +1,21 @@
++/* Serdes 2 Protocol 13: 1xPCI-e-x4, 1xPCI-e-x2, 2x1Gbps */
+ SRDS_PRTCL_S2=13
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/* Don't use Serdes 2 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz for pcie gen 3: Bit 0 = 0
++ * Select Serdes 2 PLLS frequency 100MHz for pcie and sgmii: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
+ SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Configure Serdes 2 PCIe frequency divider for max. 8Gbps data rate (gen 1+2+3) */
++SRDS_DIV_PEX_S2=1
+diff --git a/lx2160acex7/configs/lx2160a_SD3_3.rcwi b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+index 4695755..82566a2 100644
+--- a/lx2160acex7/configs/lx2160a_SD3_3.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+@@ -1 +1,21 @@
++/* Serdes 3 Protocol 0: 2xPCI-e-x4 */
+ SRDS_PRTCL_S3=3
++
++/* Enable Serdes 3 PLLS */
++SRDS_PLL_PD_PLL6=0
++
++/* Don't use Serdes 3 PLLF as reference for PLLS */
++SRDS_INTRA_REF_CLK_S3=0
++
++/* Enable Serdes 3 PLLS */
++SRDS_PLL_PD_PLL6=0
++
++/*
++ * Select Serdes 3 PLLF frequency 100MHz for pcie gen 3: Bit 0 = 0
++ * Select Serdes 3 PLLS frequency 100MHz for pcie: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S3=0
++
++/* Configure Serdes 3 PCIe frequency divider for max. 8Gbps data rate (gen 1+2+3) */
++SRDS_DIV_PEX_S3=1
+-- 
+2.35.3
+