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Commit ed87dd1c authored by Rabeeh Khoury's avatar Rabeeh Khoury
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Add half-twins motherboard support 

1. Half twins is 8xSFP+ and 8xSFP with OCPv3 NIC support board
2. Using SD1=8S (PLLF=100MHz, PLLS=161.132825MHz) runtime downgrade from
10G to 1G, according to SFP module inserted is not supported
3. Reverted default DDR speed to 3200
Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent dda96e53
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Showing with 1492 additions and 5 deletions
configs/linux/lx2k_additions.config
View file @ ed87dd1c
......@@ -44,5 +44,15 @@ CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_SFP=y
CONFIG_PHY_FSL_SERDES_28G=y
CONFIG_I40E=y
CONFIG_I40EVF=y
CONFIG_IAVF=y
CONFIG_MARVELL_PHY=y
CONFIG_NAMESPACES=y
CONFIG_MARVELL_10G_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_MICROCHIP_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_LEDS_TRIGGER_NETDEV=y
#CONFIG_VFIO_PCI=n
patches/linux-LSDK-21.08/0012-arm64-dts-add-lx2160a-based-half-twins.patch 0 → 100644
View file @ ed87dd1c
From 060972a650e4403068734119528b40c9a33a4cbc Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 18:11:37 +0300
Subject: [PATCH] arm64: dts: add lx2160a based half twins
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/fsl-lx2160a-half-twins.dts | 495 ++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 42 ++
3 files changed, 538 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index eaf7319389b6..bf51a3cfeda7 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-solidnet.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
new file mode 100644
index 000000000000..ebde6c03f545
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160A based half twins
+//
+// Copyright 2022 SolidRun Ltd.
+
+/dts-v1/;
+
+#include "fsl-lx2160a-cex7.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "SolidRun LX2160A Twins";
+ compatible = "solidrun,clearfog-twins",
+ "solidrun,lx2160a-cex7", "fsl,lx2160a";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c2 {
+ i2c-switch@76 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x76>;
+ i2c-mux-idle-disconnect;
+ twins_sfp_c1_at_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ twins_sfp_c1_ab_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ twins_sfp_c1_bt_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ twins_sfp_c1_bb_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ twins_sfp_c2_at_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ twins_sfp_c2_ab_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ };
+ i2c-switch@77 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ twins_sfp_c2_bt_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ twins_sfp_c2_bb_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ twins_sfp_c3_at_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ twins_sfp_c3_ab_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ twins_sfp_c3_bt_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ twins_sfp_c3_bb_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ };
+ expander0: gpio-expander@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ expander1: gpio-expander@21 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ /* Half twins configuration; take over c3 from the other twin side */
+ i2c-switch@73 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+ htwins_sfp_c3_at_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ htwins_sfp_c3_ab_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ htwins_sfp_c3_bt_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ htwins_sfp_c3_bb_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ };
+ expander2: gpio-expander@24 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x24>;
+ };
+ expander3: gpio-expander@25 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x25>;
+ };
+};
+
+/ {
+ c1_at_sfp: c1-at-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_at_i2c>;
+ mod-def0-gpio = <&expander0 1 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c1_ab_sfp: c1-ab-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_ab_i2c>;
+ mod-def0-gpio = <&expander0 2 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c1_bt_sfp: c1-bt-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_bt_i2c>;
+ mod-def0-gpio = <&expander0 3 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c1_bb_sfp: c1-bb-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_bb_i2c>;
+ mod-def0-gpio = <&expander0 4 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c2_at_sfp: c2-at-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_at_i2c>;
+ mod-def0-gpio = <&expander0 5 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c2_ab_sfp: c2-ab-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_ab_i2c>;
+ mod-def0-gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c2_bt_sfp: c2-bt-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_bt_i2c>;
+ mod-def0-gpio = <&expander0 9 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c2_bb_sfp: c2-bb-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_bb_i2c>;
+ mod-def0-gpio = <&expander0 10 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c3_at_sfp: c3-at-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_at_i2c>;
+ mod-def0-gpio = <&expander0 11 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c3_ab_sfp: c3-ab-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_ab_i2c>;
+ mod-def0-gpio = <&expander0 12 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c3_bt_sfp: c3-bt-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_bt_i2c>;
+ mod-def0-gpio = <&expander0 13 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ c3_bb_sfp: c3-bb-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_bb_i2c>;
+ mod-def0-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ ht_c3_at_sfp: ht-c3-at-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_at_i2c>;
+ mod-def0-gpio = <&expander2 11 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ ht_c3_ab_sfp: ht-c3-ab-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_ab_i2c>;
+ mod-def0-gpio = <&expander2 12 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ ht_c3_bt_sfp: ht-c3-bt-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_bt_i2c>;
+ mod-def0-gpio = <&expander2 13 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ ht_c3_bb_sfp: ht-c3-bb-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_bb_i2c>;
+ mod-def0-gpio = <&expander2 14 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+ leds {
+ compatible = "gpio-leds";
+ led_c1_at {
+ gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c1_ab {
+ gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c1_bt {
+ gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c1_bb {
+ gpios = <&expander1 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c2_at {
+ gpios = <&expander1 5 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c2_ab {
+ gpios = <&expander1 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c2_bt {
+ gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c2_bb {
+ gpios = <&expander1 10 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c3_at {
+ gpios = <&expander1 11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c3_ab {
+ gpios = <&expander1 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c3_bt {
+ gpios = <&expander1 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_c3_bb {
+ gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_ht_c3_at {
+ gpios = <&expander3 11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_ht_c3_ab {
+ gpios = <&expander3 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_ht_c3_bt {
+ gpios = <&expander3 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ led_ht_c3_bb {
+ gpios = <&expander3 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ };
+};
+
+/* SD1 lanes #0.. #7 */
+&dpmac3 {
+ sfp = <&c1_at_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_h>;
+};
+&dpmac4 {
+ sfp = <&c1_bt_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_g>;
+};
+&dpmac5 {
+ sfp = <&ht_c3_bt_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_f>;
+};
+&dpmac6 {
+ sfp = <&ht_c3_at_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_e>;
+};
+&dpmac7 {
+ sfp = <&c2_at_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_d>;
+};
+&dpmac8 {
+ sfp = <&c2_bt_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_c>;
+};
+&dpmac9 {
+ sfp = <&c3_at_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_b>;
+};
+&dpmac10 {
+ sfp = <&c3_bt_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes1_lane_a>;
+};
+/* SD2 lanes #0.. #7 */
+&dpmac11 {
+ sfp = <&ht_c3_ab_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_a>;
+};
+
+&dpmac12 {
+ sfp = <&c1_ab_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_b>;
+};
+&dpmac13 { // ok
+ sfp = <&c3_ab_sfp>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phys = <&serdes2_lane_g>;
+};
+&dpmac14 { // ok
+ sfp = <&c3_bb_sfp>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phys = <&serdes2_lane_h>;
+};
+&dpmac15 {
+ sfp = <&ht_c3_bb_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_e>;
+};
+&dpmac16 {
+ sfp = <&c2_bb_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_f>;
+};
+&dpmac17 {
+ /delete-property/ phy_handle;
+ /delete-property/ phy-connection-type;
+ sfp = <&c1_bb_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_c>;
+};
+&dpmac18 {
+ sfp = <&c2_ab_sfp>;
+ managed = "in-band-status";
+ phys = <&serdes2_lane_d>;
+};
+
+&emdio1 {
+ status = "disabled";
+};
+
+&emdio2 {
+ status = "disabled";
+};
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+&pcs_mdio3 {
+ status = "okay";
+};
+&pcs_mdio4 {
+ status = "okay";
+};
+&pcs_mdio5 {
+ status = "okay";
+};
+&pcs_mdio6 {
+ status = "okay";
+};
+&pcs_mdio7 {
+ status = "okay";
+};
+&pcs_mdio8 {
+ status = "okay";
+};
+&pcs_mdio9 {
+ status = "okay";
+};
+&pcs_mdio10 {
+ status = "okay";
+};
+&pcs_mdio11 {
+ status = "okay";
+};
+&pcs_mdio12 {
+ status = "okay";
+};
+&pcs_mdio13 {
+ status = "okay";
+};
+&pcs_mdio14 {
+ status = "okay";
+};
+&pcs_mdio15 {
+ status = "okay";
+};
+&pcs_mdio16 {
+ status = "okay";
+};
+&pcs_mdio17 {
+ status = "okay";
+};
+&pcs_mdio18 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c493b889c2a8..b39d9cf4a95e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -654,6 +654,48 @@ serdes1_lane_h: phy@7 {
};
};
+
+ serdes_2: serdes_phy@1eb0000 {
+ compatible = "fsl,serdes-28g";
+ reg = <0x00 0x1eb0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+ serdes2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.25.1
patches/mc-utils/0007-lx2160acex7-half-twins-configuration.patch 0 → 100644
View file @ ed87dd1c
From a9b6cf5a8c7d32f0d4257c31ddd0e8b55d0be568 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 13:52:39 +0300
Subject: [PATCH 7/7] lx2160acex7: half-twins configuration
1. The configuration is 8x10Gbps on SD1 and 8x1Gbps on SD2
2. 16 DPMACs
3. All MACs are either ls-addni added for the kernel or thru
dynamic_dpl.sh for dpdk applications
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts | 124 ++++++++++++
config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts | 177 ++++++++++++++++++
2 files changed, 301 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
create mode 100644 config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
diff --git a/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
new file mode 100644
index 0000000..354de30
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
@@ -0,0 +1,124 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@7 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@8 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@9 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@10 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@11 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@15 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts b/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
new file mode 100644
index 0000000..6c859be
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
@@ -0,0 +1,177 @@
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>;
+ };
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ dpmac@3 {
+ };
+ dpmac@4 {
+ };
+ dpmac@5 {
+ };
+ dpmac@6 {
+ };
+ dpmac@7 {
+ };
+ dpmac@8 {
+ };
+ dpmac@9 {
+ };
+ dpmac@10 {
+ };
+ dpmac@11 {
+ };
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@15 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ };
+};
--
2.25.1
patches/rcw-LSDK-21.08/0018-lx2160acex7-add-SD1-8S-swapped-PLLF-PLLS-and-SD2-9.patch 0 → 100644
View file @ ed87dd1c
From d3a7bd878bc70d105da0edf3362b5f268237f2a1 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 18:14:26 +0300
Subject: [PATCH] lx2160acex7: add SD1-8S (swapped PLLF/PLLS) and SD2-9
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_8S.rcwi | 2 ++
lx2160acex7/configs/lx2160a_SD2_9.rcwi | 2 ++
2 files changed, 4 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_8S.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_8S.rcwi b/lx2160acex7/configs/lx2160a_SD1_8S.rcwi
new file mode 100644
index 0000000..a5eea0e
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_8S.rcwi
@@ -0,0 +1,2 @@
+SRDS_PRTCL_S1=8
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_SD2_9.rcwi b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
index c3e03a5..b3ee906 100644
--- a/lx2160acex7/configs/lx2160a_SD2_9.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
@@ -1 +1,3 @@
SRDS_PRTCL_S2=9
+EC1_PMUX=1
+EC2_PMUX=1
--
2.25.1
patches/u-boot-LSDK-21.08/0037-lx2160acex7-add-8-x-x-and-half-twins-device-tree.patch 0 → 100644
View file @ ed87dd1c
From b56915cf64a7eae9633c8e0b11b34259ed7c7f30 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 17:06:24 +0300
Subject: [PATCH] lx2160acex7: add 8-x-x and half twins device tree
1. Add 8-x-x SERDES configuration device tree. Mainly used for ClearFog
CX/HoneyComb with the default 8/5/2 SERDES configuration.
2. Add new machine half-twins (SERDES configuration 8/9/2) - tota 8x10G
and 8x1G with PCIe connected to OCP card
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-lx2160a-cex7-8-x-x.dts | 196 ++++++++++++++++
arch/arm/dts/fsl-lx2160a-half-twins-8-9-x.dts | 215 ++++++++++++++++++
board/solidrun/lx2160a/eth_lx2160acex7.c | 27 ++-
configs/lx2160acex7_tfa_defconfig | 2 +-
5 files changed, 440 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2160a-cex7-8-x-x.dts
create mode 100644 arch/arm/dts/fsl-lx2160a-half-twins-8-9-x.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 861346835..b084ee0fa 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -426,6 +426,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2162a-qds-18-x.dtb\
fsl-lx2162a-qds-20-x.dtb\
fsl-lx2160a-cex7.dtb \
+ fsl-lx2160a-cex7-8-x-x.dtb \
+ fsl-lx2160a-half-twins-8-9-x.dtb \
fsl-lx2162a-som.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-cex7-8-x-x.dts b/arch/arm/dts/fsl-lx2160a-cex7-8-x-x.dts
new file mode 100644
index 000000000..0cc95fa2d
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-cex7-8-x-x.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2160ACEX7 device tree source
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * Copyright 2019 SolidRun ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160ACEX7 COM express type 7 based board";
+ compatible = "fsl,lx2160acex7", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+ };
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+
+&dpmac5 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac9 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac10 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: MT35XU512ABA1G12@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+/* The following eeprin is reserved so that the 2Kb eeprom at address 0x57
+ would be used as TLV eeprom.
+ 24aa512@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+*/
+ spd1@51 {
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+ spd2@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ ltc3882@5c {
+ compatible = "ltc3882";
+ reg = <0x5c>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@48 {
+ compatible = "nxp,sa56004";
+ reg = <0x48>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a-half-twins-8-9-x.dts b/arch/arm/dts/fsl-lx2160a-half-twins-8-9-x.dts
new file mode 100644
index 000000000..5672e7368
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-half-twins-8-9-x.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * SolidRun LX2160ACEX7 device tree source
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * Copyright 2019 SolidRun ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun Half Twins Board";
+ compatible = "fsl,lx2160acex7", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+ };
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac9 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac10 {
+ status = "okay";
+ phy-connection-type = "xgmii";
+};
+
+&dpmac11 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac12 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac13 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac14 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac15 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac16 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-connection-type = "sgmii";
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: MT35XU512ABA1G12@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+/* The following eeprin is reserved so that the 2Kb eeprom at address 0x57
+ would be used as TLV eeprom.
+ 24aa512@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+*/
+ spd1@51 {
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+ spd2@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ ltc3882@5c {
+ compatible = "ltc3882";
+ reg = <0x5c>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@48 {
+ compatible = "nxp,sa56004";
+ reg = <0x48>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ expander2: pca9555@24 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x24>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+};
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index abca006d2..6a696deaf 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -223,6 +223,7 @@ static struct serdes_configuration {
{2, 2, false},
{2, 3, false},
{2, 5, false},
+ {2, 9, true},
{2, 10, false},
{2, 11, true},
{2, 12, true},
@@ -265,11 +266,33 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1, srds_s2;
+ u32 rcw_status = in_le32(&gur->rcwsr[28]);
+
+ srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
if (get_svr() & 0x800) {
if (!strncmp(name, "fsl-lx2162a-som", 15)) {
return 0;
}
} else {
+ /* Notice - order of matching is similar to order of CONFIG_OF_LIST */
+ if (srds_s1 == 8) {
+ if (srds_s2 == 9) { /* Half-twins board */
+ if (!strncmp(name, "fsl-lx2160a-half-twins-8-9-x", 28)) {
+ return 0;
+ }
+ }
+ if (srds_s2 <= 5) { /* No network with SD2 <= 5 */
+ if (!strncmp(name, "fsl-lx2160a-cex7-8-x-x", 22)) {
+ return 0;
+ }
+ }
+ }
if (!strncmp(name, "fsl-lx2160a-cex7", 16)) return 0;
}
@@ -350,7 +373,9 @@ int fsl_board_late_init(void) {
printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
srds_s1);
}
- sprintf(expected_dts, "fsl-lx2160a-clearfog-cx.dtb");
+ if ((srds_s1 == 8) && ((srds_s2 == 9) || (srds_s2 == 2))) {
+ sprintf(expected_dts, "fsl-lx2160a-half-twins.dtb");
+ } else sprintf(expected_dts, "fsl-lx2160a-clearfog-cx.dtb");
}
env_set("fdtfile", expected_dts);
return 0;
diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
index ba3568646..3dd227251 100644
--- a/configs/lx2160acex7_tfa_defconfig
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -40,7 +40,7 @@ CONFIG_CMD_NVME=y
CONFIG_NVME=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="fsl-lx2160a-cex7 fsl-lx2162a-som"
+CONFIG_OF_LIST="fsl-lx2160a-half-twins-8-9-x fsl-lx2160a-cex7-8-x-x fsl-lx2160a-cex7 fsl-lx2162a-som"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
--
2.25.1
runme.sh
View file @ ed87dd1c
......@@ -13,7 +13,7 @@ BUILDROOT_VERSION=2020.02.1
# Misc
###############################################################################
: ${RELEASE:=LSDK-21.08}
: ${DDR_SPEED:=2600}
: ${DDR_SPEED:=3200}
: ${SERDES:=8_5_2}
: ${UEFI_RELEASE:=RELEASE}
: ${SHALLOW:=false}
......@@ -23,7 +23,7 @@ BUILDROOT_VERSION=2020.02.1
: ${BR2_PRIMARY_SITE:=} # custom buildroot mirror
if [ "x$SHALLOW" == "xtrue" ]; then
SHALLOW_FLAG="--depth 1"
SHALLOW_FLAG="--depth 1000"
fi
if [ "x$ATF_DEBUG" == "xtrue" ]; then
......@@ -53,9 +53,9 @@ case "${SERDES}" in
DPC=dpc-8_x_usxgmii.dtb
DPL=dpl-eth.8x10g.19.dtb
;;
8_9_*)
8_9_*|8S_9_*)
DPC=dpc-8_x_usxgmii_8_x_sgmii.dtb
DPL=dpl-eth.8x10g.8x1g.19.dtb
DPL=dpl-eth.8x10g.8x1g.dtb
;;
2_*)
DPC=dpc-8_x_usxgmii.dtb
......
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