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Commit ed87dd1c authored by Rabeeh Khoury's avatar Rabeeh Khoury
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Add half-twins motherboard support 

1. Half twins is 8xSFP+ and 8xSFP with OCPv3 NIC support board
2. Using SD1=8S (PLLF=100MHz, PLLS=161.132825MHz) runtime downgrade from
10G to 1G, according to SFP module inserted is not supported
3. Reverted default DDR speed to 3200
Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent dda96e53
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Showing with 1492 additions and 5 deletions
configs/linux/lx2k_additions.config
View file @ ed87dd1c
...@@ -44,5 +44,15 @@ CONFIG_CRYPTO_USER_API_RNG=y ...@@ -44,5 +44,15 @@ CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_SFP=y CONFIG_SFP=y
CONFIG_PHY_FSL_SERDES_28G=y CONFIG_PHY_FSL_SERDES_28G=y
CONFIG_I40E=y
CONFIG_I40EVF=y
CONFIG_IAVF=y
CONFIG_MARVELL_PHY=y CONFIG_MARVELL_PHY=y
CONFIG_NAMESPACES=y CONFIG_MARVELL_10G_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_MICROCHIP_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_LEDS_TRIGGER_NETDEV=y
#CONFIG_VFIO_PCI=n
patches/mc-utils/0007-lx2160acex7-half-twins-configuration.patch 0 → 100644
View file @ ed87dd1c
From a9b6cf5a8c7d32f0d4257c31ddd0e8b55d0be568 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 13:52:39 +0300
Subject: [PATCH 7/7] lx2160acex7: half-twins configuration
1. The configuration is 8x10Gbps on SD1 and 8x1Gbps on SD2
2. 16 DPMACs
3. All MACs are either ls-addni added for the kernel or thru
dynamic_dpl.sh for dpdk applications
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts | 124 ++++++++++++
config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts | 177 ++++++++++++++++++
2 files changed, 301 insertions(+)
create mode 100644 config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
create mode 100644 config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
diff --git a/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
new file mode 100644
index 0000000..354de30
--- /dev/null
+++ b/config/lx2160a/CEX7/dpc-8_x_usxgmii_8_x_sgmii.dts
@@ -0,0 +1,124 @@
+/*
+* Copyright 2018 NXP
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of the above-listed copyright holders nor the
+* names of any contributors may be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* This DPC showcases one Linux configuration for lx2160a boards.
+*/
+
+/dts-v1/;
+
+/ {
+
+ resources {
+
+ icid_pools {
+
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@7 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@8 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@9 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@10 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@11 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@12 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@13 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@14 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@15 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@16 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ mac@18 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts b/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
new file mode 100644
index 0000000..6c859be
--- /dev/null
+++ b/config/lx2160a/CEX7/dpl-eth.8x10g.8x1g.dts
@@ -0,0 +1,177 @@
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+
+ /* ------------ DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>;
+ };
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ dpmac@3 {
+ };
+ dpmac@4 {
+ };
+ dpmac@5 {
+ };
+ dpmac@6 {
+ };
+ dpmac@7 {
+ };
+ dpmac@8 {
+ };
+ dpmac@9 {
+ };
+ dpmac@10 {
+ };
+ dpmac@11 {
+ };
+ dpmac@12 {
+ };
+ dpmac@13 {
+ };
+ dpmac@14 {
+ };
+ dpmac@15 {
+ };
+ dpmac@16 {
+ };
+ dpmac@17 {
+ };
+ dpmac@18 {
+ };
+ dpmcp@1 {
+ };
+
+ dpmcp@2 {
+ };
+
+ dpmcp@3 {
+ };
+
+ dpmcp@4 {
+ };
+
+ dpmcp@5 {
+ };
+
+ dpmcp@6 {
+ };
+
+ dpmcp@7 {
+ };
+
+ dpmcp@8 {
+ };
+
+ dpmcp@9 {
+ };
+
+ dpmcp@10 {
+ };
+
+ dpmcp@11 {
+ };
+
+ dpmcp@12 {
+ };
+
+ dpmcp@13 {
+ };
+
+ dpmcp@14 {
+ };
+
+ dpmcp@15 {
+ };
+
+ dpmcp@16 {
+ };
+
+ dpmcp@17 {
+ };
+
+ dpmcp@18 {
+ };
+
+ dpmcp@19 {
+ };
+
+ dpmcp@20 {
+ };
+
+ dpmcp@21 {
+ };
+
+ dpmcp@22 {
+ };
+
+ dpmcp@23 {
+ };
+
+ dpmcp@24 {
+ };
+
+ dpmcp@25 {
+ };
+
+ dpmcp@26 {
+ };
+
+ dpmcp@27 {
+ };
+
+ dpmcp@28 {
+ };
+
+ dpmcp@29 {
+ };
+
+ dpmcp@30 {
+ };
+
+ dpmcp@31 {
+ };
+
+ dpmcp@32 {
+ };
+
+ dpmcp@33 {
+ };
+
+ dpmcp@34 {
+ };
+
+ dpmcp@35 {
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+ };
+};
--
2.25.1
patches/rcw-LSDK-21.08/0018-lx2160acex7-add-SD1-8S-swapped-PLLF-PLLS-and-SD2-9.patch 0 → 100644
View file @ ed87dd1c
From d3a7bd878bc70d105da0edf3362b5f268237f2a1 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 1 May 2022 18:14:26 +0300
Subject: [PATCH] lx2160acex7: add SD1-8S (swapped PLLF/PLLS) and SD2-9
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
lx2160acex7/configs/lx2160a_SD1_8S.rcwi | 2 ++
lx2160acex7/configs/lx2160a_SD2_9.rcwi | 2 ++
2 files changed, 4 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160a_SD1_8S.rcwi
diff --git a/lx2160acex7/configs/lx2160a_SD1_8S.rcwi b/lx2160acex7/configs/lx2160a_SD1_8S.rcwi
new file mode 100644
index 0000000..a5eea0e
--- /dev/null
+++ b/lx2160acex7/configs/lx2160a_SD1_8S.rcwi
@@ -0,0 +1,2 @@
+SRDS_PRTCL_S1=8
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160a_SD2_9.rcwi b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
index c3e03a5..b3ee906 100644
--- a/lx2160acex7/configs/lx2160a_SD2_9.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD2_9.rcwi
@@ -1 +1,3 @@
SRDS_PRTCL_S2=9
+EC1_PMUX=1
+EC2_PMUX=1
--
2.25.1
runme.sh
View file @ ed87dd1c
...@@ -13,7 +13,7 @@ BUILDROOT_VERSION=2020.02.1 ...@@ -13,7 +13,7 @@ BUILDROOT_VERSION=2020.02.1
# Misc # Misc
############################################################################### ###############################################################################
: ${RELEASE:=LSDK-21.08} : ${RELEASE:=LSDK-21.08}
: ${DDR_SPEED:=2600} : ${DDR_SPEED:=3200}
: ${SERDES:=8_5_2} : ${SERDES:=8_5_2}
: ${UEFI_RELEASE:=RELEASE} : ${UEFI_RELEASE:=RELEASE}
: ${SHALLOW:=false} : ${SHALLOW:=false}
...@@ -23,7 +23,7 @@ BUILDROOT_VERSION=2020.02.1 ...@@ -23,7 +23,7 @@ BUILDROOT_VERSION=2020.02.1
: ${BR2_PRIMARY_SITE:=} # custom buildroot mirror : ${BR2_PRIMARY_SITE:=} # custom buildroot mirror
if [ "x$SHALLOW" == "xtrue" ]; then if [ "x$SHALLOW" == "xtrue" ]; then
SHALLOW_FLAG="--depth 1" SHALLOW_FLAG="--depth 1000"
fi fi
if [ "x$ATF_DEBUG" == "xtrue" ]; then if [ "x$ATF_DEBUG" == "xtrue" ]; then
...@@ -53,9 +53,9 @@ case "${SERDES}" in ...@@ -53,9 +53,9 @@ case "${SERDES}" in
DPC=dpc-8_x_usxgmii.dtb DPC=dpc-8_x_usxgmii.dtb
DPL=dpl-eth.8x10g.19.dtb DPL=dpl-eth.8x10g.19.dtb
;; ;;
8_9_*) 8_9_*|8S_9_*)
DPC=dpc-8_x_usxgmii_8_x_sgmii.dtb DPC=dpc-8_x_usxgmii_8_x_sgmii.dtb
DPL=dpl-eth.8x10g.8x1g.19.dtb DPL=dpl-eth.8x10g.8x1g.dtb
;; ;;
2_*) 2_*)
DPC=dpc-8_x_usxgmii.dtb DPC=dpc-8_x_usxgmii.dtb
......
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