Commit 6c5a19de authored by Claes Sjofors's avatar Claes Sjofors

ABB ACS800: bit 1 and 4 in CW used for stop, previous only bit 1 was used

parent 6934ff89
#060227 cs - Changelog created.
060712 cs - ABB_ACS800_Slave: IORack bit was missing.
080318 cs - ACS800 frequency converter with PPO3 or PPO5 profibus protocol added.
090623 cs - ACS800_1: bit 1 and 4 in CW used to stop, previously only bit 1 was used.
\ No newline at end of file
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......@@ -1197,14 +1197,14 @@ Volume ABB $ClassVolume 0.0.250.2
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......@@ -1214,6 +1214,83 @@ Volume ABB $ClassVolume 0.0.250.2
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......@@ -4674,152 +4751,24 @@ Volume ABB $ClassVolume 0.0.250.2
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Attr source_point = 1
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......@@ -4838,13 +4787,13 @@ Volume ABB $ClassVolume 0.0.250.2
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......@@ -6013,7 +5962,7 @@ SW bit:
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......@@ -6021,7 +5970,7 @@ SW bit:
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Attr heigth = 5.000000e-02
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Attr mask[1] = 1
......@@ -6031,7 +5980,7 @@ SW bit:
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......@@ -6039,7 +5988,7 @@ SW bit:
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......@@ -6047,26 +5996,25 @@ SW bit:
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Body RtBody 23-JUN-2009 09:49:24.91
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Attr d3 = 1
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Attr mask[1] = 1
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......@@ -6109,24 +6057,6 @@ CW bit:
07 = od8 = Reset tripped converter"
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