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Esteban Blanc
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Commits
c437a13f
Commit
c437a13f
authored
Nov 17, 2009
by
Claes Sjofors
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ACS800Sim adapted to previous change in Fo code (CW)
parent
877b3b21
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+4536
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abb/changelog.txt
abb/changelog.txt
+2
-1
abb/wbl/mcomp/src/abb.wb_load
abb/wbl/mcomp/src/abb.wb_load
+417
-308
abb/wbl/mcomp/src/pwr_abb_acs800_1sim.flw
abb/wbl/mcomp/src/pwr_abb_acs800_1sim.flw
+4117
-3080
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abb/changelog.txt
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c437a13f
#060227 cs - Changelog created.
060712 cs - ABB_ACS800_Slave: IORack bit was missing.
080318 cs - ACS800 frequency converter with PPO3 or PPO5 profibus protocol added.
090623 cs - ACS800_1: bit 1 and 4 in CW used to stop, previously only bit 1 was used.
\ No newline at end of file
090623 cs - ACS800_1: bit 1 and 4 in CW used to stop, previously only bit 1 was used.
091111 cs - ACS800_1Sim adapted to changed CW function.
\ No newline at end of file
abb/wbl/mcomp/src/abb.wb_load
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c437a13f
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abb/wbl/mcomp/src/pwr_abb_acs800_1sim.flw
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c437a13f
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