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Commit 16b1fce9 authored by Keith Randall's avatar Keith Randall
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[dev.ssa] cmd/compile: add aux typing, flags to ops 

Add the aux type to opcodes.
Add rematerializeable as a flag.

Change-Id: I906e19281498f3ee51bb136299bf26e13a54b2ec
Reviewed-on: https://go-review.googlesource.com/19088
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: default avatarTodd Neal <todd@tneal.org>
parent c87a62f3
Hide whitespace changes
Inline Side-by-side
Showing with 696 additions and 487 deletions
src/cmd/compile/internal/gc/ssa.go
View file @ 16b1fce9
...@@ -4022,11 +4022,11 @@ func (s *genState) genValue(v *ssa.Value) { ...@@ -4022,11 +4022,11 @@ func (s *genState) genValue(v *ssa.Value) {
var i int64 var i int64
switch v.Op { switch v.Op {
case ssa.OpAMD64MOVBconst: case ssa.OpAMD64MOVBconst:
i = int64(int8(v.AuxInt)) i = int64(v.AuxInt8())
case ssa.OpAMD64MOVWconst: case ssa.OpAMD64MOVWconst:
i = int64(int16(v.AuxInt)) i = int64(v.AuxInt16())
case ssa.OpAMD64MOVLconst: case ssa.OpAMD64MOVLconst:
i = int64(int32(v.AuxInt)) i = int64(v.AuxInt32())
case ssa.OpAMD64MOVQconst: case ssa.OpAMD64MOVQconst:
i = v.AuxInt i = v.AuxInt
} }
...@@ -4116,7 +4116,7 @@ func (s *genState) genValue(v *ssa.Value) { ...@@ -4116,7 +4116,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64MOVQstoreconst, ssa.OpAMD64MOVLstoreconst, ssa.OpAMD64MOVWstoreconst, ssa.OpAMD64MOVBstoreconst: case ssa.OpAMD64MOVQstoreconst, ssa.OpAMD64MOVLstoreconst, ssa.OpAMD64MOVWstoreconst, ssa.OpAMD64MOVBstoreconst:
p := Prog(v.Op.Asm()) p := Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST p.From.Type = obj.TYPE_CONST
sc := ssa.ValAndOff(v.AuxInt) sc := v.AuxValAndOff()
i := sc.Val() i := sc.Val()
switch v.Op { switch v.Op {
case ssa.OpAMD64MOVBstoreconst: case ssa.OpAMD64MOVBstoreconst:
......
src/cmd/compile/internal/ssa/check.go
View file @ 16b1fce9
...@@ -148,9 +148,27 @@ func checkFunc(f *Func) { ...@@ -148,9 +148,27 @@ func checkFunc(f *Func) {
} }
for _, v := range b.Values { for _, v := range b.Values {
switch v.Aux.(type) {
case bool, float32, float64: // Check to make sure aux values make sense.
f.Fatalf("value %v has an Aux value of type %T, should be AuxInt", v.LongString(), v.Aux) canHaveAux := false
canHaveAuxInt := false
switch opcodeTable[v.Op].auxType {
case auxNone:
case auxBool, auxInt8, auxInt16, auxInt32, auxInt64, auxFloat:
canHaveAuxInt = true
case auxString, auxSym:
canHaveAux = true
case auxSymOff, auxSymValAndOff:
canHaveAuxInt = true
canHaveAux = true
default:
f.Fatalf("unknown aux type for %s", v.Op)
}
if !canHaveAux && v.Aux != nil {
f.Fatalf("value %v has an Aux value %v but shouldn't", v.LongString(), v.Aux)
}
if !canHaveAuxInt && v.AuxInt != 0 {
f.Fatalf("value %v has an AuxInt value %d but shouldn't", v.LongString(), v.AuxInt)
} }
for _, arg := range v.Args { for _, arg := range v.Args {
......
src/cmd/compile/internal/ssa/deadcode_test.go
View file @ 16b1fce9
...@@ -10,7 +10,7 @@ func TestDeadLoop(t *testing.T) { ...@@ -10,7 +10,7 @@ func TestDeadLoop(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem")), Exit("mem")),
...@@ -40,7 +40,7 @@ func TestDeadValue(t *testing.T) { ...@@ -40,7 +40,7 @@ func TestDeadValue(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("deadval", OpConst64, TypeInt64, 37, nil), Valu("deadval", OpConst64, TypeInt64, 37, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
...@@ -64,7 +64,7 @@ func TestNeverTaken(t *testing.T) { ...@@ -64,7 +64,7 @@ func TestNeverTaken(t *testing.T) {
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("cond", OpConstBool, TypeBool, 0, nil), Valu("cond", OpConstBool, TypeBool, 0, nil),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
If("cond", "then", "else")), If("cond", "then", "else")),
Bloc("then", Bloc("then",
Goto("exit")), Goto("exit")),
...@@ -98,7 +98,7 @@ func TestNestedDeadBlocks(t *testing.T) { ...@@ -98,7 +98,7 @@ func TestNestedDeadBlocks(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("cond", OpConstBool, TypeBool, 0, nil), Valu("cond", OpConstBool, TypeBool, 0, nil),
If("cond", "b2", "b4")), If("cond", "b2", "b4")),
Bloc("b2", Bloc("b2",
......
src/cmd/compile/internal/ssa/deadstore_test.go
View file @ 16b1fce9
...@@ -12,7 +12,7 @@ func TestDeadStore(t *testing.T) { ...@@ -12,7 +12,7 @@ func TestDeadStore(t *testing.T) {
ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr", Elem_: elemType} // dummy for testing ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr", Elem_: elemType} // dummy for testing
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"), Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil), Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, ptrType, 0, nil, "sb"), Valu("addr1", OpAddr, ptrType, 0, nil, "sb"),
...@@ -47,7 +47,7 @@ func TestDeadStorePhi(t *testing.T) { ...@@ -47,7 +47,7 @@ func TestDeadStorePhi(t *testing.T) {
ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"), Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil), Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr", OpAddr, ptrType, 0, nil, "sb"), Valu("addr", OpAddr, ptrType, 0, nil, "sb"),
...@@ -74,7 +74,7 @@ func TestDeadStoreTypes(t *testing.T) { ...@@ -74,7 +74,7 @@ func TestDeadStoreTypes(t *testing.T) {
t2 := &TypeImpl{Size_: 4, Ptr: true, Name: "t2"} t2 := &TypeImpl{Size_: 4, Ptr: true, Name: "t2"}
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"), Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil), Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, t1, 0, nil, "sb"), Valu("addr1", OpAddr, t1, 0, nil, "sb"),
......
src/cmd/compile/internal/ssa/dom_test.go
View file @ 16b1fce9
...@@ -20,7 +20,7 @@ func genLinear(size int) []bloc { ...@@ -20,7 +20,7 @@ func genLinear(size int) []bloc {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
) )
...@@ -43,7 +43,7 @@ func genFwdBack(size int) []bloc { ...@@ -43,7 +43,7 @@ func genFwdBack(size int) []bloc {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
...@@ -73,7 +73,7 @@ func genManyPred(size int) []bloc { ...@@ -73,7 +73,7 @@ func genManyPred(size int) []bloc {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
...@@ -111,7 +111,7 @@ func genMaxPred(size int) []bloc { ...@@ -111,7 +111,7 @@ func genMaxPred(size int) []bloc {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
...@@ -136,7 +136,7 @@ func genMaxPredValue(size int) []bloc { ...@@ -136,7 +136,7 @@ func genMaxPredValue(size int) []bloc {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
...@@ -223,7 +223,7 @@ func TestDominatorsSingleBlock(t *testing.T) { ...@@ -223,7 +223,7 @@ func TestDominatorsSingleBlock(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Exit("mem"))) Exit("mem")))
doms := map[string]string{} doms := map[string]string{}
...@@ -238,7 +238,7 @@ func TestDominatorsSimple(t *testing.T) { ...@@ -238,7 +238,7 @@ func TestDominatorsSimple(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("a")), Goto("a")),
Bloc("a", Bloc("a",
Goto("b")), Goto("b")),
...@@ -266,7 +266,7 @@ func TestDominatorsMultPredFwd(t *testing.T) { ...@@ -266,7 +266,7 @@ func TestDominatorsMultPredFwd(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")), If("p", "a", "c")),
Bloc("a", Bloc("a",
...@@ -294,7 +294,7 @@ func TestDominatorsDeadCode(t *testing.T) { ...@@ -294,7 +294,7 @@ func TestDominatorsDeadCode(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 0, nil), Valu("p", OpConstBool, TypeBool, 0, nil),
If("p", "b3", "b5")), If("p", "b3", "b5")),
Bloc("b2", Exit("mem")), Bloc("b2", Exit("mem")),
...@@ -319,7 +319,7 @@ func TestDominatorsMultPredRev(t *testing.T) { ...@@ -319,7 +319,7 @@ func TestDominatorsMultPredRev(t *testing.T) {
Bloc("entry", Bloc("entry",
Goto("first")), Goto("first")),
Bloc("first", Bloc("first",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto("a")), Goto("a")),
Bloc("a", Bloc("a",
...@@ -348,7 +348,7 @@ func TestDominatorsMultPred(t *testing.T) { ...@@ -348,7 +348,7 @@ func TestDominatorsMultPred(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")), If("p", "a", "c")),
Bloc("a", Bloc("a",
...@@ -376,7 +376,7 @@ func TestPostDominators(t *testing.T) { ...@@ -376,7 +376,7 @@ func TestPostDominators(t *testing.T) {
c := testConfig(t) c := testConfig(t)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")), If("p", "a", "c")),
Bloc("a", Bloc("a",
...@@ -403,7 +403,7 @@ func TestInfiniteLoop(t *testing.T) { ...@@ -403,7 +403,7 @@ func TestInfiniteLoop(t *testing.T) {
// note lack of an exit block // note lack of an exit block
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil), Valu("p", OpConstBool, TypeBool, 1, nil),
Goto("a")), Goto("a")),
Bloc("a", Bloc("a",
......
src/cmd/compile/internal/ssa/func_test.go
View file @ 16b1fce9
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
// As an example, the following func // As an example, the following func
// //
// b1: // b1:
// v1 = Arg <mem> [.mem] // v1 = InitMem <mem>
// Plain -> b2 // Plain -> b2
// b2: // b2:
// Exit v1 // Exit v1
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
// //
// fun := Fun("entry", // fun := Fun("entry",
// Bloc("entry", // Bloc("entry",
// Valu("mem", OpInitMem, TypeMem, 0, ".mem"), // Valu("mem", OpInitMem, TypeMem, 0, nil),
// Goto("exit")), // Goto("exit")),
// Bloc("exit", // Bloc("exit",
// Exit("mem")), // Exit("mem")),
...@@ -267,7 +267,7 @@ func TestArgs(t *testing.T) { ...@@ -267,7 +267,7 @@ func TestArgs(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem"))) Exit("mem")))
...@@ -289,7 +289,7 @@ func TestEquiv(t *testing.T) { ...@@ -289,7 +289,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem"))), Exit("mem"))),
...@@ -298,7 +298,7 @@ func TestEquiv(t *testing.T) { ...@@ -298,7 +298,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem"))), Exit("mem"))),
...@@ -310,7 +310,7 @@ func TestEquiv(t *testing.T) { ...@@ -310,7 +310,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem"))), Exit("mem"))),
...@@ -321,7 +321,7 @@ func TestEquiv(t *testing.T) { ...@@ -321,7 +321,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit"))), Goto("exit"))),
}, },
} }
...@@ -338,26 +338,26 @@ func TestEquiv(t *testing.T) { ...@@ -338,26 +338,26 @@ func TestEquiv(t *testing.T) {
{ {
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")), Goto("exit")),
Bloc("exit", Bloc("exit",
Exit("mem"))), Exit("mem"))),
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Exit("mem"))), Exit("mem"))),
}, },
// value order changed // value order changed
{ {
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Exit("mem"))), Exit("mem"))),
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Exit("mem"))), Exit("mem"))),
...@@ -366,12 +366,12 @@ func TestEquiv(t *testing.T) { ...@@ -366,12 +366,12 @@ func TestEquiv(t *testing.T) {
{ {
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Exit("mem"))), Exit("mem"))),
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 26, nil), Valu("a", OpConst64, TypeInt64, 26, nil),
Exit("mem"))), Exit("mem"))),
}, },
...@@ -379,12 +379,12 @@ func TestEquiv(t *testing.T) { ...@@ -379,12 +379,12 @@ func TestEquiv(t *testing.T) {
{ {
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, 14), Valu("a", OpConst64, TypeInt64, 0, 14),
Exit("mem"))), Exit("mem"))),
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, 26), Valu("a", OpConst64, TypeInt64, 0, 26),
Exit("mem"))), Exit("mem"))),
}, },
...@@ -392,14 +392,14 @@ func TestEquiv(t *testing.T) { ...@@ -392,14 +392,14 @@ func TestEquiv(t *testing.T) {
{ {
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil), Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil), Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Exit("mem"))), Exit("mem"))),
Fun(testConfig(t), "entry", Fun(testConfig(t), "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, nil), Valu("a", OpConst64, TypeInt64, 0, nil),
Valu("b", OpConst64, TypeInt64, 14, nil), Valu("b", OpConst64, TypeInt64, 14, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "b", "a"), Valu("sum", OpAdd64, TypeInt64, 0, nil, "b", "a"),
......
src/cmd/compile/internal/ssa/gen/AMD64Ops.go
View file @ 16b1fce9
...@@ -152,45 +152,45 @@ func init() { ...@@ -152,45 +152,45 @@ func init() {
{name: "DIVSS", reg: fp21x15, asm: "DIVSS"}, // fp32 div {name: "DIVSS", reg: fp21x15, asm: "DIVSS"}, // fp32 div
{name: "DIVSD", reg: fp21x15, asm: "DIVSD"}, // fp64 div {name: "DIVSD", reg: fp21x15, asm: "DIVSD"}, // fp64 div
{name: "MOVSSload", reg: fpload, asm: "MOVSS"}, // fp32 load {name: "MOVSSload", reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load
{name: "MOVSDload", reg: fpload, asm: "MOVSD"}, // fp64 load {name: "MOVSDload", reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load
{name: "MOVSSconst", reg: fp01, asm: "MOVSS"}, // fp32 constant {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float", rematerializeable: true}, // fp32 constant
{name: "MOVSDconst", reg: fp01, asm: "MOVSD"}, // fp64 constant {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float", rematerializeable: true}, // fp64 constant
{name: "MOVSSloadidx4", reg: fploadidx, asm: "MOVSS"}, // fp32 load {name: "MOVSSloadidx4", reg: fploadidx, asm: "MOVSS", aux: "SymOff"}, // fp32 load
{name: "MOVSDloadidx8", reg: fploadidx, asm: "MOVSD"}, // fp64 load {name: "MOVSDloadidx8", reg: fploadidx, asm: "MOVSD", aux: "SymOff"}, // fp64 load
{name: "MOVSSstore", reg: fpstore, asm: "MOVSS"}, // fp32 store {name: "MOVSSstore", reg: fpstore, asm: "MOVSS", aux: "SymOff"}, // fp32 store
{name: "MOVSDstore", reg: fpstore, asm: "MOVSD"}, // fp64 store {name: "MOVSDstore", reg: fpstore, asm: "MOVSD", aux: "SymOff"}, // fp64 store
{name: "MOVSSstoreidx4", reg: fpstoreidx, asm: "MOVSS"}, // fp32 indexed by 4i store {name: "MOVSSstoreidx4", reg: fpstoreidx, asm: "MOVSS", aux: "SymOff"}, // fp32 indexed by 4i store
{name: "MOVSDstoreidx8", reg: fpstoreidx, asm: "MOVSD"}, // fp64 indexed by 8i store {name: "MOVSDstoreidx8", reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store
// binary ops // binary ops
{name: "ADDQ", reg: gp21, asm: "ADDQ"}, // arg0 + arg1 {name: "ADDQ", reg: gp21, asm: "ADDQ"}, // arg0 + arg1
{name: "ADDL", reg: gp21, asm: "ADDL"}, // arg0 + arg1 {name: "ADDL", reg: gp21, asm: "ADDL"}, // arg0 + arg1
{name: "ADDW", reg: gp21, asm: "ADDW"}, // arg0 + arg1 {name: "ADDW", reg: gp21, asm: "ADDW"}, // arg0 + arg1
{name: "ADDB", reg: gp21, asm: "ADDB"}, // arg0 + arg1 {name: "ADDB", reg: gp21, asm: "ADDB"}, // arg0 + arg1
{name: "ADDQconst", reg: gp11, asm: "ADDQ", typ: "UInt64"}, // arg0 + auxint {name: "ADDQconst", reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
{name: "ADDLconst", reg: gp11, asm: "ADDL"}, // arg0 + auxint {name: "ADDLconst", reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
{name: "ADDWconst", reg: gp11, asm: "ADDW"}, // arg0 + auxint {name: "ADDWconst", reg: gp11, asm: "ADDW", aux: "Int16"}, // arg0 + auxint
{name: "ADDBconst", reg: gp11, asm: "ADDB"}, // arg0 + auxint {name: "ADDBconst", reg: gp11, asm: "ADDB", aux: "Int8"}, // arg0 + auxint
{name: "SUBQ", reg: gp21, asm: "SUBQ"}, // arg0 - arg1 {name: "SUBQ", reg: gp21, asm: "SUBQ"}, // arg0 - arg1
{name: "SUBL", reg: gp21, asm: "SUBL"}, // arg0 - arg1 {name: "SUBL", reg: gp21, asm: "SUBL"}, // arg0 - arg1
{name: "SUBW", reg: gp21, asm: "SUBW"}, // arg0 - arg1 {name: "SUBW", reg: gp21, asm: "SUBW"}, // arg0 - arg1
{name: "SUBB", reg: gp21, asm: "SUBB"}, // arg0 - arg1 {name: "SUBB", reg: gp21, asm: "SUBB"}, // arg0 - arg1
{name: "SUBQconst", reg: gp11, asm: "SUBQ"}, // arg0 - auxint {name: "SUBQconst", reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint
{name: "SUBLconst", reg: gp11, asm: "SUBL"}, // arg0 - auxint {name: "SUBLconst", reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint
{name: "SUBWconst", reg: gp11, asm: "SUBW"}, // arg0 - auxint {name: "SUBWconst", reg: gp11, asm: "SUBW", aux: "Int16"}, // arg0 - auxint
{name: "SUBBconst", reg: gp11, asm: "SUBB"}, // arg0 - auxint {name: "SUBBconst", reg: gp11, asm: "SUBB", aux: "Int8"}, // arg0 - auxint
{name: "MULQ", reg: gp21, asm: "IMULQ"}, // arg0 * arg1 {name: "MULQ", reg: gp21, asm: "IMULQ"}, // arg0 * arg1
{name: "MULL", reg: gp21, asm: "IMULL"}, // arg0 * arg1 {name: "MULL", reg: gp21, asm: "IMULL"}, // arg0 * arg1
{name: "MULW", reg: gp21, asm: "IMULW"}, // arg0 * arg1 {name: "MULW", reg: gp21, asm: "IMULW"}, // arg0 * arg1
{name: "MULB", reg: gp21, asm: "IMULW"}, // arg0 * arg1 {name: "MULB", reg: gp21, asm: "IMULW"}, // arg0 * arg1
{name: "MULQconst", reg: gp11, asm: "IMULQ"}, // arg0 * auxint {name: "MULQconst", reg: gp11, asm: "IMULQ", aux: "Int64"}, // arg0 * auxint
{name: "MULLconst", reg: gp11, asm: "IMULL"}, // arg0 * auxint {name: "MULLconst", reg: gp11, asm: "IMULL", aux: "Int32"}, // arg0 * auxint
{name: "MULWconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint {name: "MULWconst", reg: gp11, asm: "IMULW", aux: "Int16"}, // arg0 * auxint
{name: "MULBconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint {name: "MULBconst", reg: gp11, asm: "IMULW", aux: "Int8"}, // arg0 * auxint
{name: "HMULL", reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width {name: "HMULL", reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
{name: "HMULW", reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width {name: "HMULW", reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
...@@ -213,86 +213,86 @@ func init() { ...@@ -213,86 +213,86 @@ func init() {
{name: "MODLU", reg: gp11mod, asm: "DIVL"}, // arg0 % arg1 {name: "MODLU", reg: gp11mod, asm: "DIVL"}, // arg0 % arg1
{name: "MODWU", reg: gp11mod, asm: "DIVW"}, // arg0 % arg1 {name: "MODWU", reg: gp11mod, asm: "DIVW"}, // arg0 % arg1
{name: "ANDQ", reg: gp21, asm: "ANDQ"}, // arg0 & arg1 {name: "ANDQ", reg: gp21, asm: "ANDQ"}, // arg0 & arg1
{name: "ANDL", reg: gp21, asm: "ANDL"}, // arg0 & arg1 {name: "ANDL", reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDW", reg: gp21, asm: "ANDW"}, // arg0 & arg1 {name: "ANDW", reg: gp21, asm: "ANDW"}, // arg0 & arg1
{name: "ANDB", reg: gp21, asm: "ANDB"}, // arg0 & arg1 {name: "ANDB", reg: gp21, asm: "ANDB"}, // arg0 & arg1
{name: "ANDQconst", reg: gp11, asm: "ANDQ"}, // arg0 & auxint {name: "ANDQconst", reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint
{name: "ANDLconst", reg: gp11, asm: "ANDL"}, // arg0 & auxint {name: "ANDLconst", reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint
{name: "ANDWconst", reg: gp11, asm: "ANDW"}, // arg0 & auxint {name: "ANDWconst", reg: gp11, asm: "ANDW", aux: "Int16"}, // arg0 & auxint
{name: "ANDBconst", reg: gp11, asm: "ANDB"}, // arg0 & auxint {name: "ANDBconst", reg: gp11, asm: "ANDB", aux: "Int8"}, // arg0 & auxint
{name: "ORQ", reg: gp21, asm: "ORQ"}, // arg0 | arg1 {name: "ORQ", reg: gp21, asm: "ORQ"}, // arg0 | arg1
{name: "ORL", reg: gp21, asm: "ORL"}, // arg0 | arg1 {name: "ORL", reg: gp21, asm: "ORL"}, // arg0 | arg1
{name: "ORW", reg: gp21, asm: "ORW"}, // arg0 | arg1 {name: "ORW", reg: gp21, asm: "ORW"}, // arg0 | arg1
{name: "ORB", reg: gp21, asm: "ORB"}, // arg0 | arg1 {name: "ORB", reg: gp21, asm: "ORB"}, // arg0 | arg1
{name: "ORQconst", reg: gp11, asm: "ORQ"}, // arg0 | auxint {name: "ORQconst", reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint
{name: "ORLconst", reg: gp11, asm: "ORL"}, // arg0 | auxint {name: "ORLconst", reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint
{name: "ORWconst", reg: gp11, asm: "ORW"}, // arg0 | auxint {name: "ORWconst", reg: gp11, asm: "ORW", aux: "Int16"}, // arg0 | auxint
{name: "ORBconst", reg: gp11, asm: "ORB"}, // arg0 | auxint {name: "ORBconst", reg: gp11, asm: "ORB", aux: "Int8"}, // arg0 | auxint
{name: "XORQ", reg: gp21, asm: "XORQ"}, // arg0 ^ arg1 {name: "XORQ", reg: gp21, asm: "XORQ"}, // arg0 ^ arg1
{name: "XORL", reg: gp21, asm: "XORL"}, // arg0 ^ arg1 {name: "XORL", reg: gp21, asm: "XORL"}, // arg0 ^ arg1
{name: "XORW", reg: gp21, asm: "XORW"}, // arg0 ^ arg1 {name: "XORW", reg: gp21, asm: "XORW"}, // arg0 ^ arg1
{name: "XORB", reg: gp21, asm: "XORB"}, // arg0 ^ arg1 {name: "XORB", reg: gp21, asm: "XORB"}, // arg0 ^ arg1
{name: "XORQconst", reg: gp11, asm: "XORQ"}, // arg0 ^ auxint {name: "XORQconst", reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint
{name: "XORLconst", reg: gp11, asm: "XORL"}, // arg0 ^ auxint {name: "XORLconst", reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint
{name: "XORWconst", reg: gp11, asm: "XORW"}, // arg0 ^ auxint {name: "XORWconst", reg: gp11, asm: "XORW", aux: "Int16"}, // arg0 ^ auxint
{name: "XORBconst", reg: gp11, asm: "XORB"}, // arg0 ^ auxint {name: "XORBconst", reg: gp11, asm: "XORB", aux: "Int8"}, // arg0 ^ auxint
{name: "CMPQ", reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPQ", reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPL", reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPL", reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPW", reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPW", reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPB", reg: gp2flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPB", reg: gp2flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPQconst", reg: gp1flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to auxint {name: "CMPQconst", reg: gp1flags, asm: "CMPQ", typ: "Flags", aux: "Int64"}, // arg0 compare to auxint
{name: "CMPLconst", reg: gp1flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to auxint {name: "CMPLconst", reg: gp1flags, asm: "CMPL", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint
{name: "CMPWconst", reg: gp1flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to auxint {name: "CMPWconst", reg: gp1flags, asm: "CMPW", typ: "Flags", aux: "Int16"}, // arg0 compare to auxint
{name: "CMPBconst", reg: gp1flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to auxint {name: "CMPBconst", reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint
{name: "UCOMISS", reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32 {name: "UCOMISS", reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32
{name: "UCOMISD", reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64 {name: "UCOMISD", reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64
{name: "TESTQ", reg: gp2flags, asm: "TESTQ", typ: "Flags"}, // (arg0 & arg1) compare to 0 {name: "TESTQ", reg: gp2flags, asm: "TESTQ", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTL", reg: gp2flags, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0 {name: "TESTL", reg: gp2flags, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTW", reg: gp2flags, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0 {name: "TESTW", reg: gp2flags, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTB", reg: gp2flags, asm: "TESTB", typ: "Flags"}, // (arg0 & arg1) compare to 0 {name: "TESTB", reg: gp2flags, asm: "TESTB", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTQconst", reg: gp1flags, asm: "TESTQ", typ: "Flags"}, // (arg0 & auxint) compare to 0 {name: "TESTQconst", reg: gp1flags, asm: "TESTQ", typ: "Flags", aux: "Int64"}, // (arg0 & auxint) compare to 0
{name: "TESTLconst", reg: gp1flags, asm: "TESTL", typ: "Flags"}, // (arg0 & auxint) compare to 0 {name: "TESTLconst", reg: gp1flags, asm: "TESTL", typ: "Flags", aux: "Int32"}, // (arg0 & auxint) compare to 0
{name: "TESTWconst", reg: gp1flags, asm: "TESTW", typ: "Flags"}, // (arg0 & auxint) compare to 0 {name: "TESTWconst", reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0
{name: "TESTBconst", reg: gp1flags, asm: "TESTB", typ: "Flags"}, // (arg0 & auxint) compare to 0 {name: "TESTBconst", reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0
{name: "SHLQ", reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64 {name: "SHLQ", reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64
{name: "SHLL", reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLL", reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLW", reg: gp21shift, asm: "SHLW"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLW", reg: gp21shift, asm: "SHLW"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLB", reg: gp21shift, asm: "SHLB"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLB", reg: gp21shift, asm: "SHLB"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLQconst", reg: gp11, asm: "SHLQ"}, // arg0 << auxint, shift amount 0-63 {name: "SHLQconst", reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
{name: "SHLLconst", reg: gp11, asm: "SHLL"}, // arg0 << auxint, shift amount 0-31 {name: "SHLLconst", reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31
{name: "SHLWconst", reg: gp11, asm: "SHLW"}, // arg0 << auxint, shift amount 0-31 {name: "SHLWconst", reg: gp11, asm: "SHLW", aux: "Int16"}, // arg0 << auxint, shift amount 0-31
{name: "SHLBconst", reg: gp11, asm: "SHLB"}, // arg0 << auxint, shift amount 0-31 {name: "SHLBconst", reg: gp11, asm: "SHLB", aux: "Int8"}, // arg0 << auxint, shift amount 0-31
// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount! // Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
{name: "SHRQ", reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64 {name: "SHRQ", reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64
{name: "SHRL", reg: gp21shift, asm: "SHRL"}, // unsigned arg0 >> arg1, shift amount is mod 32 {name: "SHRL", reg: gp21shift, asm: "SHRL"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRW", reg: gp21shift, asm: "SHRW"}, // unsigned arg0 >> arg1, shift amount is mod 32 {name: "SHRW", reg: gp21shift, asm: "SHRW"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRB", reg: gp21shift, asm: "SHRB"}, // unsigned arg0 >> arg1, shift amount is mod 32 {name: "SHRB", reg: gp21shift, asm: "SHRB"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRQconst", reg: gp11, asm: "SHRQ"}, // unsigned arg0 >> auxint, shift amount 0-63 {name: "SHRQconst", reg: gp11, asm: "SHRQ", aux: "Int64"}, // unsigned arg0 >> auxint, shift amount 0-63
{name: "SHRLconst", reg: gp11, asm: "SHRL"}, // unsigned arg0 >> auxint, shift amount 0-31 {name: "SHRLconst", reg: gp11, asm: "SHRL", aux: "Int32"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRWconst", reg: gp11, asm: "SHRW"}, // unsigned arg0 >> auxint, shift amount 0-31 {name: "SHRWconst", reg: gp11, asm: "SHRW", aux: "Int16"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRBconst", reg: gp11, asm: "SHRB"}, // unsigned arg0 >> auxint, shift amount 0-31 {name: "SHRBconst", reg: gp11, asm: "SHRB", aux: "Int8"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SARQ", reg: gp21shift, asm: "SARQ"}, // signed arg0 >> arg1, shift amount is mod 64 {name: "SARQ", reg: gp21shift, asm: "SARQ"}, // signed arg0 >> arg1, shift amount is mod 64
{name: "SARL", reg: gp21shift, asm: "SARL"}, // signed arg0 >> arg1, shift amount is mod 32 {name: "SARL", reg: gp21shift, asm: "SARL"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARW", reg: gp21shift, asm: "SARW"}, // signed arg0 >> arg1, shift amount is mod 32 {name: "SARW", reg: gp21shift, asm: "SARW"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARB", reg: gp21shift, asm: "SARB"}, // signed arg0 >> arg1, shift amount is mod 32 {name: "SARB", reg: gp21shift, asm: "SARB"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARQconst", reg: gp11, asm: "SARQ"}, // signed arg0 >> auxint, shift amount 0-63 {name: "SARQconst", reg: gp11, asm: "SARQ", aux: "Int64"}, // signed arg0 >> auxint, shift amount 0-63
{name: "SARLconst", reg: gp11, asm: "SARL"}, // signed arg0 >> auxint, shift amount 0-31 {name: "SARLconst", reg: gp11, asm: "SARL", aux: "Int32"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARWconst", reg: gp11, asm: "SARW"}, // signed arg0 >> auxint, shift amount 0-31 {name: "SARWconst", reg: gp11, asm: "SARW", aux: "Int16"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARBconst", reg: gp11, asm: "SARB"}, // signed arg0 >> auxint, shift amount 0-31 {name: "SARBconst", reg: gp11, asm: "SARB", aux: "Int8"}, // signed arg0 >> auxint, shift amount 0-31
{name: "ROLQconst", reg: gp11, asm: "ROLQ"}, // arg0 rotate left auxint, rotate amount 0-63 {name: "ROLQconst", reg: gp11, asm: "ROLQ", aux: "Int64"}, // arg0 rotate left auxint, rotate amount 0-63
{name: "ROLLconst", reg: gp11, asm: "ROLL"}, // arg0 rotate left auxint, rotate amount 0-31 {name: "ROLLconst", reg: gp11, asm: "ROLL", aux: "Int32"}, // arg0 rotate left auxint, rotate amount 0-31
{name: "ROLWconst", reg: gp11, asm: "ROLW"}, // arg0 rotate left auxint, rotate amount 0-15 {name: "ROLWconst", reg: gp11, asm: "ROLW", aux: "Int16"}, // arg0 rotate left auxint, rotate amount 0-15
{name: "ROLBconst", reg: gp11, asm: "ROLB"}, // arg0 rotate left auxint, rotate amount 0-7 {name: "ROLBconst", reg: gp11, asm: "ROLB", aux: "Int8"}, // arg0 rotate left auxint, rotate amount 0-7
// unary ops // unary ops
{name: "NEGQ", reg: gp11, asm: "NEGQ"}, // -arg0 {name: "NEGQ", reg: gp11, asm: "NEGQ"}, // -arg0
...@@ -339,10 +339,10 @@ func init() { ...@@ -339,10 +339,10 @@ func init() {
{name: "MOVLQSX", reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64 {name: "MOVLQSX", reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
{name: "MOVLQZX", reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64 {name: "MOVLQZX", reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
{name: "MOVBconst", reg: gp01, asm: "MOVB", typ: "UInt8"}, // 8 low bits of auxint {name: "MOVBconst", reg: gp01, asm: "MOVB", typ: "UInt8", aux: "Int8", rematerializeable: true}, // 8 low bits of auxint
{name: "MOVWconst", reg: gp01, asm: "MOVW", typ: "UInt16"}, // 16 low bits of auxint {name: "MOVWconst", reg: gp01, asm: "MOVW", typ: "UInt16", aux: "Int16", rematerializeable: true}, // 16 low bits of auxint
{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32"}, // 32 low bits of auxint {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint
{name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64"}, // auxint {name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint
{name: "CVTTSD2SL", reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32 {name: "CVTTSD2SL", reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32
{name: "CVTTSD2SQ", reg: fpgp, asm: "CVTTSD2SQ"}, // convert float64 to int64 {name: "CVTTSD2SQ", reg: fpgp, asm: "CVTTSD2SQ"}, // convert float64 to int64
...@@ -357,44 +357,44 @@ func init() { ...@@ -357,44 +357,44 @@ func init() {
{name: "PXOR", reg: fp21, asm: "PXOR"}, // exclusive or, applied to X regs for float negation. {name: "PXOR", reg: fp21, asm: "PXOR"}, // exclusive or, applied to X regs for float negation.
{name: "LEAQ", reg: gp11sb}, // arg0 + auxint + offset encoded in aux {name: "LEAQ", reg: gp11sb, aux: "SymOff", rematerializeable: true}, // arg0 + auxint + offset encoded in aux
{name: "LEAQ1", reg: gp21sb}, // arg0 + arg1 + auxint {name: "LEAQ1", reg: gp21sb, aux: "SymOff"}, // arg0 + arg1 + auxint + aux
{name: "LEAQ2", reg: gp21sb}, // arg0 + 2*arg1 + auxint {name: "LEAQ2", reg: gp21sb, aux: "SymOff"}, // arg0 + 2*arg1 + auxint + aux
{name: "LEAQ4", reg: gp21sb}, // arg0 + 4*arg1 + auxint {name: "LEAQ4", reg: gp21sb, aux: "SymOff"}, // arg0 + 4*arg1 + auxint + aux
{name: "LEAQ8", reg: gp21sb}, // arg0 + 8*arg1 + auxint {name: "LEAQ8", reg: gp21sb, aux: "SymOff"}, // arg0 + 8*arg1 + auxint + aux
// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
{name: "MOVBload", reg: gpload, asm: "MOVB", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem {name: "MOVBload", reg: gpload, asm: "MOVB", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
{name: "MOVBQSXload", reg: gpload, asm: "MOVBQSX"}, // ditto, extend to int64 {name: "MOVBQSXload", reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVBQZXload", reg: gpload, asm: "MOVBQZX"}, // ditto, extend to uint64 {name: "MOVBQZXload", reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVWload", reg: gpload, asm: "MOVW", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem {name: "MOVWload", reg: gpload, asm: "MOVW", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVWQSXload", reg: gpload, asm: "MOVWQSX"}, // ditto, extend to int64 {name: "MOVWQSXload", reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVWQZXload", reg: gpload, asm: "MOVWQZX"}, // ditto, extend to uint64 {name: "MOVWQZXload", reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVLload", reg: gpload, asm: "MOVL", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem {name: "MOVLload", reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVLQSXload", reg: gpload, asm: "MOVLQSX"}, // ditto, extend to int64 {name: "MOVLQSXload", reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVLQZXload", reg: gpload, asm: "MOVLQZX"}, // ditto, extend to uint64 {name: "MOVLQZXload", reg: gpload, asm: "MOVLQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVQload", reg: gpload, asm: "MOVQ", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem {name: "MOVQload", reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVQloadidx8", reg: gploadidx, asm: "MOVQ"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem {name: "MOVQloadidx8", reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
{name: "MOVBstore", reg: gpstore, asm: "MOVB", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVBstore", reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVWstore", reg: gpstore, asm: "MOVW", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVWstore", reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVLstore", reg: gpstore, asm: "MOVL", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVLstore", reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVQstore", reg: gpstore, asm: "MOVQ", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVQstore", reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVBstoreidx1", reg: gpstoreidx, asm: "MOVB"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem {name: "MOVBstoreidx1", reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
{name: "MOVWstoreidx2", reg: gpstoreidx, asm: "MOVW"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem {name: "MOVWstoreidx2", reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
{name: "MOVLstoreidx4", reg: gpstoreidx, asm: "MOVL"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem {name: "MOVLstoreidx4", reg: gpstoreidx, asm: "MOVL", aux: "SymOff"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
{name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem {name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ", aux: "SymOff"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
{name: "MOVOload", reg: fpload, asm: "MOVUPS", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem {name: "MOVOload", reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVOstore", reg: fpstore, asm: "MOVUPS", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVOstore", reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
// For storeconst ops, the AuxInt field encodes both // For storeconst ops, the AuxInt field encodes both
// the value to store and an address offset of the store. // the value to store and an address offset of the store.
// Cast AuxInt to a ValAndOff to extract Val and Off fields. // Cast AuxInt to a ValAndOff to extract Val and Off fields.
{name: "MOVBstoreconst", reg: gpstoreconst, asm: "MOVB", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem {name: "MOVBstoreconst", reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem
{name: "MOVWstoreconst", reg: gpstoreconst, asm: "MOVW", typ: "Mem"}, // store low 2 bytes of ... {name: "MOVWstoreconst", reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ...
{name: "MOVLstoreconst", reg: gpstoreconst, asm: "MOVL", typ: "Mem"}, // store low 4 bytes of ... {name: "MOVLstoreconst", reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ...
{name: "MOVQstoreconst", reg: gpstoreconst, asm: "MOVQ", typ: "Mem"}, // store 8 bytes of ... {name: "MOVQstoreconst", reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ...
// arg0 = (duff-adjusted) pointer to start of memory to zero // arg0 = (duff-adjusted) pointer to start of memory to zero
// arg1 = value to store (will always be zero) // arg1 = value to store (will always be zero)
...@@ -403,12 +403,13 @@ func init() { ...@@ -403,12 +403,13 @@ func init() {
// returns mem // returns mem
{ {
name: "DUFFZERO", name: "DUFFZERO",
aux: "Int64",
reg: regInfo{ reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("X0")}, inputs: []regMask{buildReg("DI"), buildReg("X0")},
clobbers: buildReg("DI FLAGS"), clobbers: buildReg("DI FLAGS"),
}, },
}, },
{name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128"}, {name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128", rematerializeable: true},
// arg0 = address of memory to zero // arg0 = address of memory to zero
// arg1 = # of 8-byte words to zero // arg1 = # of 8-byte words to zero
...@@ -423,11 +424,11 @@ func init() { ...@@ -423,11 +424,11 @@ func init() {
}, },
}, },
{name: "CALLstatic", reg: regInfo{clobbers: callerSave}}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem {name: "CALLstatic", reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
{name: "CALLclosure", reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem {name: "CALLclosure", reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
{name: "CALLdefer", reg: regInfo{clobbers: callerSave}}, // call deferproc. arg0=mem, auxint=argsize, returns mem {name: "CALLdefer", reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLgo", reg: regInfo{clobbers: callerSave}}, // call newproc. arg0=mem, auxint=argsize, returns mem {name: "CALLgo", reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLinter", reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem {name: "CALLinter", reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// arg0 = destination pointer // arg0 = destination pointer
// arg1 = source pointer // arg1 = source pointer
...@@ -436,6 +437,7 @@ func init() { ...@@ -436,6 +437,7 @@ func init() {
// returns memory // returns memory
{ {
name: "DUFFCOPY", name: "DUFFCOPY",
aux: "Int64",
reg: regInfo{ reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("SI")}, inputs: []regMask{buildReg("DI"), buildReg("SI")},
clobbers: buildReg("DI SI X0 FLAGS"), // uses X0 as a temporary clobbers: buildReg("DI SI X0 FLAGS"), // uses X0 as a temporary
......
src/cmd/compile/internal/ssa/gen/genericOps.go
View file @ 16b1fce9
...@@ -148,10 +148,10 @@ var genericOps = []opData{ ...@@ -148,10 +148,10 @@ var genericOps = []opData{
// for rotates is hashing and crypto code with constant // for rotates is hashing and crypto code with constant
// distance, rotate instructions are only substituted // distance, rotate instructions are only substituted
// when arg1 is a constant between 1 and A-1, inclusive. // when arg1 is a constant between 1 and A-1, inclusive.
{name: "Lrot8"}, {name: "Lrot8", aux: "Int64"},
{name: "Lrot16"}, {name: "Lrot16", aux: "Int64"},
{name: "Lrot32"}, {name: "Lrot32", aux: "Int64"},
{name: "Lrot64"}, {name: "Lrot64", aux: "Int64"},
// 2-input comparisons // 2-input comparisons
{name: "Eq8"}, // arg0 == arg1 {name: "Eq8"}, // arg0 == arg1
...@@ -247,46 +247,46 @@ var genericOps = []opData{ ...@@ -247,46 +247,46 @@ var genericOps = []opData{
// constants. Constant values are stored in the aux or // constants. Constant values are stored in the aux or
// auxint fields. // auxint fields.
{name: "ConstBool"}, // auxint is 0 for false and 1 for true {name: "ConstBool", aux: "Bool"}, // auxint is 0 for false and 1 for true
{name: "ConstString"}, // value is aux.(string) {name: "ConstString", aux: "String"}, // value is aux.(string)
{name: "ConstNil", typ: "BytePtr"}, // nil pointer {name: "ConstNil", typ: "BytePtr"}, // nil pointer
{name: "Const8"}, // value is low 8 bits of auxint {name: "Const8", aux: "Int8"}, // value is low 8 bits of auxint
{name: "Const16"}, // value is low 16 bits of auxint {name: "Const16", aux: "Int16"}, // value is low 16 bits of auxint
{name: "Const32"}, // value is low 32 bits of auxint {name: "Const32", aux: "Int32"}, // value is low 32 bits of auxint
{name: "Const64"}, // value is auxint {name: "Const64", aux: "Int64"}, // value is auxint
{name: "Const32F"}, // value is math.Float64frombits(uint64(auxint)) {name: "Const32F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint))
{name: "Const64F"}, // value is math.Float64frombits(uint64(auxint)) {name: "Const64F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint))
{name: "ConstInterface"}, // nil interface {name: "ConstInterface"}, // nil interface
{name: "ConstSlice"}, // nil slice {name: "ConstSlice"}, // nil slice
// Constant-like things // Constant-like things
{name: "InitMem"}, // memory input to the function. {name: "InitMem"}, // memory input to the function.
{name: "Arg"}, // argument to the function. aux=GCNode of arg, off = offset in that arg. {name: "Arg", aux: "SymOff"}, // argument to the function. aux=GCNode of arg, off = offset in that arg.
// The address of a variable. arg0 is the base pointer (SB or SP, depending // The address of a variable. arg0 is the base pointer (SB or SP, depending
// on whether it is a global or stack variable). The Aux field identifies the // on whether it is a global or stack variable). The Aux field identifies the
// variable. It will be either an *ExternSymbol (with arg0=SB), *ArgSymbol (arg0=SP), // variable. It will be either an *ExternSymbol (with arg0=SB), *ArgSymbol (arg0=SP),
// or *AutoSymbol (arg0=SP). // or *AutoSymbol (arg0=SP).
{name: "Addr"}, // Address of a variable. Arg0=SP or SB. Aux identifies the variable. {name: "Addr", aux: "Sym"}, // Address of a variable. Arg0=SP or SB. Aux identifies the variable.
{name: "SP"}, // stack pointer {name: "SP"}, // stack pointer
{name: "SB", typ: "Uintptr"}, // static base pointer (a.k.a. globals pointer) {name: "SB", typ: "Uintptr"}, // static base pointer (a.k.a. globals pointer)
{name: "Func"}, // entry address of a function {name: "Func", aux: "Sym"}, // entry address of a function
// Memory operations // Memory operations
{name: "Load"}, // Load from arg0. arg1=memory {name: "Load"}, // Load from arg0. arg1=memory
{name: "Store", typ: "Mem"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory. {name: "Store", typ: "Mem", aux: "Int64"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory.
{name: "Move"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory. {name: "Move", aux: "Int64"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory.
{name: "Zero"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory. {name: "Zero", aux: "Int64"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory.
// Function calls. Arguments to the call have already been written to the stack. // Function calls. Arguments to the call have already been written to the stack.
// Return values appear on the stack. The method receiver, if any, is treated // Return values appear on the stack. The method receiver, if any, is treated
// as a phantom first argument. // as a phantom first argument.
{name: "ClosureCall"}, // arg0=code pointer, arg1=context ptr, arg2=memory. auxint=arg size. Returns memory. {name: "ClosureCall", aux: "Int64"}, // arg0=code pointer, arg1=context ptr, arg2=memory. auxint=arg size. Returns memory.
{name: "StaticCall"}, // call function aux.(*gc.Sym), arg0=memory. auxint=arg size. Returns memory. {name: "StaticCall", aux: "SymOff"}, // call function aux.(*gc.Sym), arg0=memory. auxint=arg size. Returns memory.
{name: "DeferCall"}, // defer call. arg0=memory, auxint=arg size. Returns memory. {name: "DeferCall", aux: "Int64"}, // defer call. arg0=memory, auxint=arg size. Returns memory.
{name: "GoCall"}, // go call. arg0=memory, auxint=arg size. Returns memory. {name: "GoCall", aux: "Int64"}, // go call. arg0=memory, auxint=arg size. Returns memory.
{name: "InterCall"}, // interface call. arg0=code pointer, arg1=memory, auxint=arg size. Returns memory. {name: "InterCall", aux: "Int64"}, // interface call. arg0=code pointer, arg1=memory, auxint=arg size. Returns memory.
// Conversions: signed extensions, zero (unsigned) extensions, truncations // Conversions: signed extensions, zero (unsigned) extensions, truncations
{name: "SignExt8to16", typ: "Int16"}, {name: "SignExt8to16", typ: "Int16"},
...@@ -330,9 +330,9 @@ var genericOps = []opData{ ...@@ -330,9 +330,9 @@ var genericOps = []opData{
{name: "GetClosurePtr"}, // get closure pointer from dedicated register {name: "GetClosurePtr"}, // get closure pointer from dedicated register
// Indexing operations // Indexing operations
{name: "ArrayIndex"}, // arg0=array, arg1=index. Returns a[i] {name: "ArrayIndex"}, // arg0=array, arg1=index. Returns a[i]
{name: "PtrIndex"}, // arg0=ptr, arg1=index. Computes ptr+sizeof(*v.type)*index, where index is extended to ptrwidth type {name: "PtrIndex"}, // arg0=ptr, arg1=index. Computes ptr+sizeof(*v.type)*index, where index is extended to ptrwidth type
{name: "OffPtr"}, // arg0 + auxint (arg0 and result are pointers) {name: "OffPtr", aux: "Int64"}, // arg0 + auxint (arg0 and result are pointers)
// Slices // Slices
{name: "SliceMake"}, // arg0=ptr, arg1=len, arg2=cap {name: "SliceMake"}, // arg0=ptr, arg1=len, arg2=cap
...@@ -356,12 +356,12 @@ var genericOps = []opData{ ...@@ -356,12 +356,12 @@ var genericOps = []opData{
{name: "IData"}, // arg0=interface, returns data field {name: "IData"}, // arg0=interface, returns data field
// Structs // Structs
{name: "StructMake0"}, // Returns struct with 0 fields. {name: "StructMake0"}, // Returns struct with 0 fields.
{name: "StructMake1"}, // arg0=field0. Returns struct. {name: "StructMake1"}, // arg0=field0. Returns struct.
{name: "StructMake2"}, // arg0,arg1=field0,field1. Returns struct. {name: "StructMake2"}, // arg0,arg1=field0,field1. Returns struct.
{name: "StructMake3"}, // arg0..2=field0..2. Returns struct. {name: "StructMake3"}, // arg0..2=field0..2. Returns struct.
{name: "StructMake4"}, // arg0..3=field0..3. Returns struct. {name: "StructMake4"}, // arg0..3=field0..3. Returns struct.
{name: "StructSelect"}, // arg0=struct, auxint=field index. Returns the auxint'th field. {name: "StructSelect", aux: "Int64"}, // arg0=struct, auxint=field index. Returns the auxint'th field.
// Spill&restore ops for the register allocator. These are // Spill&restore ops for the register allocator. These are
// semantically identical to OpCopy; they do not take/return // semantically identical to OpCopy; they do not take/return
...@@ -376,9 +376,9 @@ var genericOps = []opData{ ...@@ -376,9 +376,9 @@ var genericOps = []opData{
// Unknown value. Used for Values whose values don't matter because they are dead code. // Unknown value. Used for Values whose values don't matter because they are dead code.
{name: "Unknown"}, {name: "Unknown"},
{name: "VarDef", typ: "Mem"}, // aux is a *gc.Node of a variable that is about to be initialized. arg0=mem, returns mem {name: "VarDef", aux: "Sym", typ: "Mem"}, // aux is a *gc.Node of a variable that is about to be initialized. arg0=mem, returns mem
{name: "VarKill"}, // aux is a *gc.Node of a variable that is known to be dead. arg0=mem, returns mem {name: "VarKill", aux: "Sym"}, // aux is a *gc.Node of a variable that is known to be dead. arg0=mem, returns mem
{name: "VarLive"}, // aux is a *gc.Node of a variable that must be kept live. arg0=mem, returns mem {name: "VarLive", aux: "Sym"}, // aux is a *gc.Node of a variable that must be kept live. arg0=mem, returns mem
} }
// kind control successors implicit exit // kind control successors implicit exit
......
src/cmd/compile/internal/ssa/gen/main.go
View file @ 16b1fce9
...@@ -26,10 +26,12 @@ type arch struct { ...@@ -26,10 +26,12 @@ type arch struct {
} }
type opData struct { type opData struct {
name string name string
reg regInfo reg regInfo
asm string asm string
typ string // default result type typ string // default result type
aux string
rematerializeable bool
} }
type blockData struct { type blockData struct {
...@@ -117,6 +119,17 @@ func genOp() { ...@@ -117,6 +119,17 @@ func genOp() {
for _, v := range a.ops { for _, v := range a.ops {
fmt.Fprintln(w, "{") fmt.Fprintln(w, "{")
fmt.Fprintf(w, "name:\"%s\",\n", v.name) fmt.Fprintf(w, "name:\"%s\",\n", v.name)
// flags
if v.aux != "" {
fmt.Fprintf(w, "auxType: aux%s,\n", v.aux)
}
if v.rematerializeable {
if v.reg.clobbers != 0 {
log.Fatalf("%s is rematerializeable and clobbers registers", v.name)
}
fmt.Fprintln(w, "rematerializeable: true,")
}
if a.name == "generic" { if a.name == "generic" {
fmt.Fprintln(w, "generic:true,") fmt.Fprintln(w, "generic:true,")
fmt.Fprintln(w, "},") // close op fmt.Fprintln(w, "},") // close op
......
src/cmd/compile/internal/ssa/nilcheck_test.go
View file @ 16b1fce9
...@@ -21,7 +21,7 @@ func benchmarkNilCheckDeep(b *testing.B, depth int) { ...@@ -21,7 +21,7 @@ func benchmarkNilCheckDeep(b *testing.B, depth int) {
var blocs []bloc var blocs []bloc
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto(blockn(0)), Goto(blockn(0)),
), ),
...@@ -67,7 +67,7 @@ func TestNilcheckSimple(t *testing.T) { ...@@ -67,7 +67,7 @@ func TestNilcheckSimple(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -104,7 +104,7 @@ func TestNilcheckDomOrder(t *testing.T) { ...@@ -104,7 +104,7 @@ func TestNilcheckDomOrder(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -140,7 +140,7 @@ func TestNilcheckAddr(t *testing.T) { ...@@ -140,7 +140,7 @@ func TestNilcheckAddr(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -173,7 +173,7 @@ func TestNilcheckAddPtr(t *testing.T) { ...@@ -173,7 +173,7 @@ func TestNilcheckAddPtr(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -207,7 +207,7 @@ func TestNilcheckPhi(t *testing.T) { ...@@ -207,7 +207,7 @@ func TestNilcheckPhi(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("sp", OpSP, TypeInvalid, 0, nil), Valu("sp", OpSP, TypeInvalid, 0, nil),
Valu("baddr", OpAddr, TypeBool, 0, "b", "sp"), Valu("baddr", OpAddr, TypeBool, 0, "b", "sp"),
...@@ -251,7 +251,7 @@ func TestNilcheckKeepRemove(t *testing.T) { ...@@ -251,7 +251,7 @@ func TestNilcheckKeepRemove(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -299,7 +299,7 @@ func TestNilcheckInFalseBranch(t *testing.T) { ...@@ -299,7 +299,7 @@ func TestNilcheckInFalseBranch(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -350,7 +350,7 @@ func TestNilcheckUser(t *testing.T) { ...@@ -350,7 +350,7 @@ func TestNilcheckUser(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
...@@ -389,7 +389,7 @@ func TestNilcheckBug(t *testing.T) { ...@@ -389,7 +389,7 @@ func TestNilcheckBug(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true) c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")), Goto("checkPtr")),
Bloc("checkPtr", Bloc("checkPtr",
......
src/cmd/compile/internal/ssa/op.go
View file @ 16b1fce9
...@@ -15,10 +15,12 @@ import "fmt" ...@@ -15,10 +15,12 @@ import "fmt"
type Op int32 type Op int32
type opInfo struct { type opInfo struct {
name string name string
asm int asm int
reg regInfo reg regInfo
generic bool // this is a generic (arch-independent) opcode auxType auxType
generic bool // this is a generic (arch-independent) opcode
rematerializeable bool // this op is rematerializeable
} }
type inputInfo struct { type inputInfo struct {
...@@ -32,6 +34,22 @@ type regInfo struct { ...@@ -32,6 +34,22 @@ type regInfo struct {
outputs []regMask // NOTE: values can only have 1 output for now. outputs []regMask // NOTE: values can only have 1 output for now.
} }
type auxType int8
const (
auxNone auxType = iota
auxBool // auxInt is 0/1 for false/true
auxInt8 // auxInt is an 8-bit integer
auxInt16 // auxInt is a 16-bit integer
auxInt32 // auxInt is a 32-bit integer
auxInt64 // auxInt is a 64-bit integer
auxFloat // auxInt is a float64 (encoded with math.Float64bits)
auxString // auxInt is a string
auxSym // aux is a symbol
auxSymOff // aux is a symbol, auxInt is an offset
auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff
)
// A ValAndOff is used by the several opcodes. It holds // A ValAndOff is used by the several opcodes. It holds
// both a value and a pointer offset. // both a value and a pointer offset.
// A ValAndOff is intended to be encoded into an AuxInt field. // A ValAndOff is intended to be encoded into an AuxInt field.
......
src/cmd/compile/internal/ssa/opGen.go
View file @ 16b1fce9
...@@ -680,8 +680,9 @@ var opcodeTable = [...]opInfo{ ...@@ -680,8 +680,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSSload", name: "MOVSSload",
asm: x86.AMOVSS, auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -692,8 +693,9 @@ var opcodeTable = [...]opInfo{ ...@@ -692,8 +693,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSDload", name: "MOVSDload",
asm: x86.AMOVSD, auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -704,8 +706,10 @@ var opcodeTable = [...]opInfo{ ...@@ -704,8 +706,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSSconst", name: "MOVSSconst",
asm: x86.AMOVSS, auxType: auxFloat,
rematerializeable: true,
asm: x86.AMOVSS,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -713,8 +717,10 @@ var opcodeTable = [...]opInfo{ ...@@ -713,8 +717,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSDconst", name: "MOVSDconst",
asm: x86.AMOVSD, auxType: auxFloat,
rematerializeable: true,
asm: x86.AMOVSD,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -722,8 +728,9 @@ var opcodeTable = [...]opInfo{ ...@@ -722,8 +728,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSSloadidx4", name: "MOVSSloadidx4",
asm: x86.AMOVSS, auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -735,8 +742,9 @@ var opcodeTable = [...]opInfo{ ...@@ -735,8 +742,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSDloadidx8", name: "MOVSDloadidx8",
asm: x86.AMOVSD, auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -748,8 +756,9 @@ var opcodeTable = [...]opInfo{ ...@@ -748,8 +756,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSSstore", name: "MOVSSstore",
asm: x86.AMOVSS, auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -758,8 +767,9 @@ var opcodeTable = [...]opInfo{ ...@@ -758,8 +767,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSDstore", name: "MOVSDstore",
asm: x86.AMOVSD, auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -768,8 +778,9 @@ var opcodeTable = [...]opInfo{ ...@@ -768,8 +778,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSSstoreidx4", name: "MOVSSstoreidx4",
asm: x86.AMOVSS, auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -779,8 +790,9 @@ var opcodeTable = [...]opInfo{ ...@@ -779,8 +790,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVSDstoreidx8", name: "MOVSDstoreidx8",
asm: x86.AMOVSD, auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -846,8 +858,9 @@ var opcodeTable = [...]opInfo{ ...@@ -846,8 +858,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ADDQconst", name: "ADDQconst",
asm: x86.AADDQ, auxType: auxInt64,
asm: x86.AADDQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -859,8 +872,9 @@ var opcodeTable = [...]opInfo{ ...@@ -859,8 +872,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ADDLconst", name: "ADDLconst",
asm: x86.AADDL, auxType: auxInt32,
asm: x86.AADDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -872,8 +886,9 @@ var opcodeTable = [...]opInfo{ ...@@ -872,8 +886,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ADDWconst", name: "ADDWconst",
asm: x86.AADDW, auxType: auxInt16,
asm: x86.AADDW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -885,8 +900,9 @@ var opcodeTable = [...]opInfo{ ...@@ -885,8 +900,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ADDBconst", name: "ADDBconst",
asm: x86.AADDB, auxType: auxInt8,
asm: x86.AADDB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -954,8 +970,9 @@ var opcodeTable = [...]opInfo{ ...@@ -954,8 +970,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SUBQconst", name: "SUBQconst",
asm: x86.ASUBQ, auxType: auxInt64,
asm: x86.ASUBQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -967,8 +984,9 @@ var opcodeTable = [...]opInfo{ ...@@ -967,8 +984,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SUBLconst", name: "SUBLconst",
asm: x86.ASUBL, auxType: auxInt32,
asm: x86.ASUBL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -980,8 +998,9 @@ var opcodeTable = [...]opInfo{ ...@@ -980,8 +998,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SUBWconst", name: "SUBWconst",
asm: x86.ASUBW, auxType: auxInt16,
asm: x86.ASUBW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -993,8 +1012,9 @@ var opcodeTable = [...]opInfo{ ...@@ -993,8 +1012,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SUBBconst", name: "SUBBconst",
asm: x86.ASUBB, auxType: auxInt8,
asm: x86.ASUBB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1062,8 +1082,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1062,8 +1082,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MULQconst", name: "MULQconst",
asm: x86.AIMULQ, auxType: auxInt64,
asm: x86.AIMULQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1075,8 +1096,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1075,8 +1096,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MULLconst", name: "MULLconst",
asm: x86.AIMULL, auxType: auxInt32,
asm: x86.AIMULL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1088,8 +1110,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1088,8 +1110,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MULWconst", name: "MULWconst",
asm: x86.AIMULW, auxType: auxInt16,
asm: x86.AIMULW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1101,8 +1124,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1101,8 +1124,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MULBconst", name: "MULBconst",
asm: x86.AIMULW, auxType: auxInt8,
asm: x86.AIMULW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1422,8 +1446,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1422,8 +1446,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ANDQconst", name: "ANDQconst",
asm: x86.AANDQ, auxType: auxInt64,
asm: x86.AANDQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1435,8 +1460,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1435,8 +1460,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ANDLconst", name: "ANDLconst",
asm: x86.AANDL, auxType: auxInt32,
asm: x86.AANDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1448,8 +1474,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1448,8 +1474,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ANDWconst", name: "ANDWconst",
asm: x86.AANDW, auxType: auxInt16,
asm: x86.AANDW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1461,8 +1488,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1461,8 +1488,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ANDBconst", name: "ANDBconst",
asm: x86.AANDB, auxType: auxInt8,
asm: x86.AANDB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1530,8 +1558,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1530,8 +1558,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ORQconst", name: "ORQconst",
asm: x86.AORQ, auxType: auxInt64,
asm: x86.AORQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1543,8 +1572,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1543,8 +1572,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ORLconst", name: "ORLconst",
asm: x86.AORL, auxType: auxInt32,
asm: x86.AORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1556,8 +1586,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1556,8 +1586,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ORWconst", name: "ORWconst",
asm: x86.AORW, auxType: auxInt16,
asm: x86.AORW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1569,8 +1600,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1569,8 +1600,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ORBconst", name: "ORBconst",
asm: x86.AORB, auxType: auxInt8,
asm: x86.AORB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1638,8 +1670,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1638,8 +1670,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "XORQconst", name: "XORQconst",
asm: x86.AXORQ, auxType: auxInt64,
asm: x86.AXORQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1651,8 +1684,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1651,8 +1684,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "XORLconst", name: "XORLconst",
asm: x86.AXORL, auxType: auxInt32,
asm: x86.AXORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1664,8 +1698,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1664,8 +1698,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "XORWconst", name: "XORWconst",
asm: x86.AXORW, auxType: auxInt16,
asm: x86.AXORW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1677,8 +1712,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1677,8 +1712,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "XORBconst", name: "XORBconst",
asm: x86.AXORB, auxType: auxInt8,
asm: x86.AXORB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1742,8 +1778,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1742,8 +1778,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CMPQconst", name: "CMPQconst",
asm: x86.ACMPQ, auxType: auxInt64,
asm: x86.ACMPQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1754,8 +1791,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1754,8 +1791,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CMPLconst", name: "CMPLconst",
asm: x86.ACMPL, auxType: auxInt32,
asm: x86.ACMPL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1766,8 +1804,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1766,8 +1804,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CMPWconst", name: "CMPWconst",
asm: x86.ACMPW, auxType: auxInt16,
asm: x86.ACMPW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1778,8 +1817,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1778,8 +1817,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CMPBconst", name: "CMPBconst",
asm: x86.ACMPB, auxType: auxInt8,
asm: x86.ACMPB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1868,8 +1908,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1868,8 +1908,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "TESTQconst", name: "TESTQconst",
asm: x86.ATESTQ, auxType: auxInt64,
asm: x86.ATESTQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1880,8 +1921,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1880,8 +1921,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "TESTLconst", name: "TESTLconst",
asm: x86.ATESTL, auxType: auxInt32,
asm: x86.ATESTL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1892,8 +1934,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1892,8 +1934,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "TESTWconst", name: "TESTWconst",
asm: x86.ATESTW, auxType: auxInt16,
asm: x86.ATESTW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1904,8 +1947,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1904,8 +1947,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "TESTBconst", name: "TESTBconst",
asm: x86.ATESTB, auxType: auxInt8,
asm: x86.ATESTB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1972,8 +2016,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1972,8 +2016,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHLQconst", name: "SHLQconst",
asm: x86.ASHLQ, auxType: auxInt64,
asm: x86.ASHLQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1985,8 +2030,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1985,8 +2030,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHLLconst", name: "SHLLconst",
asm: x86.ASHLL, auxType: auxInt32,
asm: x86.ASHLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -1998,8 +2044,9 @@ var opcodeTable = [...]opInfo{ ...@@ -1998,8 +2044,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHLWconst", name: "SHLWconst",
asm: x86.ASHLW, auxType: auxInt16,
asm: x86.ASHLW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2011,8 +2058,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2011,8 +2058,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHLBconst", name: "SHLBconst",
asm: x86.ASHLB, auxType: auxInt8,
asm: x86.ASHLB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2080,8 +2128,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2080,8 +2128,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHRQconst", name: "SHRQconst",
asm: x86.ASHRQ, auxType: auxInt64,
asm: x86.ASHRQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2093,8 +2142,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2093,8 +2142,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHRLconst", name: "SHRLconst",
asm: x86.ASHRL, auxType: auxInt32,
asm: x86.ASHRL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2106,8 +2156,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2106,8 +2156,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHRWconst", name: "SHRWconst",
asm: x86.ASHRW, auxType: auxInt16,
asm: x86.ASHRW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2119,8 +2170,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2119,8 +2170,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SHRBconst", name: "SHRBconst",
asm: x86.ASHRB, auxType: auxInt8,
asm: x86.ASHRB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2188,8 +2240,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2188,8 +2240,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SARQconst", name: "SARQconst",
asm: x86.ASARQ, auxType: auxInt64,
asm: x86.ASARQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2201,8 +2254,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2201,8 +2254,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SARLconst", name: "SARLconst",
asm: x86.ASARL, auxType: auxInt32,
asm: x86.ASARL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2214,8 +2268,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2214,8 +2268,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SARWconst", name: "SARWconst",
asm: x86.ASARW, auxType: auxInt16,
asm: x86.ASARW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2227,8 +2282,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2227,8 +2282,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "SARBconst", name: "SARBconst",
asm: x86.ASARB, auxType: auxInt8,
asm: x86.ASARB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2240,8 +2296,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2240,8 +2296,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ROLQconst", name: "ROLQconst",
asm: x86.AROLQ, auxType: auxInt64,
asm: x86.AROLQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2253,8 +2310,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2253,8 +2310,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ROLLconst", name: "ROLLconst",
asm: x86.AROLL, auxType: auxInt32,
asm: x86.AROLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2266,8 +2324,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2266,8 +2324,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ROLWconst", name: "ROLWconst",
asm: x86.AROLW, auxType: auxInt16,
asm: x86.AROLW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2279,8 +2338,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2279,8 +2338,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "ROLBconst", name: "ROLBconst",
asm: x86.AROLB, auxType: auxInt8,
asm: x86.AROLB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2698,8 +2758,10 @@ var opcodeTable = [...]opInfo{ ...@@ -2698,8 +2758,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBconst", name: "MOVBconst",
asm: x86.AMOVB, auxType: auxInt8,
rematerializeable: true,
asm: x86.AMOVB,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2707,8 +2769,10 @@ var opcodeTable = [...]opInfo{ ...@@ -2707,8 +2769,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWconst", name: "MOVWconst",
asm: x86.AMOVW, auxType: auxInt16,
rematerializeable: true,
asm: x86.AMOVW,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2716,8 +2780,10 @@ var opcodeTable = [...]opInfo{ ...@@ -2716,8 +2780,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLconst", name: "MOVLconst",
asm: x86.AMOVL, auxType: auxInt32,
rematerializeable: true,
asm: x86.AMOVL,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2725,8 +2791,10 @@ var opcodeTable = [...]opInfo{ ...@@ -2725,8 +2791,10 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQconst", name: "MOVQconst",
asm: x86.AMOVQ, auxType: auxInt64,
rematerializeable: true,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2867,7 +2935,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2867,7 +2935,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "LEAQ", name: "LEAQ",
auxType: auxSymOff,
rematerializeable: true,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2878,7 +2948,8 @@ var opcodeTable = [...]opInfo{ ...@@ -2878,7 +2948,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "LEAQ1", name: "LEAQ1",
auxType: auxSymOff,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2890,7 +2961,8 @@ var opcodeTable = [...]opInfo{ ...@@ -2890,7 +2961,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "LEAQ2", name: "LEAQ2",
auxType: auxSymOff,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2902,7 +2974,8 @@ var opcodeTable = [...]opInfo{ ...@@ -2902,7 +2974,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "LEAQ4", name: "LEAQ4",
auxType: auxSymOff,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2914,7 +2987,8 @@ var opcodeTable = [...]opInfo{ ...@@ -2914,7 +2987,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "LEAQ8", name: "LEAQ8",
auxType: auxSymOff,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -2926,8 +3000,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2926,8 +3000,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBload", name: "MOVBload",
asm: x86.AMOVB, auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2938,8 +3013,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2938,8 +3013,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBQSXload", name: "MOVBQSXload",
asm: x86.AMOVBQSX, auxType: auxSymOff,
asm: x86.AMOVBQSX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2950,8 +3026,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2950,8 +3026,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBQZXload", name: "MOVBQZXload",
asm: x86.AMOVBQZX, auxType: auxSymOff,
asm: x86.AMOVBQZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2962,8 +3039,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2962,8 +3039,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWload", name: "MOVWload",
asm: x86.AMOVW, auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2974,8 +3052,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2974,8 +3052,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWQSXload", name: "MOVWQSXload",
asm: x86.AMOVWQSX, auxType: auxSymOff,
asm: x86.AMOVWQSX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2986,8 +3065,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2986,8 +3065,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWQZXload", name: "MOVWQZXload",
asm: x86.AMOVWQZX, auxType: auxSymOff,
asm: x86.AMOVWQZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -2998,8 +3078,9 @@ var opcodeTable = [...]opInfo{ ...@@ -2998,8 +3078,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLload", name: "MOVLload",
asm: x86.AMOVL, auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3010,8 +3091,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3010,8 +3091,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLQSXload", name: "MOVLQSXload",
asm: x86.AMOVLQSX, auxType: auxSymOff,
asm: x86.AMOVLQSX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3022,8 +3104,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3022,8 +3104,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLQZXload", name: "MOVLQZXload",
asm: x86.AMOVLQZX, auxType: auxSymOff,
asm: x86.AMOVLQZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3034,8 +3117,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3034,8 +3117,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQload", name: "MOVQload",
asm: x86.AMOVQ, auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3046,8 +3130,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3046,8 +3130,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQloadidx8", name: "MOVQloadidx8",
asm: x86.AMOVQ, auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3059,8 +3144,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3059,8 +3144,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBstore", name: "MOVBstore",
asm: x86.AMOVB, auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3069,8 +3155,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3069,8 +3155,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWstore", name: "MOVWstore",
asm: x86.AMOVW, auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3079,8 +3166,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3079,8 +3166,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLstore", name: "MOVLstore",
asm: x86.AMOVL, auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3089,8 +3177,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3089,8 +3177,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQstore", name: "MOVQstore",
asm: x86.AMOVQ, auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3099,8 +3188,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3099,8 +3188,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBstoreidx1", name: "MOVBstoreidx1",
asm: x86.AMOVB, auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3110,8 +3200,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3110,8 +3200,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWstoreidx2", name: "MOVWstoreidx2",
asm: x86.AMOVW, auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3121,8 +3212,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3121,8 +3212,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLstoreidx4", name: "MOVLstoreidx4",
asm: x86.AMOVL, auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3132,8 +3224,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3132,8 +3224,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQstoreidx8", name: "MOVQstoreidx8",
asm: x86.AMOVQ, auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3143,8 +3236,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3143,8 +3236,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVOload", name: "MOVOload",
asm: x86.AMOVUPS, auxType: auxSymOff,
asm: x86.AMOVUPS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3155,8 +3249,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3155,8 +3249,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVOstore", name: "MOVOstore",
asm: x86.AMOVUPS, auxType: auxSymOff,
asm: x86.AMOVUPS,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -3165,8 +3260,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3165,8 +3260,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBstoreconst", name: "MOVBstoreconst",
asm: x86.AMOVB, auxType: auxSymValAndOff,
asm: x86.AMOVB,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3174,8 +3270,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3174,8 +3270,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWstoreconst", name: "MOVWstoreconst",
asm: x86.AMOVW, auxType: auxSymValAndOff,
asm: x86.AMOVW,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3183,8 +3280,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3183,8 +3280,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVLstoreconst", name: "MOVLstoreconst",
asm: x86.AMOVL, auxType: auxSymValAndOff,
asm: x86.AMOVL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3192,8 +3290,9 @@ var opcodeTable = [...]opInfo{ ...@@ -3192,8 +3290,9 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVQstoreconst", name: "MOVQstoreconst",
asm: x86.AMOVQ, auxType: auxSymValAndOff,
asm: x86.AMOVQ,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
...@@ -3201,7 +3300,8 @@ var opcodeTable = [...]opInfo{ ...@@ -3201,7 +3300,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "DUFFZERO", name: "DUFFZERO",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 128}, // .DI {0, 128}, // .DI
...@@ -3211,7 +3311,8 @@ var opcodeTable = [...]opInfo{ ...@@ -3211,7 +3311,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVOconst", name: "MOVOconst",
rematerializeable: true,
reg: regInfo{ reg: regInfo{
outputs: []regMask{ outputs: []regMask{
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
...@@ -3230,13 +3331,15 @@ var opcodeTable = [...]opInfo{ ...@@ -3230,13 +3331,15 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CALLstatic", name: "CALLstatic",
auxType: auxSymOff,
reg: regInfo{ reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
}, },
}, },
{ {
name: "CALLclosure", name: "CALLclosure",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 4}, // .DX {1, 4}, // .DX
...@@ -3246,19 +3349,22 @@ var opcodeTable = [...]opInfo{ ...@@ -3246,19 +3349,22 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "CALLdefer", name: "CALLdefer",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
}, },
}, },
{ {
name: "CALLgo", name: "CALLgo",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
}, },
}, },
{ {
name: "CALLinter", name: "CALLinter",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
...@@ -3267,7 +3373,8 @@ var opcodeTable = [...]opInfo{ ...@@ -3267,7 +3373,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "DUFFCOPY", name: "DUFFCOPY",
auxType: auxInt64,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 128}, // .DI {0, 128}, // .DI
...@@ -3767,18 +3874,22 @@ var opcodeTable = [...]opInfo{ ...@@ -3767,18 +3874,22 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "Lrot8", name: "Lrot8",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Lrot16", name: "Lrot16",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Lrot32", name: "Lrot32",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Lrot64", name: "Lrot64",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
...@@ -4075,10 +4186,12 @@ var opcodeTable = [...]opInfo{ ...@@ -4075,10 +4186,12 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "ConstBool", name: "ConstBool",
auxType: auxBool,
generic: true, generic: true,
}, },
{ {
name: "ConstString", name: "ConstString",
auxType: auxString,
generic: true, generic: true,
}, },
{ {
...@@ -4087,26 +4200,32 @@ var opcodeTable = [...]opInfo{ ...@@ -4087,26 +4200,32 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "Const8", name: "Const8",
auxType: auxInt8,
generic: true, generic: true,
}, },
{ {
name: "Const16", name: "Const16",
auxType: auxInt16,
generic: true, generic: true,
}, },
{ {
name: "Const32", name: "Const32",
auxType: auxInt32,
generic: true, generic: true,
}, },
{ {
name: "Const64", name: "Const64",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Const32F", name: "Const32F",
auxType: auxFloat,
generic: true, generic: true,
}, },
{ {
name: "Const64F", name: "Const64F",
auxType: auxFloat,
generic: true, generic: true,
}, },
{ {
...@@ -4123,10 +4242,12 @@ var opcodeTable = [...]opInfo{ ...@@ -4123,10 +4242,12 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "Arg", name: "Arg",
auxType: auxSymOff,
generic: true, generic: true,
}, },
{ {
name: "Addr", name: "Addr",
auxType: auxSym,
generic: true, generic: true,
}, },
{ {
...@@ -4139,6 +4260,7 @@ var opcodeTable = [...]opInfo{ ...@@ -4139,6 +4260,7 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "Func", name: "Func",
auxType: auxSym,
generic: true, generic: true,
}, },
{ {
...@@ -4147,34 +4269,42 @@ var opcodeTable = [...]opInfo{ ...@@ -4147,34 +4269,42 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "Store", name: "Store",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Move", name: "Move",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "Zero", name: "Zero",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "ClosureCall", name: "ClosureCall",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "StaticCall", name: "StaticCall",
auxType: auxSymOff,
generic: true, generic: true,
}, },
{ {
name: "DeferCall", name: "DeferCall",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "GoCall", name: "GoCall",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
name: "InterCall", name: "InterCall",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
...@@ -4323,6 +4453,7 @@ var opcodeTable = [...]opInfo{ ...@@ -4323,6 +4453,7 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "OffPtr", name: "OffPtr",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
...@@ -4399,6 +4530,7 @@ var opcodeTable = [...]opInfo{ ...@@ -4399,6 +4530,7 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "StructSelect", name: "StructSelect",
auxType: auxInt64,
generic: true, generic: true,
}, },
{ {
...@@ -4419,14 +4551,17 @@ var opcodeTable = [...]opInfo{ ...@@ -4419,14 +4551,17 @@ var opcodeTable = [...]opInfo{
}, },
{ {
name: "VarDef", name: "VarDef",
auxType: auxSym,
generic: true, generic: true,
}, },
{ {
name: "VarKill", name: "VarKill",
auxType: auxSym,
generic: true, generic: true,
}, },
{ {
name: "VarLive", name: "VarLive",
auxType: auxSym,
generic: true, generic: true,
}, },
} }
......
src/cmd/compile/internal/ssa/passbm_test.go
View file @ 16b1fce9
...@@ -68,7 +68,7 @@ func genFunction(size int) []bloc { ...@@ -68,7 +68,7 @@ func genFunction(size int) []bloc {
valn := func(s string, m, n int) string { return fmt.Sprintf("%s%d-%d", s, m, n) } valn := func(s string, m, n int) string { return fmt.Sprintf("%s%d-%d", s, m, n) }
blocs = append(blocs, blocs = append(blocs,
Bloc("entry", Bloc("entry",
Valu(valn("store", 0, 4), OpArg, TypeMem, 0, ".mem"), Valu(valn("store", 0, 4), OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil), Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto(blockn(1)), Goto(blockn(1)),
), ),
......
src/cmd/compile/internal/ssa/regalloc.go
View file @ 16b1fce9
...@@ -1481,31 +1481,16 @@ func (e *edgeState) findRegFor(typ Type) Location { ...@@ -1481,31 +1481,16 @@ func (e *edgeState) findRegFor(typ Type) Location {
} }
func (v *Value) rematerializeable() bool { func (v *Value) rematerializeable() bool {
// TODO: add a flags field to opInfo for this test? if !opcodeTable[v.Op].rematerializeable {
regspec := opcodeTable[v.Op].reg
// rematerializeable ops must be able to fill any register.
outputs := regspec.outputs
if len(outputs) == 0 || countRegs(outputs[0]) <= 1 {
// Note: this case handles OpAMD64LoweredGetClosurePtr
// which can't be moved.
return false return false
} }
for _, a := range v.Args {
// We can't rematerialize instructions which
// clobber the flags register.
if regspec.clobbers&flagRegMask != 0 {
return false
}
if len(v.Args) == 0 {
return true
}
if len(v.Args) == 1 && (v.Args[0].Op == OpSP || v.Args[0].Op == OpSB) {
// SP and SB (generated by OpSP and OpSB) are always available. // SP and SB (generated by OpSP and OpSB) are always available.
return true if a.Op != OpSP && a.Op != OpSB {
return false
}
} }
return false return true
} }
type liveInfo struct { type liveInfo struct {
......
src/cmd/compile/internal/ssa/regalloc_test.go
View file @ 16b1fce9
...@@ -10,9 +10,9 @@ func TestLiveControlOps(t *testing.T) { ...@@ -10,9 +10,9 @@ func TestLiveControlOps(t *testing.T) {
c := testConfig(t) c := testConfig(t)
f := Fun(c, "entry", f := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("x", OpAMD64MOVBconst, TypeInt8, 0, 1), Valu("x", OpAMD64MOVBconst, TypeInt8, 1, nil),
Valu("y", OpAMD64MOVBconst, TypeInt8, 0, 2), Valu("y", OpAMD64MOVBconst, TypeInt8, 2, nil),
Valu("a", OpAMD64TESTB, TypeFlags, 0, nil, "x", "y"), Valu("a", OpAMD64TESTB, TypeFlags, 0, nil, "x", "y"),
Valu("b", OpAMD64TESTB, TypeFlags, 0, nil, "y", "x"), Valu("b", OpAMD64TESTB, TypeFlags, 0, nil, "y", "x"),
Eq("a", "if", "exit"), Eq("a", "if", "exit"),
......
src/cmd/compile/internal/ssa/schedule_test.go
View file @ 16b1fce9
...@@ -11,7 +11,7 @@ func TestSchedule(t *testing.T) { ...@@ -11,7 +11,7 @@ func TestSchedule(t *testing.T) {
cases := []fun{ cases := []fun{
Fun(c, "entry", Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem0", OpInitMem, TypeMem, 0, ".mem"), Valu("mem0", OpInitMem, TypeMem, 0, nil),
Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil), Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil),
Valu("v", OpConst64, TypeInt64, 12, nil), Valu("v", OpConst64, TypeInt64, 12, nil),
Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"), Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"),
......
src/cmd/compile/internal/ssa/shift_test.go
View file @ 16b1fce9
...@@ -34,7 +34,7 @@ func makeConstShiftFunc(c *Config, amount int64, op Op, typ Type) fun { ...@@ -34,7 +34,7 @@ func makeConstShiftFunc(c *Config, amount int64, op Op, typ Type) fun {
ptyp := &TypeImpl{Size_: 8, Ptr: true, Name: "ptr"} ptyp := &TypeImpl{Size_: 8, Ptr: true, Name: "ptr"}
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("SP", OpSP, TypeUInt64, 0, nil), Valu("SP", OpSP, TypeUInt64, 0, nil),
Valu("argptr", OpOffPtr, ptyp, 8, nil, "SP"), Valu("argptr", OpOffPtr, ptyp, 8, nil, "SP"),
Valu("resptr", OpOffPtr, ptyp, 16, nil, "SP"), Valu("resptr", OpOffPtr, ptyp, 16, nil, "SP"),
......
src/cmd/compile/internal/ssa/shortcircuit_test.go
View file @ 16b1fce9
...@@ -11,7 +11,7 @@ func TestShortCircuit(t *testing.T) { ...@@ -11,7 +11,7 @@ func TestShortCircuit(t *testing.T) {
fun := Fun(c, "entry", fun := Fun(c, "entry",
Bloc("entry", Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"), Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("arg1", OpArg, TypeInt64, 0, nil), Valu("arg1", OpArg, TypeInt64, 0, nil),
Valu("arg2", OpArg, TypeInt64, 0, nil), Valu("arg2", OpArg, TypeInt64, 0, nil),
Valu("arg3", OpArg, TypeInt64, 0, nil), Valu("arg3", OpArg, TypeInt64, 0, nil),
......
src/cmd/compile/internal/ssa/value.go
View file @ 16b1fce9
...@@ -57,34 +57,72 @@ func (v *Value) String() string { ...@@ -57,34 +57,72 @@ func (v *Value) String() string {
return fmt.Sprintf("v%d", v.ID) return fmt.Sprintf("v%d", v.ID)
} }
func (v *Value) AuxInt8() int8 {
if opcodeTable[v.Op].auxType != auxInt8 {
v.Fatalf("op %s doesn't have an int8 aux field", v.Op)
}
return int8(v.AuxInt)
}
func (v *Value) AuxInt16() int16 {
if opcodeTable[v.Op].auxType != auxInt16 {
v.Fatalf("op %s doesn't have an int16 aux field", v.Op)
}
return int16(v.AuxInt)
}
func (v *Value) AuxInt32() int32 {
if opcodeTable[v.Op].auxType != auxInt32 {
v.Fatalf("op %s doesn't have an int32 aux field", v.Op)
}
return int32(v.AuxInt)
}
func (v *Value) AuxFloat() float64 {
if opcodeTable[v.Op].auxType != auxFloat {
v.Fatalf("op %s doesn't have a float aux field", v.Op)
}
return math.Float64frombits(uint64(v.AuxInt))
}
func (v *Value) AuxValAndOff() ValAndOff {
if opcodeTable[v.Op].auxType != auxSymValAndOff {
v.Fatalf("op %s doesn't have a ValAndOff aux field", v.Op)
}
return ValAndOff(v.AuxInt)
}
// long form print. v# = opcode <type> [aux] args [: reg] // long form print. v# = opcode <type> [aux] args [: reg]
func (v *Value) LongString() string { func (v *Value) LongString() string {
s := fmt.Sprintf("v%d = %s", v.ID, v.Op.String()) s := fmt.Sprintf("v%d = %s", v.ID, v.Op.String())
s += " <" + v.Type.String() + ">" s += " <" + v.Type.String() + ">"
// TODO: use some operator property flags to decide switch opcodeTable[v.Op].auxType {
// what is encoded in the AuxInt field. case auxBool:
switch v.Op {
case OpConst32F, OpConst64F:
s += fmt.Sprintf(" [%g]", math.Float64frombits(uint64(v.AuxInt)))
case OpConstBool:
if v.AuxInt == 0 { if v.AuxInt == 0 {
s += " [false]" s += " [false]"
} else { } else {
s += " [true]" s += " [true]"
} }
case OpAMD64MOVBstoreconst, OpAMD64MOVWstoreconst, OpAMD64MOVLstoreconst, OpAMD64MOVQstoreconst: case auxInt8:
s += fmt.Sprintf(" [%s]", ValAndOff(v.AuxInt)) s += fmt.Sprintf(" [%d]", v.AuxInt8())
default: case auxInt16:
if v.AuxInt != 0 { s += fmt.Sprintf(" [%d]", v.AuxInt16())
s += fmt.Sprintf(" [%d]", v.AuxInt) case auxInt32:
s += fmt.Sprintf(" [%d]", v.AuxInt32())
case auxInt64:
s += fmt.Sprintf(" [%d]", v.AuxInt)
case auxFloat:
s += fmt.Sprintf(" [%g]", v.AuxFloat())
case auxString:
s += fmt.Sprintf(" {%s}", v.Aux)
case auxSymOff:
if v.Aux != nil {
s += fmt.Sprintf(" {%s}", v.Aux)
} }
} s += fmt.Sprintf(" [%s]", v.AuxInt)
if v.Aux != nil { case auxSymValAndOff:
if _, ok := v.Aux.(string); ok { if v.Aux != nil {
s += fmt.Sprintf(" {%q}", v.Aux) s += fmt.Sprintf(" {%s}", v.Aux)
} else {
s += fmt.Sprintf(" {%v}", v.Aux)
} }
s += fmt.Sprintf(" [%s]", v.AuxValAndOff())
} }
for _, a := range v.Args { for _, a := range v.Args {
s += fmt.Sprintf(" %v", a) s += fmt.Sprintf(" %v", a)
......
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