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Commit e405c9cc authored by quasilyte's avatar quasilyte Committed by Cherry Zhang
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cmd/internal/obj/x86: use named consts for movtab Z-cases 

Use 0-terminated opbyte sequences for Zlit-like movtabs instead of E=0xff.

movCodeFullPtr is unused (load full ptr is unsupported), but it should
be removed in a separate CL (if removed at all).

Passes toolstash-check.

Change-Id: I28436718d93b017153de0e50e3bcec344ea4ee05
Reviewed-on: https://go-review.googlesource.com/107076
Run-TryBot: Iskander Sharipov <iskander.sharipov@intel.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: default avatarCherry Zhang <cherryyz@google.com>
parent 47be3d49
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Showing with 141 additions and 124 deletions
src/cmd/asm/internal/asm/testdata/386enc.s
View file @ e405c9cc
...@@ -28,5 +28,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 ...@@ -28,5 +28,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
MOVL DR0, AX // 0f21c0 MOVL DR0, AX // 0f21c0
MOVL DR6, DX // 0f21f2 MOVL DR6, DX // 0f21f2
MOVL DR7, SI // 0f21fe MOVL DR7, SI // 0f21fe
// Test other movtab entries.
PUSHL SS // 16
PUSHL FS // 0fa0
POPL FS // 0fa1
POPL SS // 17
// End of tests. // End of tests.
RET RET
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
View file @ e405c9cc
...@@ -309,5 +309,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 ...@@ -309,5 +309,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
MOVQ DR0, AX // 0f21c0 MOVQ DR0, AX // 0f21c0
MOVQ DR6, DX // 0f21f2 MOVQ DR6, DX // 0f21f2
MOVQ DR7, SI // 0f21fe MOVQ DR7, SI // 0f21fe
// Test other movtab entries.
PUSHQ GS // 0fa8
PUSHQ FS // 0fa0
POPQ FS // 0fa1
POPQ GS // 0fa9
// End of tests. // End of tests.
RET RET
src/cmd/internal/obj/x86/asm6.go
View file @ e405c9cc
...@@ -3479,150 +3479,157 @@ func unbytereg(a *obj.Addr, t *uint8) { ...@@ -3479,150 +3479,157 @@ func unbytereg(a *obj.Addr, t *uint8) {
} }
const ( const (
E = 0xff movLit uint8 = iota // Like Zlit
movRegMem
movMemReg
movRegMem2op
movMemReg2op
movFullPtr // Load full pointer, trash heap (unsupported)
movDoubleShift
movTLSReg
) )
var ymovtab = []Movtab{ var ymovtab = []Movtab{
// push // push
{APUSHL, Ycs, Ynone, Ynone, 0, [4]uint8{0x0e, E, 0, 0}}, {APUSHL, Ycs, Ynone, Ynone, movLit, [4]uint8{0x0e, 0}},
{APUSHL, Yss, Ynone, Ynone, 0, [4]uint8{0x16, E, 0, 0}}, {APUSHL, Yss, Ynone, Ynone, movLit, [4]uint8{0x16, 0}},
{APUSHL, Yds, Ynone, Ynone, 0, [4]uint8{0x1e, E, 0, 0}}, {APUSHL, Yds, Ynone, Ynone, movLit, [4]uint8{0x1e, 0}},
{APUSHL, Yes, Ynone, Ynone, 0, [4]uint8{0x06, E, 0, 0}}, {APUSHL, Yes, Ynone, Ynone, movLit, [4]uint8{0x06, 0}},
{APUSHL, Yfs, Ynone, Ynone, 0, [4]uint8{0x0f, 0xa0, E, 0}}, {APUSHL, Yfs, Ynone, Ynone, movLit, [4]uint8{0x0f, 0xa0, 0}},
{APUSHL, Ygs, Ynone, Ynone, 0, [4]uint8{0x0f, 0xa8, E, 0}}, {APUSHL, Ygs, Ynone, Ynone, movLit, [4]uint8{0x0f, 0xa8, 0}},
{APUSHQ, Yfs, Ynone, Ynone, 0, [4]uint8{0x0f, 0xa0, E, 0}}, {APUSHQ, Yfs, Ynone, Ynone, movLit, [4]uint8{0x0f, 0xa0, 0}},
{APUSHQ, Ygs, Ynone, Ynone, 0, [4]uint8{0x0f, 0xa8, E, 0}}, {APUSHQ, Ygs, Ynone, Ynone, movLit, [4]uint8{0x0f, 0xa8, 0}},
{APUSHW, Ycs, Ynone, Ynone, 0, [4]uint8{Pe, 0x0e, E, 0}}, {APUSHW, Ycs, Ynone, Ynone, movLit, [4]uint8{Pe, 0x0e, 0}},
{APUSHW, Yss, Ynone, Ynone, 0, [4]uint8{Pe, 0x16, E, 0}}, {APUSHW, Yss, Ynone, Ynone, movLit, [4]uint8{Pe, 0x16, 0}},
{APUSHW, Yds, Ynone, Ynone, 0, [4]uint8{Pe, 0x1e, E, 0}}, {APUSHW, Yds, Ynone, Ynone, movLit, [4]uint8{Pe, 0x1e, 0}},
{APUSHW, Yes, Ynone, Ynone, 0, [4]uint8{Pe, 0x06, E, 0}}, {APUSHW, Yes, Ynone, Ynone, movLit, [4]uint8{Pe, 0x06, 0}},
{APUSHW, Yfs, Ynone, Ynone, 0, [4]uint8{Pe, 0x0f, 0xa0, E}}, {APUSHW, Yfs, Ynone, Ynone, movLit, [4]uint8{Pe, 0x0f, 0xa0, 0}},
{APUSHW, Ygs, Ynone, Ynone, 0, [4]uint8{Pe, 0x0f, 0xa8, E}}, {APUSHW, Ygs, Ynone, Ynone, movLit, [4]uint8{Pe, 0x0f, 0xa8, 0}},
// pop // pop
{APOPL, Ynone, Ynone, Yds, 0, [4]uint8{0x1f, E, 0, 0}}, {APOPL, Ynone, Ynone, Yds, movLit, [4]uint8{0x1f, 0}},
{APOPL, Ynone, Ynone, Yes, 0, [4]uint8{0x07, E, 0, 0}}, {APOPL, Ynone, Ynone, Yes, movLit, [4]uint8{0x07, 0}},
{APOPL, Ynone, Ynone, Yss, 0, [4]uint8{0x17, E, 0, 0}}, {APOPL, Ynone, Ynone, Yss, movLit, [4]uint8{0x17, 0}},
{APOPL, Ynone, Ynone, Yfs, 0, [4]uint8{0x0f, 0xa1, E, 0}}, {APOPL, Ynone, Ynone, Yfs, movLit, [4]uint8{0x0f, 0xa1, 0}},
{APOPL, Ynone, Ynone, Ygs, 0, [4]uint8{0x0f, 0xa9, E, 0}}, {APOPL, Ynone, Ynone, Ygs, movLit, [4]uint8{0x0f, 0xa9, 0}},
{APOPQ, Ynone, Ynone, Yfs, 0, [4]uint8{0x0f, 0xa1, E, 0}}, {APOPQ, Ynone, Ynone, Yfs, movLit, [4]uint8{0x0f, 0xa1, 0}},
{APOPQ, Ynone, Ynone, Ygs, 0, [4]uint8{0x0f, 0xa9, E, 0}}, {APOPQ, Ynone, Ynone, Ygs, movLit, [4]uint8{0x0f, 0xa9, 0}},
{APOPW, Ynone, Ynone, Yds, 0, [4]uint8{Pe, 0x1f, E, 0}}, {APOPW, Ynone, Ynone, Yds, movLit, [4]uint8{Pe, 0x1f, 0}},
{APOPW, Ynone, Ynone, Yes, 0, [4]uint8{Pe, 0x07, E, 0}}, {APOPW, Ynone, Ynone, Yes, movLit, [4]uint8{Pe, 0x07, 0}},
{APOPW, Ynone, Ynone, Yss, 0, [4]uint8{Pe, 0x17, E, 0}}, {APOPW, Ynone, Ynone, Yss, movLit, [4]uint8{Pe, 0x17, 0}},
{APOPW, Ynone, Ynone, Yfs, 0, [4]uint8{Pe, 0x0f, 0xa1, E}}, {APOPW, Ynone, Ynone, Yfs, movLit, [4]uint8{Pe, 0x0f, 0xa1, 0}},
{APOPW, Ynone, Ynone, Ygs, 0, [4]uint8{Pe, 0x0f, 0xa9, E}}, {APOPW, Ynone, Ynone, Ygs, movLit, [4]uint8{Pe, 0x0f, 0xa9, 0}},
// mov seg // mov seg
{AMOVW, Yes, Ynone, Yml, 1, [4]uint8{0x8c, 0, 0, 0}}, {AMOVW, Yes, Ynone, Yml, movRegMem, [4]uint8{0x8c, 0, 0, 0}},
{AMOVW, Ycs, Ynone, Yml, 1, [4]uint8{0x8c, 1, 0, 0}}, {AMOVW, Ycs, Ynone, Yml, movRegMem, [4]uint8{0x8c, 1, 0, 0}},
{AMOVW, Yss, Ynone, Yml, 1, [4]uint8{0x8c, 2, 0, 0}}, {AMOVW, Yss, Ynone, Yml, movRegMem, [4]uint8{0x8c, 2, 0, 0}},
{AMOVW, Yds, Ynone, Yml, 1, [4]uint8{0x8c, 3, 0, 0}}, {AMOVW, Yds, Ynone, Yml, movRegMem, [4]uint8{0x8c, 3, 0, 0}},
{AMOVW, Yfs, Ynone, Yml, 1, [4]uint8{0x8c, 4, 0, 0}}, {AMOVW, Yfs, Ynone, Yml, movRegMem, [4]uint8{0x8c, 4, 0, 0}},
{AMOVW, Ygs, Ynone, Yml, 1, [4]uint8{0x8c, 5, 0, 0}}, {AMOVW, Ygs, Ynone, Yml, movRegMem, [4]uint8{0x8c, 5, 0, 0}},
{AMOVW, Yml, Ynone, Yes, 2, [4]uint8{0x8e, 0, 0, 0}}, {AMOVW, Yml, Ynone, Yes, movMemReg, [4]uint8{0x8e, 0, 0, 0}},
{AMOVW, Yml, Ynone, Ycs, 2, [4]uint8{0x8e, 1, 0, 0}}, {AMOVW, Yml, Ynone, Ycs, movMemReg, [4]uint8{0x8e, 1, 0, 0}},
{AMOVW, Yml, Ynone, Yss, 2, [4]uint8{0x8e, 2, 0, 0}}, {AMOVW, Yml, Ynone, Yss, movMemReg, [4]uint8{0x8e, 2, 0, 0}},
{AMOVW, Yml, Ynone, Yds, 2, [4]uint8{0x8e, 3, 0, 0}}, {AMOVW, Yml, Ynone, Yds, movMemReg, [4]uint8{0x8e, 3, 0, 0}},
{AMOVW, Yml, Ynone, Yfs, 2, [4]uint8{0x8e, 4, 0, 0}}, {AMOVW, Yml, Ynone, Yfs, movMemReg, [4]uint8{0x8e, 4, 0, 0}},
{AMOVW, Yml, Ynone, Ygs, 2, [4]uint8{0x8e, 5, 0, 0}}, {AMOVW, Yml, Ynone, Ygs, movMemReg, [4]uint8{0x8e, 5, 0, 0}},
// mov cr // mov cr
{AMOVL, Ycr0, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 0, 0}}, {AMOVL, Ycr0, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 0, 0}},
{AMOVL, Ycr2, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 2, 0}}, {AMOVL, Ycr2, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 2, 0}},
{AMOVL, Ycr3, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 3, 0}}, {AMOVL, Ycr3, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 3, 0}},
{AMOVL, Ycr4, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 4, 0}}, {AMOVL, Ycr4, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 4, 0}},
{AMOVL, Ycr8, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 8, 0}}, {AMOVL, Ycr8, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 8, 0}},
{AMOVQ, Ycr0, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 0, 0}}, {AMOVQ, Ycr0, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 0, 0}},
{AMOVQ, Ycr2, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 2, 0}}, {AMOVQ, Ycr2, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 2, 0}},
{AMOVQ, Ycr3, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 3, 0}}, {AMOVQ, Ycr3, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 3, 0}},
{AMOVQ, Ycr4, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 4, 0}}, {AMOVQ, Ycr4, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 4, 0}},
{AMOVQ, Ycr8, Ynone, Yrl, 3, [4]uint8{0x0f, 0x20, 8, 0}}, {AMOVQ, Ycr8, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x20, 8, 0}},
{AMOVL, Yrl, Ynone, Ycr0, 4, [4]uint8{0x0f, 0x22, 0, 0}}, {AMOVL, Yrl, Ynone, Ycr0, movMemReg2op, [4]uint8{0x0f, 0x22, 0, 0}},
{AMOVL, Yrl, Ynone, Ycr2, 4, [4]uint8{0x0f, 0x22, 2, 0}}, {AMOVL, Yrl, Ynone, Ycr2, movMemReg2op, [4]uint8{0x0f, 0x22, 2, 0}},
{AMOVL, Yrl, Ynone, Ycr3, 4, [4]uint8{0x0f, 0x22, 3, 0}}, {AMOVL, Yrl, Ynone, Ycr3, movMemReg2op, [4]uint8{0x0f, 0x22, 3, 0}},
{AMOVL, Yrl, Ynone, Ycr4, 4, [4]uint8{0x0f, 0x22, 4, 0}}, {AMOVL, Yrl, Ynone, Ycr4, movMemReg2op, [4]uint8{0x0f, 0x22, 4, 0}},
{AMOVL, Yrl, Ynone, Ycr8, 4, [4]uint8{0x0f, 0x22, 8, 0}}, {AMOVL, Yrl, Ynone, Ycr8, movMemReg2op, [4]uint8{0x0f, 0x22, 8, 0}},
{AMOVQ, Yrl, Ynone, Ycr0, 4, [4]uint8{0x0f, 0x22, 0, 0}}, {AMOVQ, Yrl, Ynone, Ycr0, movMemReg2op, [4]uint8{0x0f, 0x22, 0, 0}},
{AMOVQ, Yrl, Ynone, Ycr2, 4, [4]uint8{0x0f, 0x22, 2, 0}}, {AMOVQ, Yrl, Ynone, Ycr2, movMemReg2op, [4]uint8{0x0f, 0x22, 2, 0}},
{AMOVQ, Yrl, Ynone, Ycr3, 4, [4]uint8{0x0f, 0x22, 3, 0}}, {AMOVQ, Yrl, Ynone, Ycr3, movMemReg2op, [4]uint8{0x0f, 0x22, 3, 0}},
{AMOVQ, Yrl, Ynone, Ycr4, 4, [4]uint8{0x0f, 0x22, 4, 0}}, {AMOVQ, Yrl, Ynone, Ycr4, movMemReg2op, [4]uint8{0x0f, 0x22, 4, 0}},
{AMOVQ, Yrl, Ynone, Ycr8, 4, [4]uint8{0x0f, 0x22, 8, 0}}, {AMOVQ, Yrl, Ynone, Ycr8, movMemReg2op, [4]uint8{0x0f, 0x22, 8, 0}},
// mov dr // mov dr
{AMOVL, Ydr0, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 0, 0}}, {AMOVL, Ydr0, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 0, 0}},
{AMOVL, Ydr6, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 6, 0}}, {AMOVL, Ydr6, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 6, 0}},
{AMOVL, Ydr7, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 7, 0}}, {AMOVL, Ydr7, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 7, 0}},
{AMOVQ, Ydr0, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 0, 0}}, {AMOVQ, Ydr0, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 0, 0}},
{AMOVQ, Ydr2, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 2, 0}}, {AMOVQ, Ydr2, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 2, 0}},
{AMOVQ, Ydr3, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 3, 0}}, {AMOVQ, Ydr3, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 3, 0}},
{AMOVQ, Ydr6, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 6, 0}}, {AMOVQ, Ydr6, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 6, 0}},
{AMOVQ, Ydr7, Ynone, Yrl, 3, [4]uint8{0x0f, 0x21, 7, 0}}, {AMOVQ, Ydr7, Ynone, Yrl, movRegMem2op, [4]uint8{0x0f, 0x21, 7, 0}},
{AMOVL, Yrl, Ynone, Ydr0, 4, [4]uint8{0x0f, 0x23, 0, 0}}, {AMOVL, Yrl, Ynone, Ydr0, movMemReg2op, [4]uint8{0x0f, 0x23, 0, 0}},
{AMOVL, Yrl, Ynone, Ydr6, 4, [4]uint8{0x0f, 0x23, 6, 0}}, {AMOVL, Yrl, Ynone, Ydr6, movMemReg2op, [4]uint8{0x0f, 0x23, 6, 0}},
{AMOVL, Yrl, Ynone, Ydr7, 4, [4]uint8{0x0f, 0x23, 7, 0}}, {AMOVL, Yrl, Ynone, Ydr7, movMemReg2op, [4]uint8{0x0f, 0x23, 7, 0}},
{AMOVQ, Yrl, Ynone, Ydr0, 4, [4]uint8{0x0f, 0x23, 0, 0}}, {AMOVQ, Yrl, Ynone, Ydr0, movMemReg2op, [4]uint8{0x0f, 0x23, 0, 0}},
{AMOVQ, Yrl, Ynone, Ydr2, 4, [4]uint8{0x0f, 0x23, 2, 0}}, {AMOVQ, Yrl, Ynone, Ydr2, movMemReg2op, [4]uint8{0x0f, 0x23, 2, 0}},
{AMOVQ, Yrl, Ynone, Ydr3, 4, [4]uint8{0x0f, 0x23, 3, 0}}, {AMOVQ, Yrl, Ynone, Ydr3, movMemReg2op, [4]uint8{0x0f, 0x23, 3, 0}},
{AMOVQ, Yrl, Ynone, Ydr6, 4, [4]uint8{0x0f, 0x23, 6, 0}}, {AMOVQ, Yrl, Ynone, Ydr6, movMemReg2op, [4]uint8{0x0f, 0x23, 6, 0}},
{AMOVQ, Yrl, Ynone, Ydr7, 4, [4]uint8{0x0f, 0x23, 7, 0}}, {AMOVQ, Yrl, Ynone, Ydr7, movMemReg2op, [4]uint8{0x0f, 0x23, 7, 0}},
// mov tr // mov tr
{AMOVL, Ytr6, Ynone, Yml, 3, [4]uint8{0x0f, 0x24, 6, 0}}, {AMOVL, Ytr6, Ynone, Yml, movRegMem2op, [4]uint8{0x0f, 0x24, 6, 0}},
{AMOVL, Ytr7, Ynone, Yml, 3, [4]uint8{0x0f, 0x24, 7, 0}}, {AMOVL, Ytr7, Ynone, Yml, movRegMem2op, [4]uint8{0x0f, 0x24, 7, 0}},
{AMOVL, Yml, Ynone, Ytr6, 4, [4]uint8{0x0f, 0x26, 6, E}}, {AMOVL, Yml, Ynone, Ytr6, movMemReg2op, [4]uint8{0x0f, 0x26, 6, 0xff}},
{AMOVL, Yml, Ynone, Ytr7, 4, [4]uint8{0x0f, 0x26, 7, E}}, {AMOVL, Yml, Ynone, Ytr7, movMemReg2op, [4]uint8{0x0f, 0x26, 7, 0xff}},
// lgdt, sgdt, lidt, sidt // lgdt, sgdt, lidt, sidt
{AMOVL, Ym, Ynone, Ygdtr, 4, [4]uint8{0x0f, 0x01, 2, 0}}, {AMOVL, Ym, Ynone, Ygdtr, movMemReg2op, [4]uint8{0x0f, 0x01, 2, 0}},
{AMOVL, Ygdtr, Ynone, Ym, 3, [4]uint8{0x0f, 0x01, 0, 0}}, {AMOVL, Ygdtr, Ynone, Ym, movRegMem2op, [4]uint8{0x0f, 0x01, 0, 0}},
{AMOVL, Ym, Ynone, Yidtr, 4, [4]uint8{0x0f, 0x01, 3, 0}}, {AMOVL, Ym, Ynone, Yidtr, movMemReg2op, [4]uint8{0x0f, 0x01, 3, 0}},
{AMOVL, Yidtr, Ynone, Ym, 3, [4]uint8{0x0f, 0x01, 1, 0}}, {AMOVL, Yidtr, Ynone, Ym, movRegMem2op, [4]uint8{0x0f, 0x01, 1, 0}},
{AMOVQ, Ym, Ynone, Ygdtr, 4, [4]uint8{0x0f, 0x01, 2, 0}}, {AMOVQ, Ym, Ynone, Ygdtr, movMemReg2op, [4]uint8{0x0f, 0x01, 2, 0}},
{AMOVQ, Ygdtr, Ynone, Ym, 3, [4]uint8{0x0f, 0x01, 0, 0}}, {AMOVQ, Ygdtr, Ynone, Ym, movRegMem2op, [4]uint8{0x0f, 0x01, 0, 0}},
{AMOVQ, Ym, Ynone, Yidtr, 4, [4]uint8{0x0f, 0x01, 3, 0}}, {AMOVQ, Ym, Ynone, Yidtr, movMemReg2op, [4]uint8{0x0f, 0x01, 3, 0}},
{AMOVQ, Yidtr, Ynone, Ym, 3, [4]uint8{0x0f, 0x01, 1, 0}}, {AMOVQ, Yidtr, Ynone, Ym, movRegMem2op, [4]uint8{0x0f, 0x01, 1, 0}},
// lldt, sldt // lldt, sldt
{AMOVW, Yml, Ynone, Yldtr, 4, [4]uint8{0x0f, 0x00, 2, 0}}, {AMOVW, Yml, Ynone, Yldtr, movMemReg2op, [4]uint8{0x0f, 0x00, 2, 0}},
{AMOVW, Yldtr, Ynone, Yml, 3, [4]uint8{0x0f, 0x00, 0, 0}}, {AMOVW, Yldtr, Ynone, Yml, movRegMem2op, [4]uint8{0x0f, 0x00, 0, 0}},
// lmsw, smsw // lmsw, smsw
{AMOVW, Yml, Ynone, Ymsw, 4, [4]uint8{0x0f, 0x01, 6, 0}}, {AMOVW, Yml, Ynone, Ymsw, movMemReg2op, [4]uint8{0x0f, 0x01, 6, 0}},
{AMOVW, Ymsw, Ynone, Yml, 3, [4]uint8{0x0f, 0x01, 4, 0}}, {AMOVW, Ymsw, Ynone, Yml, movRegMem2op, [4]uint8{0x0f, 0x01, 4, 0}},
// ltr, str // ltr, str
{AMOVW, Yml, Ynone, Ytask, 4, [4]uint8{0x0f, 0x00, 3, 0}}, {AMOVW, Yml, Ynone, Ytask, movMemReg2op, [4]uint8{0x0f, 0x00, 3, 0}},
{AMOVW, Ytask, Ynone, Yml, 3, [4]uint8{0x0f, 0x00, 1, 0}}, {AMOVW, Ytask, Ynone, Yml, movRegMem2op, [4]uint8{0x0f, 0x00, 1, 0}},
/* load full pointer - unsupported /* load full pointer - unsupported
Movtab{AMOVL, Yml, Ycol, 5, [4]uint8{0, 0, 0, 0}}, Movtab{AMOVL, Yml, Ycol, movFullPtr, [4]uint8{0, 0, 0, 0}},
Movtab{AMOVW, Yml, Ycol, 5, [4]uint8{Pe, 0, 0, 0}}, Movtab{AMOVW, Yml, Ycol, movFullPtr, [4]uint8{Pe, 0, 0, 0}},
*/ */
// double shift // double shift
{ASHLL, Yi8, Yrl, Yml, 6, [4]uint8{0xa4, 0xa5, 0, 0}}, {ASHLL, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
{ASHLL, Ycl, Yrl, Yml, 6, [4]uint8{0xa4, 0xa5, 0, 0}}, {ASHLL, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
{ASHLL, Ycx, Yrl, Yml, 6, [4]uint8{0xa4, 0xa5, 0, 0}}, {ASHLL, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
{ASHRL, Yi8, Yrl, Yml, 6, [4]uint8{0xac, 0xad, 0, 0}}, {ASHRL, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{0xac, 0xad, 0, 0}},
{ASHRL, Ycl, Yrl, Yml, 6, [4]uint8{0xac, 0xad, 0, 0}}, {ASHRL, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{0xac, 0xad, 0, 0}},
{ASHRL, Ycx, Yrl, Yml, 6, [4]uint8{0xac, 0xad, 0, 0}}, {ASHRL, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{0xac, 0xad, 0, 0}},
{ASHLQ, Yi8, Yrl, Yml, 6, [4]uint8{Pw, 0xa4, 0xa5, 0}}, {ASHLQ, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xa4, 0xa5, 0}},
{ASHLQ, Ycl, Yrl, Yml, 6, [4]uint8{Pw, 0xa4, 0xa5, 0}}, {ASHLQ, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xa4, 0xa5, 0}},
{ASHLQ, Ycx, Yrl, Yml, 6, [4]uint8{Pw, 0xa4, 0xa5, 0}}, {ASHLQ, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xa4, 0xa5, 0}},
{ASHRQ, Yi8, Yrl, Yml, 6, [4]uint8{Pw, 0xac, 0xad, 0}}, {ASHRQ, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xac, 0xad, 0}},
{ASHRQ, Ycl, Yrl, Yml, 6, [4]uint8{Pw, 0xac, 0xad, 0}}, {ASHRQ, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xac, 0xad, 0}},
{ASHRQ, Ycx, Yrl, Yml, 6, [4]uint8{Pw, 0xac, 0xad, 0}}, {ASHRQ, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{Pw, 0xac, 0xad, 0}},
{ASHLW, Yi8, Yrl, Yml, 6, [4]uint8{Pe, 0xa4, 0xa5, 0}}, {ASHLW, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xa4, 0xa5, 0}},
{ASHLW, Ycl, Yrl, Yml, 6, [4]uint8{Pe, 0xa4, 0xa5, 0}}, {ASHLW, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xa4, 0xa5, 0}},
{ASHLW, Ycx, Yrl, Yml, 6, [4]uint8{Pe, 0xa4, 0xa5, 0}}, {ASHLW, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xa4, 0xa5, 0}},
{ASHRW, Yi8, Yrl, Yml, 6, [4]uint8{Pe, 0xac, 0xad, 0}}, {ASHRW, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xac, 0xad, 0}},
{ASHRW, Ycl, Yrl, Yml, 6, [4]uint8{Pe, 0xac, 0xad, 0}}, {ASHRW, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xac, 0xad, 0}},
{ASHRW, Ycx, Yrl, Yml, 6, [4]uint8{Pe, 0xac, 0xad, 0}}, {ASHRW, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{Pe, 0xac, 0xad, 0}},
// load TLS base // load TLS base
{AMOVL, Ytls, Ynone, Yrl, 7, [4]uint8{0, 0, 0, 0}}, {AMOVL, Ytls, Ynone, Yrl, movTLSReg, [4]uint8{0, 0, 0, 0}},
{AMOVQ, Ytls, Ynone, Yrl, 7, [4]uint8{0, 0, 0, 0}}, {AMOVQ, Ytls, Ynone, Yrl, movTLSReg, [4]uint8{0, 0, 0, 0}},
{0, 0, 0, 0, 0, [4]uint8{}}, {0, 0, 0, 0, 0, [4]uint8{}},
} }
...@@ -4424,30 +4431,30 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) { ...@@ -4424,30 +4431,30 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) {
default: default:
ctxt.Diag("asmins: unknown mov %d %v", mo[0].code, p) ctxt.Diag("asmins: unknown mov %d %v", mo[0].code, p)
case 0: // lit case movLit:
for z = 0; t[z] != E; z++ { for z = 0; t[z] != 0; z++ {
ab.Put1(t[z]) ab.Put1(t[z])
} }
case 1: // r,m case movRegMem:
ab.Put1(t[0]) ab.Put1(t[0])
ab.asmando(ctxt, cursym, p, &p.To, int(t[1])) ab.asmando(ctxt, cursym, p, &p.To, int(t[1]))
case 2: // m,r case movMemReg:
ab.Put1(t[0]) ab.Put1(t[0])
ab.asmando(ctxt, cursym, p, &p.From, int(t[1])) ab.asmando(ctxt, cursym, p, &p.From, int(t[1]))
case 3: // r,m - 2op case movRegMem2op: // r,m - 2op
ab.Put2(t[0], t[1]) ab.Put2(t[0], t[1])
ab.asmando(ctxt, cursym, p, &p.To, int(t[2])) ab.asmando(ctxt, cursym, p, &p.To, int(t[2]))
ab.rexflag |= regrex[p.From.Reg] & (Rxr | 0x40) ab.rexflag |= regrex[p.From.Reg] & (Rxr | 0x40)
case 4: // m,r - 2op case movMemReg2op:
ab.Put2(t[0], t[1]) ab.Put2(t[0], t[1])
ab.asmando(ctxt, cursym, p, &p.From, int(t[2])) ab.asmando(ctxt, cursym, p, &p.From, int(t[2]))
ab.rexflag |= regrex[p.To.Reg] & (Rxr | 0x40) ab.rexflag |= regrex[p.To.Reg] & (Rxr | 0x40)
case 5: // load full pointer, trash heap case movFullPtr:
if t[0] != 0 { if t[0] != 0 {
ab.Put1(t[0]) ab.Put1(t[0])
} }
...@@ -4473,7 +4480,7 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) { ...@@ -4473,7 +4480,7 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) {
ab.asmand(ctxt, cursym, p, &p.From, &p.To) ab.asmand(ctxt, cursym, p, &p.From, &p.To)
case 6: // double shift case movDoubleShift:
if t[0] == Pw { if t[0] == Pw {
if ctxt.Arch.Family != sys.AMD64 { if ctxt.Arch.Family != sys.AMD64 {
ctxt.Diag("asmins: illegal 64: %v", p) ctxt.Diag("asmins: illegal 64: %v", p)
...@@ -4509,7 +4516,7 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) { ...@@ -4509,7 +4516,7 @@ func (ab *AsmBuf) doasm(ctxt *obj.Link, cursym *obj.LSym, p *obj.Prog) {
// where you load the TLS base register into a register and then index off that // where you load the TLS base register into a register and then index off that
// register to access the actual TLS variables. Systems that allow direct TLS access // register to access the actual TLS variables. Systems that allow direct TLS access
// are handled in prefixof above and should not be listed here. // are handled in prefixof above and should not be listed here.
case 7: // mov tls, r case movTLSReg:
if ctxt.Arch.Family == sys.AMD64 && p.As != AMOVQ || ctxt.Arch.Family == sys.I386 && p.As != AMOVL { if ctxt.Arch.Family == sys.AMD64 && p.As != AMOVQ || ctxt.Arch.Family == sys.I386 && p.As != AMOVL {
ctxt.Diag("invalid load of TLS: %v", p) ctxt.Diag("invalid load of TLS: %v", p)
} }
......
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