Commit e66ad16d authored by Russ Cox's avatar Russ Cox

liblink: renumber ARM conditions to make C_SCOND_NONE == 0

A step toward making the zero Prog useful.

Change-Id: I427b98b1ce9bd8f093da825aa4bb83244fc01903
Reviewed-on: https://go-review.googlesource.com/3573Reviewed-by: default avatarDave Cheney <dave@cheney.net>
Reviewed-by: default avatarAustin Clements <austin@google.com>
parent 77a415e5
...@@ -95,7 +95,7 @@ enum ...@@ -95,7 +95,7 @@ enum
CMACRO, CMACRO,
CPREPROC, CPREPROC,
Always = 14, Always = C_SCOND_NONE,
}; };
EXTERN int debug[256]; EXTERN int debug[256];
......
...@@ -295,7 +295,7 @@ inst: ...@@ -295,7 +295,7 @@ inst:
g.offset = g.offset =
(0xe << 24) | /* opcode */ (0xe << 24) | /* opcode */
($1 << 20) | /* MCR/MRC */ ($1 << 20) | /* MCR/MRC */
($2 << 28) | /* scond */ (($2^C_SCOND_XOR) << 28) | /* scond */
(($3 & 15) << 8) | /* coprocessor number */ (($3 & 15) << 8) | /* coprocessor number */
(($5 & 7) << 21) | /* coprocessor operation */ (($5 & 7) << 21) | /* coprocessor operation */
(($7 & 15) << 12) | /* arm register */ (($7 & 15) << 12) | /* arm register */
......
...@@ -255,23 +255,23 @@ struct ...@@ -255,23 +255,23 @@ struct
"FPSR", LFCR, REG_FPSR, "FPSR", LFCR, REG_FPSR,
"FPCR", LFCR, REG_FPCR, "FPCR", LFCR, REG_FPCR,
".EQ", LCOND, 0, ".EQ", LCOND, C_SCOND_EQ,
".NE", LCOND, 1, ".NE", LCOND, C_SCOND_NE,
".CS", LCOND, 2, ".CS", LCOND, C_SCOND_HS,
".HS", LCOND, 2, ".HS", LCOND, C_SCOND_HS,
".CC", LCOND, 3, ".CC", LCOND, C_SCOND_LO,
".LO", LCOND, 3, ".LO", LCOND, C_SCOND_LO,
".MI", LCOND, 4, ".MI", LCOND, C_SCOND_MI,
".PL", LCOND, 5, ".PL", LCOND, C_SCOND_PL,
".VS", LCOND, 6, ".VS", LCOND, C_SCOND_VS,
".VC", LCOND, 7, ".VC", LCOND, C_SCOND_VC,
".HI", LCOND, 8, ".HI", LCOND, C_SCOND_HI,
".LS", LCOND, 9, ".LS", LCOND, C_SCOND_LS,
".GE", LCOND, 10, ".GE", LCOND, C_SCOND_GE,
".LT", LCOND, 11, ".LT", LCOND, C_SCOND_LT,
".GT", LCOND, 12, ".GT", LCOND, C_SCOND_GT,
".LE", LCOND, 13, ".LE", LCOND, C_SCOND_LE,
".AL", LCOND, Always, ".AL", LCOND, C_SCOND_NONE,
".U", LS, C_UBIT, ".U", LS, C_UBIT,
".S", LS, C_SBIT, ".S", LS, C_SBIT,
...@@ -505,8 +505,8 @@ outcode(int a, int scond, Addr *g1, int reg, Addr *g2) ...@@ -505,8 +505,8 @@ outcode(int a, int scond, Addr *g1, int reg, Addr *g2)
/* hack to make B.NE etc. work: turn it into the corresponding conditional */ /* hack to make B.NE etc. work: turn it into the corresponding conditional */
if(a == AB){ if(a == AB){
a = bcode[scond&0xf]; a = bcode[(scond^C_SCOND_XOR)&0xf];
scond = (scond & ~0xf) | Always; scond = (scond & ~0xf) | C_SCOND_NONE;
} }
if(pass == 1) if(pass == 1)
......
...@@ -2028,7 +2028,7 @@ yyreduce: ...@@ -2028,7 +2028,7 @@ yyreduce:
g.offset = g.offset =
(0xe << 24) | /* opcode */ (0xe << 24) | /* opcode */
((yyvsp[(1) - (12)].lval) << 20) | /* MCR/MRC */ ((yyvsp[(1) - (12)].lval) << 20) | /* MCR/MRC */
((yyvsp[(2) - (12)].lval) << 28) | /* scond */ (((yyvsp[(2) - (12)].lval)^C_SCOND_XOR) << 28) | /* scond */
(((yyvsp[(3) - (12)].lval) & 15) << 8) | /* coprocessor number */ (((yyvsp[(3) - (12)].lval) & 15) << 8) | /* coprocessor number */
(((yyvsp[(5) - (12)].lval) & 7) << 21) | /* coprocessor operation */ (((yyvsp[(5) - (12)].lval) & 7) << 21) | /* coprocessor operation */
(((yyvsp[(7) - (12)].lval) & 15) << 12) | /* arm register */ (((yyvsp[(7) - (12)].lval) & 15) << 12) | /* arm register */
......
...@@ -321,22 +321,27 @@ enum ...@@ -321,22 +321,27 @@ enum
C_FBIT = 1<<7, /* psr flags-only */ C_FBIT = 1<<7, /* psr flags-only */
C_UBIT = 1<<7, /* up bit, unsigned bit */ C_UBIT = 1<<7, /* up bit, unsigned bit */
C_SCOND_EQ = 0, // These constants are the ARM condition codes encodings,
C_SCOND_NE = 1, // XORed with 14 so that C_SCOND_NONE has value 0,
C_SCOND_HS = 2, // so that a zeroed Prog.scond means "always execute".
C_SCOND_LO = 3, C_SCOND_XOR = 14,
C_SCOND_MI = 4,
C_SCOND_PL = 5, C_SCOND_EQ = 0 ^ C_SCOND_XOR,
C_SCOND_VS = 6, C_SCOND_NE = 1 ^ C_SCOND_XOR,
C_SCOND_VC = 7, C_SCOND_HS = 2 ^ C_SCOND_XOR,
C_SCOND_HI = 8, C_SCOND_LO = 3 ^ C_SCOND_XOR,
C_SCOND_LS = 9, C_SCOND_MI = 4 ^ C_SCOND_XOR,
C_SCOND_GE = 10, C_SCOND_PL = 5 ^ C_SCOND_XOR,
C_SCOND_LT = 11, C_SCOND_VS = 6 ^ C_SCOND_XOR,
C_SCOND_GT = 12, C_SCOND_VC = 7 ^ C_SCOND_XOR,
C_SCOND_LE = 13, C_SCOND_HI = 8 ^ C_SCOND_XOR,
C_SCOND_NONE = 14, C_SCOND_LS = 9 ^ C_SCOND_XOR,
C_SCOND_NV = 15, C_SCOND_GE = 10 ^ C_SCOND_XOR,
C_SCOND_LT = 11 ^ C_SCOND_XOR,
C_SCOND_GT = 12 ^ C_SCOND_XOR,
C_SCOND_LE = 13 ^ C_SCOND_XOR,
C_SCOND_NONE = 14 ^ C_SCOND_XOR,
C_SCOND_NV = 15 ^ C_SCOND_XOR,
/* D_SHIFT type */ /* D_SHIFT type */
SHIFT_LL = 0<<5, SHIFT_LL = 0<<5,
......
This diff is collapsed.
...@@ -90,7 +90,7 @@ Pconv(Fmt *fp) ...@@ -90,7 +90,7 @@ Pconv(Fmt *fp)
bigP = p; bigP = p;
a = p->as; a = p->as;
s = p->scond; s = p->scond;
strcpy(sc, extra[s & C_SCOND]); strcpy(sc, extra[(s & C_SCOND) ^ C_SCOND_XOR]);
if(s & C_SBIT) if(s & C_SBIT)
strcat(sc, ".S"); strcat(sc, ".S");
if(s & C_PBIT) if(s & C_PBIT)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment