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Commit e96b2329 authored by Ilya Tocar's avatar Ilya Tocar Committed by Keith Randall
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[dev.ssa] cmd/compile: promote byte/word operation 

Writing to low 8/16 bits of register creates false dependency
Generate 32-bit operations when possible.

Change-Id: I8eb6c1c43a66424eec6baa91a660bceb6b80d1d3
Reviewed-on: https://go-review.googlesource.com/19506Reviewed-by: default avatarKeith Randall <khr@golang.org>
Run-TryBot: Ilya Tocar <ilya.tocar@intel.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
parent 6a8a9da5
Expand all Show whitespace changes
Inline Side-by-side
Showing with 112 additions and 97 deletions
src/cmd/compile/internal/gc/ssa.go
View file @ e96b2329
......@@ -3793,7 +3793,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDL:
asm = x86.ALEAL
case ssa.OpAMD64ADDW:
asm = x86.ALEAW
asm = x86.ALEAL
}
p := Prog(asm)
p.From.Type = obj.TYPE_MEM
......@@ -3843,10 +3843,16 @@ func (s *genState) genValue(v *ssa.Value) {
opregreg(v.Op.Asm(), r, y)
if neg {
p := Prog(x86.ANEGQ) // TODO: use correct size? This is mostly a hack until regalloc does 2-address correctly
if v.Op == ssa.OpAMD64SUBQ {
p := Prog(x86.ANEGQ)
p.To.Type = obj.TYPE_REG
p.To.Reg = r
} else { // Avoids partial registers write
p := Prog(x86.ANEGL)
p.To.Type = obj.TYPE_REG
p.To.Reg = r
}
}
case ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD:
r := regnum(v)
x := regnum(v.Args[0])
......@@ -4035,7 +4041,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst:
asm = x86.AINCL
case ssa.OpAMD64ADDWconst:
asm = x86.AINCW
asm = x86.AINCL
}
p := Prog(asm)
p.To.Type = obj.TYPE_REG
......@@ -4049,7 +4055,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst:
asm = x86.ADECL
case ssa.OpAMD64ADDWconst:
asm = x86.ADECW
asm = x86.ADECL
}
p := Prog(asm)
p.To.Type = obj.TYPE_REG
......@@ -4071,7 +4077,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst:
asm = x86.ALEAL
case ssa.OpAMD64ADDWconst:
asm = x86.ALEAW
asm = x86.ALEAL
}
p := Prog(asm)
p.From.Type = obj.TYPE_MEM
......@@ -4131,7 +4137,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst:
asm = x86.AINCL
case ssa.OpAMD64SUBWconst:
asm = x86.AINCW
asm = x86.AINCL
}
p := Prog(asm)
p.To.Type = obj.TYPE_REG
......@@ -4144,7 +4150,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst:
asm = x86.ADECL
case ssa.OpAMD64SUBWconst:
asm = x86.ADECW
asm = x86.ADECL
}
p := Prog(asm)
p.To.Type = obj.TYPE_REG
......@@ -4157,7 +4163,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst:
asm = x86.ALEAL
case ssa.OpAMD64SUBWconst:
asm = x86.ALEAW
asm = x86.ALEAL
}
p := Prog(asm)
p.From.Type = obj.TYPE_MEM
......@@ -4596,8 +4602,8 @@ func (s *genState) genValue(v *ssa.Value) {
q := Prog(x86.ASETPS)
q.To.Type = obj.TYPE_REG
q.To.Reg = x86.REG_AX
// TODO AORQ copied from old code generator, why not AORB?
opregreg(x86.AORQ, regnum(v), x86.REG_AX)
// ORL avoids partial register write and is smaller than ORQ, used by old compiler
opregreg(x86.AORL, regnum(v), x86.REG_AX)
case ssa.OpAMD64SETEQF:
p := Prog(v.Op.Asm())
......@@ -4606,8 +4612,8 @@ func (s *genState) genValue(v *ssa.Value) {
q := Prog(x86.ASETPC)
q.To.Type = obj.TYPE_REG
q.To.Reg = x86.REG_AX
// TODO AANDQ copied from old code generator, why not AANDB?
opregreg(x86.AANDQ, regnum(v), x86.REG_AX)
// ANDL avoids partial register write and is smaller than ANDQ, used by old compiler
opregreg(x86.AANDL, regnum(v), x86.REG_AX)
case ssa.OpAMD64InvertFlags:
v.Fatalf("InvertFlags should never make it to codegen %v", v)
......@@ -5019,7 +5025,15 @@ var ssaRegToReg = [...]int16{
// loadByType returns the load instruction of the given type.
func loadByType(t ssa.Type) int {
// For x86, there's no difference between load and store opcodes.
// Avoid partial register write
if !t.IsFloat() && t.Size() <= 2 {
if t.Size() == 1 {
return x86.AMOVBLZX
} else {
return x86.AMOVWLZX
}
}
// Otherwise, there's no difference between load and store opcodes.
return storeByType(t)
}
......@@ -5059,9 +5073,10 @@ func moveByType(t ssa.Type) int {
} else {
switch t.Size() {
case 1:
return x86.AMOVB
// Avoids partial register write
return x86.AMOVL
case 2:
return x86.AMOVW
return x86.AMOVL
case 4:
return x86.AMOVL
case 8:
......
src/cmd/compile/internal/ssa/opGen.go
View file @ e96b2329
......@@ -865,7 +865,7 @@ var opcodeTable = [...]opInfo{
{
name: "ADDW",
argLen: 2,
asm: x86.AADDW,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -880,7 +880,7 @@ var opcodeTable = [...]opInfo{
{
name: "ADDB",
argLen: 2,
asm: x86.AADDB,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -926,7 +926,7 @@ var opcodeTable = [...]opInfo{
name: "ADDWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.AADDW,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -941,7 +941,7 @@ var opcodeTable = [...]opInfo{
name: "ADDBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.AADDB,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -985,7 +985,7 @@ var opcodeTable = [...]opInfo{
{
name: "SUBW",
argLen: 2,
asm: x86.ASUBW,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1000,7 +1000,7 @@ var opcodeTable = [...]opInfo{
{
name: "SUBB",
argLen: 2,
asm: x86.ASUBB,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1046,7 +1046,7 @@ var opcodeTable = [...]opInfo{
name: "SUBWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.ASUBW,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1061,7 +1061,7 @@ var opcodeTable = [...]opInfo{
name: "SUBBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.ASUBB,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1539,7 +1539,7 @@ var opcodeTable = [...]opInfo{
{
name: "ANDW",
argLen: 2,
asm: x86.AANDW,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1554,7 +1554,7 @@ var opcodeTable = [...]opInfo{
{
name: "ANDB",
argLen: 2,
asm: x86.AANDB,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1600,7 +1600,7 @@ var opcodeTable = [...]opInfo{
name: "ANDWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.AANDW,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1615,7 +1615,7 @@ var opcodeTable = [...]opInfo{
name: "ANDBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.AANDB,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1659,7 +1659,7 @@ var opcodeTable = [...]opInfo{
{
name: "ORW",
argLen: 2,
asm: x86.AORW,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1674,7 +1674,7 @@ var opcodeTable = [...]opInfo{
{
name: "ORB",
argLen: 2,
asm: x86.AORB,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1720,7 +1720,7 @@ var opcodeTable = [...]opInfo{
name: "ORWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.AORW,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1735,7 +1735,7 @@ var opcodeTable = [...]opInfo{
name: "ORBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.AORB,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1779,7 +1779,7 @@ var opcodeTable = [...]opInfo{
{
name: "XORW",
argLen: 2,
asm: x86.AXORW,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1794,7 +1794,7 @@ var opcodeTable = [...]opInfo{
{
name: "XORB",
argLen: 2,
asm: x86.AXORB,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1840,7 +1840,7 @@ var opcodeTable = [...]opInfo{
name: "XORWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.AXORW,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -1855,7 +1855,7 @@ var opcodeTable = [...]opInfo{
name: "XORBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.AXORB,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2151,7 +2151,7 @@ var opcodeTable = [...]opInfo{
{
name: "SHLW",
argLen: 2,
asm: x86.ASHLW,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // .CX
......@@ -2166,7 +2166,7 @@ var opcodeTable = [...]opInfo{
{
name: "SHLB",
argLen: 2,
asm: x86.ASHLB,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // .CX
......@@ -2212,7 +2212,7 @@ var opcodeTable = [...]opInfo{
name: "SHLWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.ASHLW,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2227,7 +2227,7 @@ var opcodeTable = [...]opInfo{
name: "SHLBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.ASHLB,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2569,7 +2569,7 @@ var opcodeTable = [...]opInfo{
{
name: "NEGW",
argLen: 1,
asm: x86.ANEGW,
asm: x86.ANEGL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2583,7 +2583,7 @@ var opcodeTable = [...]opInfo{
{
name: "NEGB",
argLen: 1,
asm: x86.ANEGB,
asm: x86.ANEGL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2625,7 +2625,7 @@ var opcodeTable = [...]opInfo{
{
name: "NOTW",
argLen: 1,
asm: x86.ANOTW,
asm: x86.ANOTL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -2639,7 +2639,7 @@ var opcodeTable = [...]opInfo{
{
name: "NOTB",
argLen: 1,
asm: x86.ANOTB,
asm: x86.ANOTL,
reg: regInfo{
inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -3243,7 +3243,7 @@ var opcodeTable = [...]opInfo{
name: "MOVBload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVB,
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
......@@ -3285,7 +3285,7 @@ var opcodeTable = [...]opInfo{
name: "MOVWload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVW,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
......@@ -3457,7 +3457,7 @@ var opcodeTable = [...]opInfo{
name: "MOVBloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVB,
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......@@ -3472,7 +3472,7 @@ var opcodeTable = [...]opInfo{
name: "MOVWloadidx2",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVW,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
......
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