STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge

MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
time. Active port input stream will be de-serialized and its content outputted
through PARALLEL output port.
CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
input port is a single lane 800Mbps. Both ports support clock and data lane
polarity swap. First port also supports data lane swap.
PARALLEL output port has a maximum width of 12 bits.
Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.

Required Properties:
- compatible: shall be "st,st-mipid02"
- clocks: reference to the xclk input clock.
- clock-names: shall be "xclk".
- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.

Optional Properties:
- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
	       This is an active low signal to the mipid02.

Required subnodes:
  - ports: A ports node with one port child node per device input and output
	   port, in accordance with the video interface bindings defined in
	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
	   port nodes are numbered as follows:

	   Port Description
	   -----------------------------
	   0    CSI-2 first input port
	   1    CSI-2 second input port
	   2    PARALLEL output

Endpoint node required property for CSI-2 connection is:
- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
Endpoint node optional property for CSI-2 connection is:
- lane-polarities: any lane can be inverted or not.

Endpoint node required property for PARALLEL connection is:
- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
Endpoint node optional properties for PARALLEL connection are:
- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
LOW being the default.
- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
LOW being the default.

Example:

mipid02: csi2rx@14 {
	compatible = "st,st-mipid02";
	reg = <0x14>;
	status = "okay";
	clocks = <&clk_ext_camera_12>;
	clock-names = "xclk";
	VDDE-supply = <&vdd>;
	VDDIN-supply = <&vdd>;
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;

			ep0: endpoint {
				data-lanes = <1 2>;
				remote-endpoint = <&mipi_csi2_in>;
			};
		};
		port@2 {
			reg = <2>;

			ep2: endpoint {
				bus-width = <8>;
				hsync-active = <0>;
				vsync-active = <0>;
				remote-endpoint = <&parallel_out>;
			};
		};
	};
};
