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 =  Zynq UltraScale+ MPSoC and Versal reset driver binding =
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The Zynq UltraScale+ MPSoC and Versal has several different resets.

See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
about zynqmp resets.

Please also refer to reset.txt in this directory for common reset
controller binding usage.

Required Properties:
- compatible:	"xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
		"xlnx,versal-reset" for Versal platform
- #reset-cells:	Specifies the number of cells needed to encode reset
		line, should be 1

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Example
-------

firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";

		zynqmp_reset: reset-controller {
			compatible = "xlnx,zynqmp-reset";
			#reset-cells = <1>;
		};
	};
};

Specifying reset lines connected to IP modules
==============================================

Device nodes that need access to reset lines should
specify them as a reset phandle in their corresponding node as
specified in reset.txt.

For list of all valid reset indices for Zynq UltraScale+ MPSoC see
<dt-bindings/reset/xlnx-zynqmp-resets.h>
For list of all valid reset indices for Versal see
<dt-bindings/reset/xlnx-versal-resets.h>

Example:

serdes: zynqmp_phy@fd400000 {
	...

	resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
	reset-names = "sata_rst";

	...
};
