Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
---------------------------------------------------------

Required properties:
- compatible		: Should be:
			  - "xlnx,zynq-can-1.0" for Zynq CAN controllers
			  - "xlnx,axi-can-1.00.a" for Axi CAN controllers
			  - "xlnx,canfd-1.0" for CAN FD controllers
			  - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
- reg			: Physical base address and size of the controller
			  registers map.
- interrupts		: Property with a value describing the interrupt
			  number.
- clock-names		: List of input clock names
			  - "can_clk", "pclk" (For CANPS),
			  - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD).
			  (See clock bindings for details).
- clocks		: Clock phandles (see clock bindings for details).
- tx-fifo-depth		: Can Tx fifo depth (Zynq, Axi CAN).
- rx-fifo-depth		: Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
                          sequential Rx mode).
- tx-mailbox-count	: Can Tx mailbox buffer count (CAN FD).
- rx-mailbox-count	: Can Rx mailbox buffer count (CAN FD in mailbox Rx
			  mode).


Example:

For Zynq CANPS Dts file:
	zynq_can_0: can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			clocks = <&clkc 19>, <&clkc 36>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0 28 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};
For Axi CAN Dts file:
	axi_can_0: axi-can@40000000 {
			compatible = "xlnx,axi-can-1.00.a";
			clocks = <&clkc 0>, <&clkc 1>;
			clock-names = "can_clk","s_axi_aclk" ;
			reg = <0x40000000 0x10000>;
			interrupt-parent = <&intc>;
			interrupts = <0 59 1>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};
For CAN FD Dts file:
	canfd_0: canfd@40000000 {
			compatible = "xlnx,canfd-1.0";
			clocks = <&clkc 0>, <&clkc 1>;
			clock-names = "can_clk", "s_axi_aclk";
			reg = <0x40000000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <0 59 1>;
			tx-mailbox-count = <0x20>;
			rx-fifo-depth = <0x20>;
		};
