MediaTek display PWM controller

Required properties:
 - compatible: should be "mediatek,<name>-disp-pwm":
   - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
   - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
   - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
   - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
 - reg: physical base address and length of the controller's registers.
 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
   the cell format.
 - clocks: phandle and clock specifier of the PWM reference clock.
 - clock-names: must contain the following:
   - "main": clock used to generate PWM signals.
   - "mm": sync signals from the modules of mmsys.
 - pinctrl-names: Must contain a "default" entry.
 - pinctrl-0: One property must exist for each entry in pinctrl-names.
   See pinctrl/pinctrl-bindings.txt for details of the property values.

Example:
	pwm0: pwm@1401e000 {
		compatible = "mediatek,mt8173-disp-pwm",
			     "mediatek,mt6595-disp-pwm";
		reg = <0 0x1401e000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&mmsys CLK_MM_DISP_PWM026M>,
			 <&mmsys CLK_MM_DISP_PWM0MM>;
		clock-names = "main", "mm";
		pinctrl-names = "default";
		pinctrl-0 = <&disp_pwm0_pins>;
	};

	backlight_lcd: backlight_lcd {
		compatible = "pwm-backlight";
		pwms = <&pwm0 0 1000000>;
		brightness-levels = <
			  0  16  32  48  64  80  96 112
			128 144 160 176 192 208 224 240
			255
		>;
		default-brightness-level = <9>;
		power-supply = <&mt6397_vio18_reg>;
		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
	};
