Samsung Exynos SoC USB controller

The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.

EHCI
Required properties:
 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
   EHCI controller in host mode.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Optional properties:
 - samsung,vbus-gpio:  if present, specifies the GPIO that
   needs to be pulled up for the bus to be powered.

Example:

	usb@12110000 {
		compatible = "samsung,exynos4210-ehci";
		reg = <0x12110000 0x100>;
		interrupts = <0 71 0>;
		samsung,vbus-gpio = <&gpx2 6 1 3 3>;

		clocks = <&clock 285>;
		clock-names = "usbhost";

		phys = <&usb2phy 1>;
		phy-names = "host";
	};

OHCI
Required properties:
 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
   OHCI companion controller in host mode.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Example:
	usb@12120000 {
		compatible = "samsung,exynos4210-ohci";
		reg = <0x12120000 0x100>;
		interrupts = <0 71 0>;

		clocks = <&clock 285>;
		clock-names = "usbhost";

		phys = <&usb2phy 1>;
		phy-names = "host";
	};

DWC3
Required properties:
 - compatible: should be one of the following -
	       "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
					    Exynos5250/5420.
	       "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
					    Exynos5433.
	       "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
				 with 'reg' property.
 - ranges: allows valid 1:1 translation between child's address space and
	   parent's address space
 - clocks: Clock IDs array as required by the controller.
 - clock-names: Names of clocks corresponding to IDs in the clock property.
                Following clock names shall be provided for different
                compatibles:
                 - samsung,exynos5250-dwusb3: "usbdrd30",
                 - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk",
                                              "phyclk",
                 - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk",
                                           "usbdrd30_axius_clk"
 - vdd10-supply: 1.0V powr supply
 - vdd33-supply: 3.0V/3.3V power supply

Sub-nodes:
The dwc3 core should be added as subnode to Exynos dwc3 glue.
- dwc3 :
   The binding details of dwc3 can be found in:
   Documentation/devicetree/bindings/usb/snps,dwc3.yaml

Example:
	usb@12000000 {
		compatible = "samsung,exynos5250-dwusb3";
		clocks = <&clock 286>;
		clock-names = "usbdrd30";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		vdd10-supply = <&ldo11_reg>;
		vdd33-supply = <&ldo9_reg>;

		dwc3 {
			compatible = "synopsys,dwc3";
			reg = <0x12000000 0x10000>;
			interrupts = <0 72 0>;
			usb-phy = <&usb2_phy &usb3_phy>;
		};
	};
