/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_

/*
 *****************************************
 *   PSOC_GLOBAL_CONF
 *   (Prototype: GLOBAL_CONF)
 *****************************************
 */

/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800

/* PSOC_GLOBAL_CONF_BTM_FSM */
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F

/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */
#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF

/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F

/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F

/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_QSPI_SPI */
#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1

/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2

/* PSOC_GLOBAL_CONF_PRSTN */
#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_EN */
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_MASK 0x300
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_SHIFT 10
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_MASK 0xC00
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_SHIFT 12
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_MASK 0x3000
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_SHIFT 14
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_MASK 0xC000
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_SHIFT 16
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_MASK 0x30000
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_SHIFT 18
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_MASK 0xC0000

/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100

/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1

/* PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST */
#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_PHY_STABLE */
#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0
#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1

/* PSOC_GLOBAL_CONF_PRSTN_OVR */
#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4
#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10

/* PSOC_GLOBAL_CONF_ETR_FLUSH */
#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1

/* PSOC_GLOBAL_CONF_ANY_RST */
#define PSOC_GLOBAL_CONF_ANY_RST_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ANY_RST_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */
#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */
#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_SHIFT 16
#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_MASK 0x10000

/* PSOC_GLOBAL_CONF_RAZWI_INTERRUPT */
#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_SHIFT 0
#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_MASK 0x1

/* PSOC_GLOBAL_CONF_RAZWI_MASK_INFO */
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK 0x1
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT 1
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK 0x2
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT 2
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK 0x4
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT 4
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK 0x3FF0
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT 16
#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK 0xFFFF0000

/* PSOC_GLOBAL_CONF_BTL_PROT */
#define PSOC_GLOBAL_CONF_BTL_PROT_AR_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_PROT_AR_MASK 0x7
#define PSOC_GLOBAL_CONF_BTL_PROT_AW_SHIFT 4
#define PSOC_GLOBAL_CONF_BTL_PROT_AW_MASK 0x70

/* PSOC_GLOBAL_CONF_BTL_ADDR_EXT */
#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_MASK 0xFFFFF

/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1

/* PSOC_GLOBAL_CONF_RESET_DELAYS */
#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_SHIFT 0
#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_MASK 0xFFFF
#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_SHIFT 16
#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_MASK 0xFFFF0000

/* PSOC_GLOBAL_CONF_SCRATCHPAD */
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SEMAPHORE */
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */
#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0
#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */
#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPL_SOURCE */
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7

/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19
#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000

/* PSOC_GLOBAL_CONF_I2C_SLV */
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0
#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1

/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_SHIFT 0
#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_MASK 0x1

/* PSOC_GLOBAL_CONF_TRACE_ADDR */
#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0
#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0xFFFFFF

/* PSOC_GLOBAL_CONF_SMB_ALERT_CTRL */
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_MASK 0xFF
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_SHIFT 8
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_MASK 0xFF00
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_SHIFT 16
#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_MASK 0xFF0000

/* PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE */
#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL */
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_SHIFT 4
#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_MASK 0x10

/* PSOC_GLOBAL_CONF_TRACE_AXPROT */
#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_MASK 0x7

/* PSOC_GLOBAL_CONF_TRACE_AWUSER */
#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TRACE_ARUSER */
#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_BTL_STS */
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8
#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00

/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9
#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200

/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_PERIPH_INTR */
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7
#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13
#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16
#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000

/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ARC_WD_INTR */
#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_MASK 0x3

/* PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK */
#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_MASK 0x3

/* PSOC_GLOBAL_CONF_DBG_APB_CTRL */
#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_SHIFT 0
#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_MASK 0x1
#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_SHIFT 1
#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_MASK 0x2

/* PSOC_GLOBAL_CONF_SPI_DMA_BAUDR */
#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_MASK 0xFFFF

/* PSOC_GLOBAL_CONF_SPI_DMA_AWPROT */
#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_MASK 0x7

/* PSOC_GLOBAL_CONF_SPI_DMA_AWUSER */
#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_DMA_CTRL */
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_MASK 0x2
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_MASK 0x3FFF0
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_SHIFT 18
#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_MASK 0xFFFC0000

/* PSOC_GLOBAL_CONF_SPI_DMA_STATUS */
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_MASK 0x2
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_MASK 0x3FFF0

/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L */
#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H */
#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL */
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_MASK 0x10
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_SHIFT 8
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_MASK 0xFF00
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_SHIFT 16
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_MASK 0xFF0000
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_SHIFT 24
#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_MASK 0xFF000000

/* PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_MASK 0x2
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_MASK 0xFF0

/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L */
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H */
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS */
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR */
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_MASK 0x2

/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_MASK 0x2

/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_MASK 0x2

/* PSOC_GLOBAL_CONF_MSTR_IF */
#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_SHIFT 0
#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_MASK 0x1
#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_SHIFT 1
#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_MASK 0x2

/* PSOC_GLOBAL_CONF_TARGETID */
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1
#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16
#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28
#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000

/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL */
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_SHIFT 0
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_MASK 0xFF
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_SHIFT 8
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_MASK 0xFF00
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_SHIFT 16
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_MASK 0x10000

/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2 */
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_SHIFT 4
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_MASK 0xF0
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_SHIFT 8
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_MASK 0xF000
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_SHIFT 16
#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_MASK 0x10000

/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L */
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_SHIFT 1
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_MASK 0x2
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_SHIFT 2
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_MASK 0xC
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_SHIFT 4
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_MASK 0x10
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_SHIFT 5
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_MASK 0x20
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_SHIFT 6
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_MASK 0x40
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_SHIFT 7
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_MASK 0x80
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_SHIFT 8
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_MASK 0x3FFF00
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_SHIFT 22
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_MASK 0x400000
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_SHIFT 23
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_MASK 0x800000
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_SHIFT 24
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_MASK 0x1F000000
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_SHIFT 29
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_MASK 0x20000000
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_SHIFT 30
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_MASK 0xC0000000

/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H */
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_MASK 0x1
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_SHIFT 1
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_MASK 0x2
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_SHIFT 2
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_MASK 0x7C
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_SHIFT 7
#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_MASK 0x380

/* PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS */
#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8
#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00

/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1

/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4
#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10

/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1
#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2

/* PSOC_GLOBAL_CONF_MASK_REQ */
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_BSAC_CTRL */
#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_MASK 0x1
#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_SHIFT 1
#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_MASK 0x2
#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_SHIFT 4
#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_MASK 0x10
#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_SHIFT 5
#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_MASK 0x20
#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_SHIFT 6
#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_MASK 0x40
#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_SHIFT 8
#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_MASK 0x300
#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_SHIFT 10
#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_MASK 0xC00
#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_SHIFT 12
#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_MASK 0x3000

/* PSOC_GLOBAL_CONF_BSAC_ADDR */
#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_MASK 0xFFFFFFF

/* PSOC_GLOBAL_CONF_BSAC_DATA */
#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL */
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_MASK 0xFFFFFFF
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_SHIFT 28
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_MASK 0x10000000
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_SHIFT 29
#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_MASK 0x20000000

/* PSOC_GLOBAL_CONF_BSAC_POLLING_DATA */
#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_BSAC_POLLING_MASK */
#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_BTL_IMG */
#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_MASK 0x1
#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_SHIFT 1
#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_MASK 0x2
#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_SHIFT 2
#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_MASK 0x4
#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_SHIFT 4
#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_MASK 0x10
#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_SHIFT 5
#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_MASK 0x20
#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_SHIFT 6
#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_MASK 0x40
#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_SHIFT 7
#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_MASK 0x80
#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_SHIFT 8
#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100
#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_SHIFT 9
#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200
#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_SHIFT 10
#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_MASK 0x400

/* PSOC_GLOBAL_CONF_PRSTN_MASK */
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_WD_MASK */
#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_RST_SRC */
#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_SHIFT 1
#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_MASK 0x2
#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_SHIFT 2
#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_MASK 0x4
#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_SHIFT 3
#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_MASK 0x8
#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_SHIFT 4
#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_MASK 0x10
#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_SHIFT 5
#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_MASK 0x20
#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_SHIFT 6
#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_MASK 0x40
#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_SHIFT 7
#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_MASK 0x80
#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_SHIFT 8
#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100

/* PSOC_GLOBAL_CONF_BOOT_STATE */
#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL */
#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_MASK 0x1
#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_SHIFT 4
#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_MASK 0x10

/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F

/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F

/* PSOC_GLOBAL_CONF_BNK3V3_MS */
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3

/* PSOC_GLOBAL_CONF_TPC_ISO */
#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_MASK 0x1FFFFFF

/* PSOC_GLOBAL_CONF_VDEC_ISO */
#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_MASK 0x3FF

/* PSOC_GLOBAL_CONF_NIC_ISO */
#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_MASK 0xFFF

/* PSOC_GLOBAL_CONF_MME_ISO */
#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_SHIFT 0
#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_MASK 0x3F
#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_SHIFT 6
#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_MASK 0xFC0
#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_SHIFT 12
#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_MASK 0x3F000
#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_SHIFT 18
#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_MASK 0xFC0000

/* PSOC_GLOBAL_CONF_EDMA_ISO */
#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_MASK 0xFF

/* PSOC_GLOBAL_CONF_HBM_ISO */
#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_SHIFT 0
#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_MASK 0xFFF
#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_SHIFT 16
#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_MASK 0x3F0000

/* PSOC_GLOBAL_CONF_XBAR_EDGE_ISO */
#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_MASK 0xF

/* PSOC_GLOBAL_CONF_HIF_HMMU_ISO */
#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_MASK 0xFFFF

/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_MASK 0xFFF
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_SHIFT 12
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_MASK 0x7000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_SHIFT 16
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_MASK 0x10000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_SHIFT 17
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_MASK 0x20000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_SHIFT 18
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_MASK 0x40000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_SHIFT 20
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_MASK 0x3F00000

/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_MASK 0x1
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_SHIFT 4
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_MASK 0x10

/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_MASK 0x1
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_SHIFT 1
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_MASK 0x2
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_SHIFT 2
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_MASK 0x4
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_SHIFT 3
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_MASK 0x8
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_SHIFT 4
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_MASK 0x10
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_SHIFT 5
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_MASK 0x20
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_SHIFT 6
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_MASK 0x40
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_SHIFT 7
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_MASK 0x80
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_SHIFT 9
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_SHIFT 12
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_MASK 0xFFF000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_SHIFT 24
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_MASK 0x3F000000
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_SHIFT 31
#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_MASK 0x80000000

/* PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_MASK 0x1
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_SHIFT 1
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_MASK 0x2
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_SHIFT 2
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_MASK 0x4
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_SHIFT 3
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_MASK 0x8
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_SHIFT 4
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_MASK 0x10
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_SHIFT 5
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_MASK 0x20
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_SHIFT 6
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_MASK 0x40
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_SHIFT 7
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_MASK 0x80
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_SHIFT 9
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_SHIFT 16
#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_MASK 0x10000

/* PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS */
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_MASK 0x3F
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_MASK 0x1F00
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_SHIFT 16
#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_MASK 0x3F0000

/* PSOC_GLOBAL_CONF_ASIF_CORE_CFG */
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_MASK 0x1F
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_MASK 0x1F00
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_SHIFT 16
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_MASK 0xF0000
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_SHIFT 31
#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_MASK 0x80000000

/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT */
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_MASK 0xF
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_SHIFT 4
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_MASK 0xF0
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_MASK 0xF00
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_SHIFT 12
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_MASK 0xF000
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_SHIFT 16
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_MASK 0xF0000
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_SHIFT 20
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_MASK 0xF00000
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_SHIFT 24
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_MASK 0xF000000

/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR */
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_MASK 0x1
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_SHIFT 1
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_MASK 0x2
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_SHIFT 2
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_MASK 0x4
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_SHIFT 3
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_MASK 0x8
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_SHIFT 4
#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_MASK 0x10

/* PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG */
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_SHIFT 1
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_MASK 0x2
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_SHIFT 2
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_MASK 0x4
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_SHIFT 3
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_MASK 0x8
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_SHIFT 8
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_MASK 0x3FF00
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_SHIFT 20
#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_MASK 0x3FF00000

/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE */
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK */
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE */
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK */
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_PAD_DEFAULT */
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF

/* PSOC_GLOBAL_CONF_PAD_SEL */
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3

/* PSOC_GLOBAL_CONF_SMI_ACCESS_EN */
#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN */
#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_SCRAM_PERM_SEL */
#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_MASK 0xF

/* PSOC_GLOBAL_CONF_SCRAM_POLY_H3 */
#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_MASK 0x1FFFFFFF

/* PSOC_GLOBAL_CONF_CORE_MODE */
#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_EXTMEM_ID_LOC */
#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_SHIFT 24
#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_MASK 0x3F000000

/* PSOC_GLOBAL_CONF_LBW_USER_CTRL */
#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_ADC_STM_ID */
#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_MASK 0x3F

/* PSOC_GLOBAL_CONF_ADC */
#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0xF

/* PSOC_GLOBAL_CONF_ADC_INT_MASK */
#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_MASK 0xF

/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */
#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */
#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_ADC_SAMPLES */
#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_MASK 0x1F
#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_SHIFT 8
#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_MASK 0x1F00

/* PSOC_GLOBAL_CONF_ADC_TPH_CS */
#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */
#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */
#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_SHIFT 4
#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_MASK 0x30

/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */
#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_ADC_PID_SEL */
#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_MASK 0x3
#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_SHIFT 4
#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_MASK 0x30

/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */
#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF

/* PSOC_GLOBAL_CONF_ADC_CH_SEL */
#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_MASK 0xFF
#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_SHIFT 8
#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_MASK 0x300

/* PSOC_GLOBAL_CONF_ADC_WRITE_ADDR */
#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */
#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL */
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_SHIFT 1
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_MASK 0x2
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_SHIFT 12
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_MASK 0x1000
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_SHIFT 13
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_MASK 0x2000
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_SHIFT 14
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_MASK 0x4000
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_SHIFT 15
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_MASK 0x8000
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_SHIFT 16
#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_MASK 0x10000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_MASK 0x3
#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_SHIFT 4
#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_MASK 0xF0

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_SHIFT 12
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_MASK 0xFFFFF000

/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H */
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL */
#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_SHIFT 0
#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_MASK 0x1
#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_SHIFT 4
#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_MASK 0x10

/* PSOC_GLOBAL_CONF_RST_OUT_CTRL */
#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_SHIFT 0
#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_MASK 0x1

/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL */
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_MEM_CPY_STATUS */
#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_MASK 0x1

/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H */
#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L */
#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H */
#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L */
#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL2 */
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_MASK 0xFFFF
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_SHIFT 16
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_MASK 0x3F0000
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_SHIFT 24
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_MASK 0x3F000000
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_SHIFT 31
#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_MASK 0x80000000

/* PSOC_GLOBAL_CONF_MEM_CPY_CONST */
#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H */
#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L */
#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_SPLIT_CFG */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000

/* PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_MASK 0x7
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_SHIFT 8
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_MASK 0x700
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_MASK 0x70000
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_MASK 0x7000000

/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_MASK 0xFF
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_SHIFT 8
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_MASK 0xFF00
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_MASK 0xFF0000
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_MASK 0xFF000000

/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD */
#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN */
#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD */
#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN */
#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 */
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8
#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0x7FFFFF00

/* PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 */
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8
#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0xFFFFF00

/* PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_SHIFT 1
#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_MASK 0x2

/* PSOC_GLOBAL_CONF_MEM_CPY_PROT */
#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_MASK 0x7
#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_SHIFT 4
#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_MASK 0x70

/* PSOC_GLOBAL_CONF_ISOLATE_INPUTS */
#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL */
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_SHIFT 1
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_MASK 0x6
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_SHIFT 5
#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_MASK 0x60

/* PSOC_GLOBAL_CONF_ARC_JT_SEL */
#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_PLL_DUMP_CRTL */
#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_SHIFT 0
#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_MASK 0x3F
#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_SHIFT 8
#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_MASK 0xF00

/* PSOC_GLOBAL_CONF_MEM_CPY_AXUSER */
#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_BTL_AXUSER */
#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_MASK 0x3F
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_SHIFT 6
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_MASK 0xFC0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK 0xFC0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK 0x3F000000

/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_MASK 0x3F
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_SHIFT 6
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_MASK 0xFC0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_MASK 0x1000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK 0x4000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK 0xFF0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000

/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK 0xFFFF
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT 16
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK 0xFFFF0000

/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_MASK 0x7
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_SHIFT 3
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_MASK 0x38
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_SHIFT 6
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_MASK 0x1C0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_SHIFT 9
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_MASK 0xE00
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_MASK 0x7000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_SHIFT 15
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_MASK 0x38000

/* PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_MASK 0x1
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_SHIFT 4
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_MASK 0x30
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_SHIFT 8
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_SHIFT 9
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_MASK 0x1000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_SHIFT 13
#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_MASK 0x2000

/* PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_AXI_DRAIN_INTR */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_SHIFT 1
#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_MASK 0x2

/* PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK */
#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_ECO_INTR_CAUSE */
#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ECO_INTR_CLEAR */
#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_ECO_INTR_MASK */
#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_DFT_APB_CONTROL */
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_SHIFT 0
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_MASK 0x1
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_SHIFT 1
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_MASK 0xFFFE
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_SHIFT 16
#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_MASK 0xFFFF0000

#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
