Qualcomm Technologies Inc. adreno/snapdragon DSI output

DSI Controller:
Required properties:
- compatible:
  * "qcom,mdss-dsi-ctrl"
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
  * "dsi_ctrl"
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
- clock-names: the following clocks are required:
  * "mdp_core"
  * "iface"
  * "bus"
  * "core_mmss"
  * "byte"
  * "pixel"
  * "core"
  For DSIv2, we need an additional clock:
   * "src"
  For DSI6G v2.0 onwards, we need also need the clock:
   * "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
  by a DSI PHY block. See [1] for details on clock bindings.
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
- phys: phandle to DSI PHY device node
- phy-names: the name of the corresponding PHY device
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
  an endpoint subnode as defined in [2] and [3].

Optional properties:
- panel@0: Node of panel connected to this DSI controller.
  See files in [4] for each supported panel.
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
  driving a panel which needs 2 DSI links.
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
  the master link of the 2-DSI panel.
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
  driving a 2-DSI panel whose 2 links need receive command simultaneously.
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
- ports: contains DSI controller input and output ports as children, each
  containing one endpoint subnode.

  DSI Endpoint properties:
  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
    input endpoint. For port@1, set to the MDP interface output. See [2] for
    device graph info.

  - data-lanes: this describes how the physical DSI data lanes are mapped
    to the logical lanes on the given platform. The value contained in
    index n describes what physical lane is mapped to the logical lane n
    (DATAn, where n lies between 0 and 3). The clock lane position is fixed
    and can't be changed. Hence, they aren't a part of the DT bindings. See
    [3] for more info on the data-lanes property.

    For example:

    data-lanes = <3 0 1 2>;

    The above mapping describes that the logical data lane DATA0 is mapped to
    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
    to phys DATA1 and logic DATA3 to phys DATA2.

    There are only a limited number of physical to logical mappings possible:
    <0 1 2 3>
    <1 2 3 0>
    <2 3 0 1>
    <3 0 1 2>
    <0 3 2 1>
    <1 0 3 2>
    <2 1 0 3>
    <3 2 1 0>

DSI PHY:
Required properties:
- compatible: Could be the following
  * "qcom,dsi-phy-28nm-hpm"
  * "qcom,dsi-phy-28nm-lp"
  * "qcom,dsi-phy-20nm"
  * "qcom,dsi-phy-28nm-8960"
  * "qcom,dsi-phy-14nm"
  * "qcom,dsi-phy-14nm-660"
  * "qcom,dsi-phy-10nm"
  * "qcom,dsi-phy-10nm-8998"
  * "qcom,dsi-phy-7nm"
  * "qcom,dsi-phy-7nm-8150"
- reg: Physical base address and length of the registers of PLL, PHY. Some
  revisions require the PHY regulator base address, whereas others require the
  PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
  * "dsi_pll"
  * "dsi_phy"
  * "dsi_phy_regulator"
  For DSI 14nm, 10nm and 7nm PHYs:
  * "dsi_pll"
  * "dsi_phy"
  * "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
  2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
  * "iface"
  * "ref" (only required for new DTS files/entries)
  For 28nm HPM/LP, 28nm 8960 PHYs:
- vddio-supply: phandle to vdd-io regulator device node
  For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
- vcca-supply: phandle to vcca regulator device node
  For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
  For 10nm and 7nm PHY:
- vdds-supply: phandle to vdds regulator device node

Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
  regulator is wanted.
- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
					panels in microseconds. Driver uses this number to adjust
					the clock rate according to the expected transfer time.
					Increasing this value would slow down the mdp processing
					and can result in slower performance.
					Decreasing this value can speed up the mdp processing,
					but this can also impact power consumption.
					As a rule this time should not be higher than the time
					that would be expected with the processing at the
					dsi link rate since anyways this would be the maximum
					transfer time that could be achieved.
					If ping pong split is enabled, this time should not be higher
					than two times the dsi link rate time.
					If the property is not specified, then the default value is 14000 us.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
[4] Documentation/devicetree/bindings/display/panel/

Example:
	dsi0: dsi@fd922800 {
		compatible = "qcom,mdss-dsi-ctrl";
		qcom,dsi-host-index = <0>;
		interrupt-parent = <&mdp>;
		interrupts = <4 0>;
		reg-names = "dsi_ctrl";
		reg = <0xfd922800 0x200>;
		power-domains = <&mmcc MDSS_GDSC>;
		clock-names =
			"bus",
			"byte",
			"core",
			"core_mmss",
			"iface",
			"mdp_core",
			"pixel";
		clocks =
			<&mmcc MDSS_AXI_CLK>,
			<&mmcc MDSS_BYTE0_CLK>,
			<&mmcc MDSS_ESC0_CLK>,
			<&mmcc MMSS_MISC_AHB_CLK>,
			<&mmcc MDSS_AHB_CLK>,
			<&mmcc MDSS_MDP_CLK>,
			<&mmcc MDSS_PCLK0_CLK>;

		assigned-clocks =
				 <&mmcc BYTE0_CLK_SRC>,
				 <&mmcc PCLK0_CLK_SRC>;
		assigned-clock-parents =
				 <&dsi_phy0 0>,
				 <&dsi_phy0 1>;

		vdda-supply = <&pma8084_l2>;
		vdd-supply = <&pma8084_l22>;
		vddio-supply = <&pma8084_l12>;

		phys = <&dsi_phy0>;
		phy-names ="dsi-phy";

		qcom,dual-dsi-mode;
		qcom,master-dsi;
		qcom,sync-dual-dsi;

		qcom,mdss-mdp-transfer-time-us = <12000>;

		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&dsi_active>;
		pinctrl-1 = <&dsi_suspend>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				dsi0_in: endpoint {
					remote-endpoint = <&mdp_intf1_out>;
				};
			};

			port@1 {
				reg = <1>;
				dsi0_out: endpoint {
					remote-endpoint = <&panel_in>;
					data-lanes = <0 1 2 3>;
				};
			};
		};

		panel: panel@0 {
			compatible = "sharp,lq101r1sx01";
			reg = <0>;
			link2 = <&secondary>;

			power-supply = <...>;
			backlight = <...>;

			port {
				panel_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};
		};
	};

	dsi_phy0: dsi-phy@fd922a00 {
		compatible = "qcom,dsi-phy-28nm-hpm";
		qcom,dsi-phy-index = <0>;
		reg-names =
			"dsi_pll",
			"dsi_phy",
			"dsi_phy_regulator";
		reg =   <0xfd922a00 0xd4>,
			<0xfd922b00 0x2b0>,
			<0xfd922d80 0x7b>;
		clock-names = "iface";
		clocks = <&mmcc MDSS_AHB_CLK>;
		#clock-cells = <1>;
		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy-regulator-ldo-mode;
	};
