// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
 *
 * Product homepage:
 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
 */

#include <dt-bindings/leds/common.h>

#include "imx93.dtsi"

/{
	model = "PHYTEC phyCORE-i.MX93";
	compatible = "phytec,imx93-phycore-som", "fsl,imx93";

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0 0x80000000 0 0x40000000>;
			size = <0 0x10000000>;
			linux,cma-default;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_leds>;

		led-0 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_HEARTBEAT;
			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};
};

/* Ethernet */
&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
			  <&clk IMX93_CLK_ENET_REF>,
			  <&clk IMX93_CLK_ENET_REF_PHY>;
	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
	assigned-clock-rates = <100000000>, <50000000>, <50000000>;
	status = "okay";

	mdio: mdio {
		clock-frequency = <5000000>;
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

/* eMMC */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

/* Watchdog */
&wdog3 {
	status = "okay";
};

&iomuxc {
	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__ENET1_MDC			0x50e
			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x502
			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
			MX93_PAD_ENET2_RXC__ENET1_RX_ER			0x5fe
			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x50e
			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x50e
			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x50e
			MX93_PAD_ENET2_TD2__ENET1_TX_CLK		0x4000050e
		>;
	};

	pinctrl_leds: ledsgrp {
		fsl,pins = <
			MX93_PAD_I2C1_SDA__GPIO1_IO01		0x31e
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x179e
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x1386
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
		>;
	};
};
