Mediatek Video Codec

Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
supports high resolution encoding and decoding functionalities.

Required properties:
- compatible : must be one of the following string:
  "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
  "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
  "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
  "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
  "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
  "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
  "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
- reg : Physical base address of the video codec registers and length of
  memory mapped region.
- interrupts : interrupt number to the cpu.
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
  the clock-names property.
- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
  contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
  "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
  "vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
  for details.
- dma-ranges : describes the dma address range space that the codec hw access.
One of the two following nodes:
- mediatek,vpu : the node of the video processor unit, if using VPU.
- mediatek,scp : the node of the SCP unit, if using SCP.


Example:

vcodec_dec: vcodec@16000000 {
    compatible = "mediatek,mt8173-vcodec-dec";
    reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/
          <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/
          <0 0x16021000 0 0x800>,   /*VDEC_LD*/
          <0 0x16021800 0 0x800>,   /*VDEC_TOP*/
          <0 0x16022000 0 0x1000>,  /*VDEC_CM*/
          <0 0x16023000 0 0x1000>,  /*VDEC_AD*/
          <0 0x16024000 0 0x1000>,  /*VDEC_AV*/
          <0 0x16025000 0 0x1000>,  /*VDEC_PP*/
          <0 0x16026800 0 0x800>,   /*VP8_VD*/
          <0 0x16027000 0 0x800>,   /*VP6_VD*/
          <0 0x16027800 0 0x800>,   /*VP8_VL*/
          <0 0x16028400 0 0x400>;   /*VP9_VD*/
    interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
    mediatek,larb = <&larb1>;
    iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
    mediatek,vpu = <&vpu>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
    clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
             <&topckgen CLK_TOP_UNIVPLL_D2>,
             <&topckgen CLK_TOP_CCI400_SEL>,
             <&topckgen CLK_TOP_VDEC_SEL>,
             <&topckgen CLK_TOP_VCODECPLL>,
             <&apmixedsys CLK_APMIXED_VENCPLL>,
             <&topckgen CLK_TOP_VENC_LT_SEL>,
             <&topckgen CLK_TOP_VCODECPLL_370P5>;
    clock-names = "vcodecpll",
                  "univpll_d2",
                  "clk_cci400_sel",
                  "vdec_sel",
                  "vdecpll",
                  "vencpll",
                  "venc_lt_sel",
                  "vdec_bus_clk_src";
    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
                      <&topckgen CLK_TOP_CCI400_SEL>,
                      <&topckgen CLK_TOP_VDEC_SEL>,
                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
                      <&apmixedsys CLK_APMIXED_VENCPLL>;
    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
                             <&topckgen CLK_TOP_UNIVPLL_D2>,
                             <&topckgen CLK_TOP_VCODECPLL>;
    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
  };

vcodec_enc_avc: vcodec@18002000 {
    compatible = "mediatek,mt8173-vcodec-enc";
    reg = <0 0x18002000 0 0x1000>;
    interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
    iommus = <&iommu M4U_PORT_VENC_RCPU>,
             <&iommu M4U_PORT_VENC_REC>,
             <&iommu M4U_PORT_VENC_BSDMA>,
             <&iommu M4U_PORT_VENC_SV_COMV>,
             <&iommu M4U_PORT_VENC_RD_COMV>,
             <&iommu M4U_PORT_VENC_CUR_LUMA>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
             <&iommu M4U_PORT_VENC_REF_LUMA>,
             <&iommu M4U_PORT_VENC_REF_CHROMA>,
             <&iommu M4U_PORT_VENC_NBM_RDMA>,
             <&iommu M4U_PORT_VENC_NBM_WDMA>;
    mediatek,larb = <&larb3>;
    mediatek,vpu = <&vpu>;
    clocks = <&topckgen CLK_TOP_VENC_SEL>;
    clock-names = "venc_sel";
    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
  };

vcodec_enc_vp8: vcodec@19002000 {
    compatible = "mediatek,mt8173-vcodec-enc-vp8";
    reg =  <0 0x19002000 0 0x1000>;	/* VENC_LT_SYS */
    interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
    iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
    mediatek,larb = <&larb5>;
    mediatek,vpu = <&vpu>;
    clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
    clock-names = "venc_lt_sel";
    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
  };
