amdgpu_psp.c 91.2 KB
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/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Author: Huang Rui
 *
 */

#include <linux/firmware.h>
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#include <drm/drm_drv.h>
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#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "amdgpu_ucode.h"
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#include "amdgpu_xgmi.h"
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#include "soc15_common.h"
#include "psp_v3_1.h"
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#include "psp_v10_0.h"
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#include "psp_v11_0.h"
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#include "psp_v11_0_8.h"
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#include "psp_v12_0.h"
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#include "psp_v13_0.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_securedisplay.h"
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#include "amdgpu_atomfirmware.h"
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static int psp_sysfs_init(struct amdgpu_device *adev);
static void psp_sysfs_fini(struct amdgpu_device *adev);

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static int psp_load_smu_fw(struct psp_context *psp);
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static int psp_rap_terminate(struct psp_context *psp);
static int psp_securedisplay_terminate(struct psp_context *psp);
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/*
 * Due to DF Cstate management centralized to PMFW, the firmware
 * loading sequence will be updated as below:
 *   - Load KDB
 *   - Load SYS_DRV
 *   - Load tOS
 *   - Load PMFW
 *   - Setup TMR
 *   - Load other non-psp fw
 *   - Load ASD
 *   - Load XGMI/RAS/HDCP/DTM TA if any
 *
 * This new sequence is required for
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 *   - Arcturus and onwards
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 */
static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
{
	struct amdgpu_device *adev = psp->adev;

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	if (amdgpu_sriov_vf(adev)) {
		psp->pmfw_centralized_cstate_management = false;
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		return;
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	}
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	switch (adev->ip_versions[MP0_HWIP][0]) {
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	case IP_VERSION(11, 0, 0):
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	case IP_VERSION(11, 0, 4):
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	case IP_VERSION(11, 0, 5):
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	case IP_VERSION(11, 0, 7):
	case IP_VERSION(11, 0, 9):
	case IP_VERSION(11, 0, 11):
	case IP_VERSION(11, 0, 12):
	case IP_VERSION(11, 0, 13):
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	case IP_VERSION(13, 0, 0):
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	case IP_VERSION(13, 0, 2):
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		psp->pmfw_centralized_cstate_management = true;
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		break;
	default:
		psp->pmfw_centralized_cstate_management = false;
		break;
	}
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}

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static int psp_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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	struct psp_context *psp = &adev->psp;
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	switch (adev->ip_versions[MP0_HWIP][0]) {
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	case IP_VERSION(9, 0, 0):
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		psp_v3_1_set_psp_funcs(psp);
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		psp->autoload_supported = false;
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		break;
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	case IP_VERSION(10, 0, 0):
	case IP_VERSION(10, 0, 1):
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		psp_v10_0_set_psp_funcs(psp);
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		psp->autoload_supported = false;
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		break;
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	case IP_VERSION(11, 0, 2):
	case IP_VERSION(11, 0, 4):
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		psp_v11_0_set_psp_funcs(psp);
		psp->autoload_supported = false;
		break;
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	case IP_VERSION(11, 0, 0):
	case IP_VERSION(11, 0, 5):
	case IP_VERSION(11, 0, 9):
	case IP_VERSION(11, 0, 7):
	case IP_VERSION(11, 0, 11):
	case IP_VERSION(11, 5, 0):
	case IP_VERSION(11, 0, 12):
	case IP_VERSION(11, 0, 13):
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		psp_v11_0_set_psp_funcs(psp);
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		psp->autoload_supported = true;
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		break;
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	case IP_VERSION(11, 0, 3):
	case IP_VERSION(12, 0, 1):
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		psp_v12_0_set_psp_funcs(psp);
		break;
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	case IP_VERSION(13, 0, 2):
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		psp_v13_0_set_psp_funcs(psp);
		break;
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	case IP_VERSION(13, 0, 1):
	case IP_VERSION(13, 0, 3):
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	case IP_VERSION(13, 0, 5):
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	case IP_VERSION(13, 0, 8):
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		psp_v13_0_set_psp_funcs(psp);
		psp->autoload_supported = true;
		break;
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	case IP_VERSION(11, 0, 8):
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		if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
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			psp_v11_0_8_set_psp_funcs(psp);
			psp->autoload_supported = false;
		}
		break;
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	case IP_VERSION(13, 0, 0):
		psp_v13_0_set_psp_funcs(psp);
		psp->autoload_supported = true;
		break;
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	default:
		return -EINVAL;
	}

	psp->adev = adev;

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	psp_check_pmfw_centralized_cstate_management(psp);

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	return 0;
}

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void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
{
	amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
			      &mem_ctx->shared_buf);
}

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static void psp_free_shared_bufs(struct psp_context *psp)
{
	void *tmr_buf;
	void **pptr;

	/* free TMR memory buffer */
	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
	amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);

	/* free xgmi shared memory */
	psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);

	/* free ras shared memory */
	psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);

	/* free hdcp shared memory */
	psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);

	/* free dtm shared memory */
	psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);

	/* free rap shared memory */
	psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);

	/* free securedisplay shared memory */
	psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);


}

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static void psp_memory_training_fini(struct psp_context *psp)
{
	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;

	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
	kfree(ctx->sys_cache);
	ctx->sys_cache = NULL;
}

static int psp_memory_training_init(struct psp_context *psp)
{
	int ret;
	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;

	if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
		DRM_DEBUG("memory training is not supported!\n");
		return 0;
	}

	ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
	if (ctx->sys_cache == NULL) {
		DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
		ret = -ENOMEM;
		goto Err_out;
	}

	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
		  ctx->train_data_size,
		  ctx->p2c_train_data_offset,
		  ctx->c2p_train_data_offset);
	ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
	return 0;

Err_out:
	psp_memory_training_fini(psp);
	return ret;
}

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/*
 * Helper funciton to query psp runtime database entry
 *
 * @adev: amdgpu_device pointer
 * @entry_type: the type of psp runtime database entry
 * @db_entry: runtime database entry pointer
 *
 * Return false if runtime database doesn't exit or entry is invalid
 * or true if the specific database entry is found, and copy to @db_entry
 */
static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
				     enum psp_runtime_entry_type entry_type,
				     void *db_entry)
{
	uint64_t db_header_pos, db_dir_pos;
	struct psp_runtime_data_header db_header = {0};
	struct psp_runtime_data_directory db_dir = {0};
	bool ret = false;
	int i;

	db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
	db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);

	/* read runtime db header from vram */
	amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
			sizeof(struct psp_runtime_data_header), false);

	if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
		/* runtime db doesn't exist, exit */
		dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
		return false;
	}

	/* read runtime database entry from vram */
	amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
			sizeof(struct psp_runtime_data_directory), false);

	if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
		/* invalid db entry count, exit */
		dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
		return false;
	}

	/* look up for requested entry type */
	for (i = 0; i < db_dir.entry_count && !ret; i++) {
		if (db_dir.entry_list[i].entry_type == entry_type) {
			switch (entry_type) {
			case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
				if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
					/* invalid db entry size */
					dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
					return false;
				}
				/* read runtime database entry */
				amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
							  (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
				ret = true;
				break;
			default:
				ret = false;
				break;
			}
		}
	}

	return ret;
}

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static int psp_init_sriov_microcode(struct psp_context *psp)
{
	struct amdgpu_device *adev = psp->adev;
	int ret = 0;

	switch (adev->ip_versions[MP0_HWIP][0]) {
	case IP_VERSION(9, 0, 0):
		ret = psp_init_cap_microcode(psp, "vega10");
		break;
	case IP_VERSION(11, 0, 9):
		ret = psp_init_cap_microcode(psp, "navi12");
		break;
	case IP_VERSION(11, 0, 7):
		ret = psp_init_cap_microcode(psp, "sienna_cichlid");
		break;
	case IP_VERSION(13, 0, 2):
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		ret = psp_init_cap_microcode(psp, "aldebaran");
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		ret &= psp_init_ta_microcode(psp, "aldebaran");
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		break;
	default:
		BUG();
		break;
	}

	return ret;
}

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static int psp_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct psp_context *psp = &adev->psp;
	int ret;
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	struct psp_runtime_boot_cfg_entry boot_cfg_entry;
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	struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
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	psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
	if (!psp->cmd) {
		DRM_ERROR("Failed to allocate memory to command buffer!\n");
		ret = -ENOMEM;
	}

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	if (amdgpu_sriov_vf(adev))
		ret = psp_init_sriov_microcode(psp);
	else
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		ret = psp_init_microcode(psp);
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	if (ret) {
		DRM_ERROR("Failed to load psp firmware!\n");
		return ret;
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	}

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	adev->psp.xgmi_context.supports_extended_data =
		!adev->gmc.xgmi.connected_to_cpu &&
			adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);

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	memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
	if (psp_get_runtime_db_entry(adev,
				PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
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				&boot_cfg_entry)) {
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		psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
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		if ((psp->boot_cfg_bitmask) &
		    BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
			/* If psp runtime database exists, then
			 * only enable two stage memory training
			 * when TWO_STAGE_DRAM_TRAINING bit is set
			 * in runtime database */
			mem_training_ctx->enable_mem_training = true;
		}
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	} else {
		/* If psp runtime database doesn't exist or
		 * is invalid, force enable two stage memory
		 * training */
		mem_training_ctx->enable_mem_training = true;
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	}
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	if (mem_training_ctx->enable_mem_training) {
		ret = psp_memory_training_init(psp);
		if (ret) {
			DRM_ERROR("Failed to initialize memory training!\n");
			return ret;
		}

		ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
		if (ret) {
			DRM_ERROR("Failed to process memory training!\n");
			return ret;
		}
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	}

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	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
	    adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
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		ret= psp_sysfs_init(adev);
		if (ret) {
			return ret;
		}
	}

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	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
				      amdgpu_sriov_vf(adev) ?
				      AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
				      &psp->fw_pri_bo,
				      &psp->fw_pri_mc_addr,
				      &psp->fw_pri_buf);
	if (ret)
		return ret;

	ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
				      AMDGPU_GEM_DOMAIN_VRAM,
				      &psp->fence_buf_bo,
				      &psp->fence_buf_mc_addr,
				      &psp->fence_buf);
	if (ret)
		goto failed1;

	ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
				      AMDGPU_GEM_DOMAIN_VRAM,
				      &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
				      (void **)&psp->cmd_buf_mem);
	if (ret)
		goto failed2;

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	return 0;
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failed2:
	amdgpu_bo_free_kernel(&psp->fw_pri_bo,
			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
failed1:
	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
			      &psp->fence_buf_mc_addr, &psp->fence_buf);
	return ret;
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}

static int psp_sw_fini(void *handle)
{
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	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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	struct psp_context *psp = &adev->psp;
	struct psp_gfx_cmd_resp *cmd = psp->cmd;
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	psp_memory_training_fini(psp);
	if (psp->sos_fw) {
		release_firmware(psp->sos_fw);
		psp->sos_fw = NULL;
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	}
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	if (psp->asd_fw) {
		release_firmware(psp->asd_fw);
		psp->asd_fw = NULL;
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	}
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	if (psp->ta_fw) {
		release_firmware(psp->ta_fw);
		psp->ta_fw = NULL;
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	}
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	if (adev->psp.cap_fw) {
		release_firmware(psp->cap_fw);
		psp->cap_fw = NULL;
	}
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	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
	    adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
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		psp_sysfs_fini(adev);

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	kfree(cmd);
	cmd = NULL;

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	amdgpu_bo_free_kernel(&psp->fw_pri_bo,
			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
			      &psp->fence_buf_mc_addr, &psp->fence_buf);
	amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
			      (void **)&psp->cmd_buf_mem);

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	return 0;
}

int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
		 uint32_t reg_val, uint32_t mask, bool check_changed)
{
	uint32_t val;
	int i;
	struct amdgpu_device *adev = psp->adev;

483
	if (psp->adev->no_hw_access)
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		return 0;

486
	for (i = 0; i < adev->usec_timeout; i++) {
487
		val = RREG32(reg_index);
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		if (check_changed) {
			if (val != reg_val)
				return 0;
		} else {
			if ((val & mask) == reg_val)
				return 0;
		}
		udelay(1);
	}

	return -ETIME;
}

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static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
{
	switch (cmd_id) {
	case GFX_CMD_ID_LOAD_TA:
		return "LOAD_TA";
	case GFX_CMD_ID_UNLOAD_TA:
		return "UNLOAD_TA";
	case GFX_CMD_ID_INVOKE_CMD:
		return "INVOKE_CMD";
	case GFX_CMD_ID_LOAD_ASD:
		return "LOAD_ASD";
	case GFX_CMD_ID_SETUP_TMR:
		return "SETUP_TMR";
	case GFX_CMD_ID_LOAD_IP_FW:
		return "LOAD_IP_FW";
	case GFX_CMD_ID_DESTROY_TMR:
		return "DESTROY_TMR";
	case GFX_CMD_ID_SAVE_RESTORE:
		return "SAVE_RESTORE_IP_FW";
	case GFX_CMD_ID_SETUP_VMR:
		return "SETUP_VMR";
	case GFX_CMD_ID_DESTROY_VMR:
		return "DESTROY_VMR";
	case GFX_CMD_ID_PROG_REG:
		return "PROG_REG";
	case GFX_CMD_ID_GET_FW_ATTESTATION:
		return "GET_FW_ATTESTATION";
	case GFX_CMD_ID_LOAD_TOC:
		return "ID_LOAD_TOC";
	case GFX_CMD_ID_AUTOLOAD_RLC:
		return "AUTOLOAD_RLC";
	case GFX_CMD_ID_BOOT_CFG:
		return "BOOT_CFG";
	default:
		return "UNKNOWN CMD";
	}
}

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static int
psp_cmd_submit_buf(struct psp_context *psp,
		   struct amdgpu_firmware_info *ucode,
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		   struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
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{
	int ret;
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	int index, idx;
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	int timeout = 20000;
547
	bool ras_intr = false;
548
	bool skip_unsupport = false;
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550
	if (psp->adev->no_hw_access)
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		return 0;

553
	if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
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		return 0;

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	memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
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558
	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
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560
	index = atomic_inc_return(&psp->fence_value);
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	ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
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	if (ret) {
		atomic_dec(&psp->fence_value);
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		goto exit;
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	}
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	amdgpu_device_invalidate_hdp(psp->adev, NULL);
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	while (*((unsigned int *)psp->fence_buf) != index) {
		if (--timeout == 0)
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			break;
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		/*
		 * Shouldn't wait for timeout when err_event_athub occurs,
		 * because gpu reset thread triggered and lock resource should
		 * be released for psp resume sequence.
		 */
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		ras_intr = amdgpu_ras_intr_triggered();
		if (ras_intr)
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			break;
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		usleep_range(10, 100);
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		amdgpu_device_invalidate_hdp(psp->adev, NULL);
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	}
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	/* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
	skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
		psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
586

587 588
	memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));

589 590 591 592 593 594 595
	/* In some cases, psp response status is not 0 even there is no
	 * problem while the command is submitted. Some version of PSP FW
	 * doesn't write 0 to that field.
	 * So here we would like to only print a warning instead of an error
	 * during psp initialization to avoid breaking hw_init and it doesn't
	 * return -EINVAL.
	 */
596
	if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
597
		if (ucode)
598 599 600 601
			DRM_WARN("failed to load ucode %s(0x%X) ",
				  amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
		DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
			 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
602
			 psp->cmd_buf_mem->resp.status);
603 604 605 606
		/* If we load CAP FW, PSP must return 0 under SRIOV
		 * also return failure in case of timeout
		 */
		if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) {
607 608
			ret = -EINVAL;
			goto exit;
609
		}
610 611
	}

612 613 614 615 616
	if (ucode) {
		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
	}

617 618
exit:
	drm_dev_exit(idx);
619 620 621
	return ret;
}

622 623 624 625 626 627 628 629 630 631 632
static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
{
	struct psp_gfx_cmd_resp *cmd = psp->cmd;

	mutex_lock(&psp->mutex);

	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));

	return cmd;
}

633
static void release_psp_cmd_buf(struct psp_context *psp)
634 635 636 637
{
	mutex_unlock(&psp->mutex);
}

638 639
static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
				 struct psp_gfx_cmd_resp *cmd,
640
				 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
641
{
642 643 644 645
	struct amdgpu_device *adev = psp->adev;
	uint32_t size = amdgpu_bo_size(tmr_bo);
	uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);

646
	if (amdgpu_sriov_vf(psp->adev))
647 648 649
		cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
	else
		cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
650 651
	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
652
	cmd->cmd.cmd_setup_tmr.buf_size = size;
653 654 655
	cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
	cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
	cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
656 657
}

658 659 660 661 662 663 664 665 666 667 668 669 670 671
static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
				      uint64_t pri_buf_mc, uint32_t size)
{
	cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
	cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
	cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
	cmd->cmd.cmd_load_toc.toc_size = size;
}

/* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
static int psp_load_toc(struct psp_context *psp,
			uint32_t *tmr_size)
{
	int ret;
672
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
673 674

	/* Copy toc to psp firmware private buffer */
675
	psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
676

677
	psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
678 679 680 681 682

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);
	if (!ret)
		*tmr_size = psp->cmd_buf_mem->resp.tmr_size;
683

684 685
	release_psp_cmd_buf(psp);

686 687 688
	return ret;
}

689 690 691 692
/* Set up Trusted Memory Region */
static int psp_tmr_init(struct psp_context *psp)
{
	int ret;
693
	int tmr_size;
694 695
	void *tmr_buf;
	void **pptr;
696 697

	/*
698 699
	 * According to HW engineer, they prefer the TMR address be "naturally
	 * aligned" , e.g. the start address be an integer divide of TMR size.
700 701 702 703
	 *
	 * Note: this memory need be reserved till the driver
	 * uninitializes.
	 */
704
	tmr_size = PSP_TMR_SIZE(psp->adev);
705 706 707

	/* For ASICs support RLC autoload, psp will parse the toc
	 * and calculate the total size of TMR needed */
708
	if (!amdgpu_sriov_vf(psp->adev) &&
709 710
	    psp->toc.start_addr &&
	    psp->toc.size_bytes &&
711 712 713 714 715 716 717 718
	    psp->fw_pri_buf) {
		ret = psp_load_toc(psp, &tmr_size);
		if (ret) {
			DRM_ERROR("Failed to load toc\n");
			return ret;
		}
	}

719
	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
720
	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
721
				      AMDGPU_GEM_DOMAIN_VRAM,
722
				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
723 724 725 726

	return ret;
}

727 728
static bool psp_skip_tmr(struct psp_context *psp)
{
729
	switch (psp->adev->ip_versions[MP0_HWIP][0]) {
730 731 732
	case IP_VERSION(11, 0, 9):
	case IP_VERSION(11, 0, 7):
	case IP_VERSION(13, 0, 2):
733 734 735 736 737 738
		return true;
	default:
		return false;
	}
}

739 740 741
static int psp_tmr_load(struct psp_context *psp)
{
	int ret;
742
	struct psp_gfx_cmd_resp *cmd;
743

744 745 746 747 748 749
	/* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
	 * Already set up by host driver.
	 */
	if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
		return 0;

750 751
	cmd = acquire_psp_cmd_buf(psp);

752
	psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
753 754
	DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
		 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
755 756

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
757
				 psp->fence_buf_mc_addr);
758

759 760
	release_psp_cmd_buf(psp);

761 762 763
	return ret;
}

764
static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
765
				        struct psp_gfx_cmd_resp *cmd)
766 767 768 769 770 771 772 773 774 775
{
	if (amdgpu_sriov_vf(psp->adev))
		cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
	else
		cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
}

static int psp_tmr_unload(struct psp_context *psp)
{
	int ret;
776
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
777 778 779 780 781 782 783

	psp_prep_tmr_unload_cmd_buf(psp, cmd);
	DRM_INFO("free PSP TMR buffer\n");

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);

784 785
	release_psp_cmd_buf(psp);

786 787 788 789 790
	return ret;
}

static int psp_tmr_terminate(struct psp_context *psp)
{
791
	return psp_tmr_unload(psp);
792 793
}

794 795 796 797
int psp_get_fw_attestation_records_addr(struct psp_context *psp,
					uint64_t *output_ptr)
{
	int ret;
798
	struct psp_gfx_cmd_resp *cmd;
799 800 801 802 803 804 805

	if (!output_ptr)
		return -EINVAL;

	if (amdgpu_sriov_vf(psp->adev))
		return 0;

806 807
	cmd = acquire_psp_cmd_buf(psp);

808 809 810 811 812 813 814 815 816 817
	cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);

	if (!ret) {
		*output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
			      ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
	}

818 819
	release_psp_cmd_buf(psp);

820 821 822
	return ret;
}

823 824 825
static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
{
	struct psp_context *psp = &adev->psp;
826
	struct psp_gfx_cmd_resp *cmd;
827 828 829 830 831
	int ret;

	if (amdgpu_sriov_vf(adev))
		return 0;

832
	cmd = acquire_psp_cmd_buf(psp);
833 834 835 836 837 838 839 840 841 842

	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;

	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
	if (!ret) {
		*boot_cfg =
			(cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
	}

843 844
	release_psp_cmd_buf(psp);

845 846 847
	return ret;
}

848
static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
849
{
850
	int ret;
851
	struct psp_context *psp = &adev->psp;
852
	struct psp_gfx_cmd_resp *cmd;
853

854
	if (amdgpu_sriov_vf(adev))
855 856
		return 0;

857
	cmd = acquire_psp_cmd_buf(psp);
858 859 860

	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
861 862
	cmd->cmd.boot_cfg.boot_config = boot_cfg;
	cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
863

864 865 866 867 868
	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);

	release_psp_cmd_buf(psp);

	return ret;
869 870
}

871 872
static int psp_rl_load(struct amdgpu_device *adev)
{
873
	int ret;
874
	struct psp_context *psp = &adev->psp;
875
	struct psp_gfx_cmd_resp *cmd;
876

877
	if (!is_psp_fw_valid(psp->rl))
878 879
		return 0;

880 881
	cmd = acquire_psp_cmd_buf(psp);

882
	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
883
	memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
884 885 886 887

	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
888
	cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
889 890
	cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;

891 892 893 894 895
	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);

	release_psp_cmd_buf(psp);

	return ret;
896 897
}

898
static int psp_asd_initialize(struct psp_context *psp)
899 900 901
{
	int ret;

902 903 904 905
	/* If PSP version doesn't match ASD version, asd loading will be failed.
	 * add workaround to bypass it for sriov now.
	 * TODO: add version check to make it common
	 */
906
	if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
907 908
		return 0;

909 910 911
	psp->asd_context.mem_context.shared_mc_addr  = 0;
	psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
	psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
912

913
	ret = psp_ta_load(psp, &psp->asd_context);
914 915
	if (!ret)
		psp->asd_context.initialized = true;
916

917 918 919
	return ret;
}

920 921
static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
				       uint32_t session_id)
922 923
{
	cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
924
	cmd->cmd.cmd_unload_ta.session_id = session_id;
925 926
}

927
int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
928 929 930 931
{
	int ret;
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);

932
	psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
933 934 935 936 937 938 939 940 941

	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);

	release_psp_cmd_buf(psp);

	return ret;
}

static int psp_asd_terminate(struct psp_context *psp)
942 943 944 945 946 947
{
	int ret;

	if (amdgpu_sriov_vf(psp->adev))
		return 0;

948
	if (!psp->asd_context.initialized)
949 950
		return 0;

951
	ret = psp_ta_unload(psp, &psp->asd_context);
952
	if (!ret)
953
		psp->asd_context.initialized = false;
954 955 956 957

	return ret;
}

958 959 960 961 962 963 964 965 966 967 968
static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		uint32_t id, uint32_t value)
{
	cmd->cmd_id = GFX_CMD_ID_PROG_REG;
	cmd->cmd.cmd_setup_reg_prog.reg_value = value;
	cmd->cmd.cmd_setup_reg_prog.reg_id = id;
}

int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
		uint32_t value)
{
969
	struct psp_gfx_cmd_resp *cmd;
970 971 972 973 974
	int ret = 0;

	if (reg >= PSP_REG_LAST)
		return -EINVAL;

975 976
	cmd = acquire_psp_cmd_buf(psp);

977 978
	psp_prep_reg_prog_cmd_buf(cmd, reg, value);
	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
979 980
	if (ret)
		DRM_ERROR("PSP failed to program reg id %d", reg);
981

982 983
	release_psp_cmd_buf(psp);

984 985 986
	return ret;
}

987 988
static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
				     uint64_t ta_bin_mc,
989
				     struct ta_context *context)
990
{
991
	cmd->cmd_id				= context->ta_load_type;
992
	cmd->cmd.cmd_load_ta.app_phy_addr_lo 	= lower_32_bits(ta_bin_mc);
993
	cmd->cmd.cmd_load_ta.app_phy_addr_hi	= upper_32_bits(ta_bin_mc);
994
	cmd->cmd.cmd_load_ta.app_len		= context->bin_desc.size_bytes;
995

996 997 998 999 1000
	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
		lower_32_bits(context->mem_context.shared_mc_addr);
	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
		upper_32_bits(context->mem_context.shared_mc_addr);
	cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1001 1002
}

1003
int psp_ta_init_shared_buf(struct psp_context *psp,
1004
				  struct ta_mem_context *mem_ctx)
1005 1006
{
	/*
1007 1008 1009
	* Allocate 16k memory aligned to 4k from Frame Buffer (local
	* physical) for ta to host memory
	*/
1010
	return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1011
				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1012 1013 1014
				      &mem_ctx->shared_bo,
				      &mem_ctx->shared_mc_addr,
				      &mem_ctx->shared_buf);
1015 1016
}

1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
				       uint32_t ta_cmd_id,
				       struct ta_context *context)
{
	cmd->cmd_id                         = GFX_CMD_ID_INVOKE_CMD;
	cmd->cmd.cmd_invoke_cmd.session_id  = context->session_id;
	cmd->cmd.cmd_invoke_cmd.ta_cmd_id   = ta_cmd_id;

	cmd->cmd.cmd_invoke_cmd.buf.num_desc   = 1;
	cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
	cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
	cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
				     lower_32_bits(context->mem_context.shared_mc_addr);
	cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
				     upper_32_bits(context->mem_context.shared_mc_addr);
}

int psp_ta_invoke_indirect(struct psp_context *psp,
		  uint32_t ta_cmd_id,
		  struct ta_context *context)
{
	int ret;
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);

	psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);

	context->resp_status = cmd->resp.status;

	release_psp_cmd_buf(psp);

	return ret;
}

1053 1054 1055 1056
static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
				       uint32_t ta_cmd_id,
				       uint32_t session_id)
{
1057 1058 1059
	cmd->cmd_id				= GFX_CMD_ID_INVOKE_CMD;
	cmd->cmd.cmd_invoke_cmd.session_id	= session_id;
	cmd->cmd.cmd_invoke_cmd.ta_cmd_id	= ta_cmd_id;
1060 1061
}

1062
int psp_ta_invoke(struct psp_context *psp,
1063
		  uint32_t ta_cmd_id,
1064
		  struct ta_context *context)
1065 1066
{
	int ret;
1067
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1068

1069
	psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1070 1071 1072 1073

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);

1074 1075
	context->resp_status = cmd->resp.status;

1076 1077
	release_psp_cmd_buf(psp);

1078 1079 1080
	return ret;
}

1081
int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1082 1083
{
	int ret;
1084
	struct psp_gfx_cmd_resp *cmd;
1085

1086 1087
	cmd = acquire_psp_cmd_buf(psp);

1088 1089
	psp_copy_fw(psp, context->bin_desc.start_addr,
		    context->bin_desc.size_bytes);
1090

1091
	psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1092 1093 1094 1095

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);

1096 1097
	context->resp_status = cmd->resp.status;

1098
	if (!ret) {
1099
		context->session_id = cmd->resp.session_id;
1100 1101
	}

1102 1103
	release_psp_cmd_buf(psp);

1104 1105 1106
	return ret;
}

1107 1108
int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
1109
	return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1110 1111
}

1112
int psp_xgmi_terminate(struct psp_context *psp)
1113 1114
{
	int ret;
1115 1116 1117
	struct amdgpu_device *adev = psp->adev;

	/* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1118 1119
	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
	    (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1120
	     adev->gmc.xgmi.connected_to_cpu))
1121
		return 0;
1122

1123
	if (!psp->xgmi_context.context.initialized)
1124 1125
		return 0;

1126
	ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1127

1128
	psp->xgmi_context.context.initialized = false;
1129

1130
	return ret;
1131 1132
}

1133
int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1134 1135 1136 1137
{
	struct ta_xgmi_shared_memory *xgmi_cmd;
	int ret;

1138
	if (!psp->ta_fw ||
1139 1140
	    !psp->xgmi_context.context.bin_desc.size_bytes ||
	    !psp->xgmi_context.context.bin_desc.start_addr)
1141 1142
		return -ENOENT;

1143 1144 1145
	if (!load_ta)
		goto invoke;

1146
	psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1147
	psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1148

1149
	if (!psp->xgmi_context.context.initialized) {
1150
		ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1151 1152 1153 1154 1155
		if (ret)
			return ret;
	}

	/* Load XGMI TA */
1156
	ret = psp_ta_load(psp, &psp->xgmi_context.context);
1157 1158 1159
	if (!ret)
		psp->xgmi_context.context.initialized = true;
	else
1160 1161
		return ret;

1162
invoke:
1163
	/* Initialize XGMI session */
1164
	xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1165
	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1166
	xgmi_cmd->flag_extend_link_record = set_extended_data;
1167 1168 1169 1170 1171 1172 1173
	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;

	ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);

	return ret;
}

1174 1175 1176 1177 1178
int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
{
	struct ta_xgmi_shared_memory *xgmi_cmd;
	int ret;

1179
	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));

	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;

	/* Invoke xgmi ta to get hive id */
	ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
	if (ret)
		return ret;

	*hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;

	return 0;
}

int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
{
	struct ta_xgmi_shared_memory *xgmi_cmd;
	int ret;

1199
	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));

	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;

	/* Invoke xgmi ta to get the node id */
	ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
	if (ret)
		return ret;

	*node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;

	return 0;
}

1214 1215
static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
{
1216
	return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1217
		psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1218 1219
}

1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
/*
 * Chips that support extended topology information require the driver to
 * reflect topology information in the opposite direction.  This is
 * because the TA has already exceeded its link record limit and if the
 * TA holds bi-directional information, the driver would have to do
 * multiple fetches instead of just two.
 */
static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
					struct psp_xgmi_node_info node_info)
{
	struct amdgpu_device *mirror_adev;
	struct amdgpu_hive_info *hive;
	uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
	uint64_t dst_node_id = node_info.node_id;
	uint8_t dst_num_hops = node_info.num_hops;
	uint8_t dst_num_links = node_info.num_links;

	hive = amdgpu_get_xgmi_hive(psp->adev);
	list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
		struct psp_xgmi_topology_info *mirror_top_info;
		int j;

		if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
			continue;

		mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
		for (j = 0; j < mirror_top_info->num_nodes; j++) {
			if (mirror_top_info->nodes[j].node_id != src_node_id)
				continue;

			mirror_top_info->nodes[j].num_hops = dst_num_hops;
			/*
			 * prevent 0 num_links value re-reflection since reflection
			 * criteria is based on num_hops (direct or indirect).
			 *
			 */
			if (dst_num_links)
				mirror_top_info->nodes[j].num_links = dst_num_links;

			break;
		}

		break;
	}
}

1266 1267
int psp_xgmi_get_topology_info(struct psp_context *psp,
			       int number_devices,
1268 1269
			       struct psp_xgmi_topology_info *topology,
			       bool get_extended_data)
1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
{
	struct ta_xgmi_shared_memory *xgmi_cmd;
	struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
	struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
	int i;
	int ret;

	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
		return -EINVAL;

1280
	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1281
	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1282
	xgmi_cmd->flag_extend_link_record = get_extended_data;
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304

	/* Fill in the shared memory with topology information as input */
	topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
	topology_info_input->num_nodes = number_devices;

	for (i = 0; i < topology_info_input->num_nodes; i++) {
		topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
		topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
		topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
		topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
	}

	/* Invoke xgmi ta to get the topology information */
	ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
	if (ret)
		return ret;

	/* Read the output topology information from the shared memory */
	topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
	topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
	for (i = 0; i < topology->num_nodes; i++) {
1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
		/* extended data will either be 0 or equal to non-extended data */
		if (topology_info_output->nodes[i].num_hops)
			topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;

		/* non-extended data gets everything here so no need to update */
		if (!get_extended_data) {
			topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
			topology->nodes[i].is_sharing_enabled =
					topology_info_output->nodes[i].is_sharing_enabled;
			topology->nodes[i].sdma_engine =
					topology_info_output->nodes[i].sdma_engine;
		}

1318 1319
	}

1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331
	/* Invoke xgmi ta again to get the link information */
	if (psp_xgmi_peer_link_info_supported(psp)) {
		struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;

		xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;

		ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);

		if (ret)
			return ret;

		link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1332 1333 1334 1335 1336
		for (i = 0; i < topology->num_nodes; i++) {
			/* accumulate num_links on extended data */
			topology->nodes[i].num_links = get_extended_data ?
					topology->nodes[i].num_links +
							link_info_output->nodes[i].num_links :
1337
					link_info_output->nodes[i].num_links;
1338 1339 1340 1341 1342 1343

			/* reflect the topology information for bi-directionality */
			if (psp->xgmi_context.supports_extended_data &&
					get_extended_data && topology->nodes[i].num_hops)
				psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
		}
1344 1345
	}

1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
	return 0;
}

int psp_xgmi_set_topology_info(struct psp_context *psp,
			       int number_devices,
			       struct psp_xgmi_topology_info *topology)
{
	struct ta_xgmi_shared_memory *xgmi_cmd;
	struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
	int i;

	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
		return -EINVAL;

1360
	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));

	topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
	topology_info_input->num_nodes = number_devices;

	for (i = 0; i < topology_info_input->num_nodes; i++) {
		topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
		topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
		topology_info_input->nodes[i].is_sharing_enabled = 1;
		topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
	}

	/* Invoke xgmi ta to set topology information */
	return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
}

1378
// ras begin
1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
static void psp_ras_ta_check_status(struct psp_context *psp)
{
	struct ta_ras_shared_memory *ras_cmd =
		(struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;

	switch (ras_cmd->ras_status) {
	case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
		dev_warn(psp->adev->dev,
				"RAS WARNING: cmd failed due to unsupported ip\n");
		break;
1389 1390 1391 1392
	case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
		dev_warn(psp->adev->dev,
				"RAS WARNING: cmd failed due to unsupported error injection\n");
		break;
1393 1394
	case TA_RAS_STATUS__SUCCESS:
		break;
1395 1396 1397 1398 1399
	case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
		if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
			dev_warn(psp->adev->dev,
					"RAS WARNING: Inject error to critical region is not allowed\n");
		break;
1400 1401 1402 1403 1404 1405 1406
	default:
		dev_warn(psp->adev->dev,
				"RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
		break;
	}
}

1407 1408
int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
1409 1410 1411
	struct ta_ras_shared_memory *ras_cmd;
	int ret;

1412
	ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1413

1414 1415 1416 1417 1418 1419
	/*
	 * TODO: bypass the loading in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1420
	ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1421

1422 1423 1424
	if (amdgpu_ras_intr_triggered())
		return ret;

1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
	if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
	{
		DRM_WARN("RAS: Unsupported Interface");
		return -EINVAL;
	}

	if (!ret) {
		if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
			dev_warn(psp->adev->dev, "ECC switch disabled\n");

			ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
		}
		else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
			dev_warn(psp->adev->dev,
				 "RAS internal register access blocked\n");
1440

1441
		psp_ras_ta_check_status(psp);
1442 1443 1444
	}

	return ret;
1445 1446 1447 1448 1449 1450 1451 1452
}

int psp_ras_enable_features(struct psp_context *psp,
		union ta_ras_cmd_input *info, bool enable)
{
	struct ta_ras_shared_memory *ras_cmd;
	int ret;

1453
	if (!psp->ras_context.context.initialized)
1454 1455
		return -EINVAL;

1456
	ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));

	if (enable)
		ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
	else
		ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;

	ras_cmd->ras_in_message = *info;

	ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
	if (ret)
		return -EINVAL;

1470
	return 0;
1471 1472
}

1473
int psp_ras_terminate(struct psp_context *psp)
1474 1475 1476
{
	int ret;

1477 1478 1479 1480 1481 1482
	/*
	 * TODO: bypass the terminate in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1483
	if (!psp->ras_context.context.initialized)
1484 1485
		return 0;

1486
	ret = psp_ta_unload(psp, &psp->ras_context.context);
1487

1488
	psp->ras_context.context.initialized = false;
1489

1490
	return ret;
1491 1492 1493 1494 1495
}

static int psp_ras_initialize(struct psp_context *psp)
{
	int ret;
1496 1497
	uint32_t boot_cfg = 0xFF;
	struct amdgpu_device *adev = psp->adev;
1498
	struct ta_ras_shared_memory *ras_cmd;
1499

1500 1501 1502
	/*
	 * TODO: bypass the initialize in sriov for now
	 */
1503
	if (amdgpu_sriov_vf(adev))
1504 1505
		return 0;

1506 1507
	if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
	    !adev->psp.ras_context.context.bin_desc.start_addr) {
1508
		dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1509 1510 1511
		return 0;
	}

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552
	if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
		/* query GECC enablement status from boot config
		 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
		 */
		ret = psp_boot_config_get(adev, &boot_cfg);
		if (ret)
			dev_warn(adev->dev, "PSP get boot config failed\n");

		if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
			if (!boot_cfg) {
				dev_info(adev->dev, "GECC is disabled\n");
			} else {
				/* disable GECC in next boot cycle if ras is
				 * disabled by module parameter amdgpu_ras_enable
				 * and/or amdgpu_ras_mask, or boot_config_get call
				 * is failed
				 */
				ret = psp_boot_config_set(adev, 0);
				if (ret)
					dev_warn(adev->dev, "PSP set boot config failed\n");
				else
					dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
						 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
			}
		} else {
			if (1 == boot_cfg) {
				dev_info(adev->dev, "GECC is enabled\n");
			} else {
				/* enable GECC in next boot cycle if it is disabled
				 * in boot config, or force enable GECC if failed to
				 * get boot configuration
				 */
				ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
				if (ret)
					dev_warn(adev->dev, "PSP set boot config failed\n");
				else
					dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
			}
		}
	}

1553
	psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1554
	psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1555

1556
	if (!psp->ras_context.context.initialized) {
1557
		ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1558 1559 1560 1561
		if (ret)
			return ret;
	}

1562 1563 1564
	ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));

1565
	if (amdgpu_ras_is_poison_mode_supported(adev))
1566
		ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1567
	if (!adev->gmc.xgmi.connected_to_cpu)
1568 1569
		ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;

1570
	ret = psp_ta_load(psp, &psp->ras_context.context);
1571

1572 1573 1574 1575 1576 1577 1578 1579 1580
	if (!ret && !ras_cmd->ras_status)
		psp->ras_context.context.initialized = true;
	else {
		if (ras_cmd->ras_status)
			dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
		amdgpu_ras_fini(psp->adev);
	}

	return ret;
1581
}
1582 1583 1584 1585 1586 1587 1588

int psp_ras_trigger_error(struct psp_context *psp,
			  struct ta_ras_trigger_error_input *info)
{
	struct ta_ras_shared_memory *ras_cmd;
	int ret;

1589
	if (!psp->ras_context.context.initialized)
1590 1591
		return -EINVAL;

1592
	ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606
	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));

	ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
	ras_cmd->ras_in_message.trigger_error = *info;

	ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
	if (ret)
		return -EINVAL;

	/* If err_event_athub occurs error inject was successful, however
	   return status from TA is no long reliable */
	if (amdgpu_ras_intr_triggered())
		return 0;

1607 1608 1609
	if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
		return -EACCES;
	else if (ras_cmd->ras_status)
1610 1611 1612
		return -EINVAL;

	return 0;
1613
}
1614 1615
// ras end

1616 1617 1618 1619 1620
// HDCP start
static int psp_hdcp_initialize(struct psp_context *psp)
{
	int ret;

1621 1622 1623 1624 1625 1626
	/*
	 * TODO: bypass the initialize in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1627 1628
	if (!psp->hdcp_context.context.bin_desc.size_bytes ||
	    !psp->hdcp_context.context.bin_desc.start_addr) {
1629
		dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1630 1631 1632
		return 0;
	}

1633
	psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1634
	psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1635

1636
	if (!psp->hdcp_context.context.initialized) {
1637
		ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1638 1639 1640 1641
		if (ret)
			return ret;
	}

1642
	ret = psp_ta_load(psp, &psp->hdcp_context.context);
1643 1644 1645 1646
	if (!ret) {
		psp->hdcp_context.context.initialized = true;
		mutex_init(&psp->hdcp_context.mutex);
	}
1647

1648
	return ret;
1649 1650 1651 1652 1653 1654 1655 1656 1657 1658
}

int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
	/*
	 * TODO: bypass the loading in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1659
	return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1660 1661 1662 1663 1664 1665
}

static int psp_hdcp_terminate(struct psp_context *psp)
{
	int ret;

1666 1667 1668 1669 1670 1671
	/*
	 * TODO: bypass the terminate in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1672 1673
	if (!psp->hdcp_context.context.initialized)
		return 0;
1674

1675
	ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1676

1677
	psp->hdcp_context.context.initialized = false;
1678

1679
	return ret;
1680 1681 1682
}
// HDCP end

1683 1684 1685 1686 1687
// DTM start
static int psp_dtm_initialize(struct psp_context *psp)
{
	int ret;

1688 1689 1690 1691 1692 1693
	/*
	 * TODO: bypass the initialize in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1694 1695
	if (!psp->dtm_context.context.bin_desc.size_bytes ||
	    !psp->dtm_context.context.bin_desc.start_addr) {
1696
		dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1697 1698 1699
		return 0;
	}

1700
	psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1701
	psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1702

1703
	if (!psp->dtm_context.context.initialized) {
1704
		ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1705 1706 1707 1708
		if (ret)
			return ret;
	}

1709
	ret = psp_ta_load(psp, &psp->dtm_context.context);
1710 1711 1712 1713
	if (!ret) {
		psp->dtm_context.context.initialized = true;
		mutex_init(&psp->dtm_context.mutex);
	}
1714

1715
	return ret;
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
}

int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
	/*
	 * TODO: bypass the loading in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1726
	return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1727 1728 1729 1730 1731 1732
}

static int psp_dtm_terminate(struct psp_context *psp)
{
	int ret;

1733 1734 1735 1736 1737 1738
	/*
	 * TODO: bypass the terminate in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1739 1740
	if (!psp->dtm_context.context.initialized)
		return 0;
1741

1742
	ret = psp_ta_unload(psp, &psp->dtm_context.context);
1743

1744
	psp->dtm_context.context.initialized = false;
1745

1746
	return ret;
1747 1748 1749
}
// DTM end

1750 1751 1752 1753
// RAP start
static int psp_rap_initialize(struct psp_context *psp)
{
	int ret;
1754
	enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1755 1756 1757 1758 1759 1760 1761

	/*
	 * TODO: bypass the initialize in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1762 1763
	if (!psp->rap_context.context.bin_desc.size_bytes ||
	    !psp->rap_context.context.bin_desc.start_addr) {
1764 1765 1766 1767
		dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
		return 0;
	}

1768
	psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1769
	psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1770

1771
	if (!psp->rap_context.context.initialized) {
1772
		ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1773 1774 1775 1776
		if (ret)
			return ret;
	}

1777
	ret = psp_ta_load(psp, &psp->rap_context.context);
1778 1779 1780 1781
	if (!ret) {
		psp->rap_context.context.initialized = true;
		mutex_init(&psp->rap_context.mutex);
	} else
1782 1783
		return ret;

1784 1785
	ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
	if (ret || status != TA_RAP_STATUS__SUCCESS) {
1786
		psp_rap_terminate(psp);
1787 1788
		/* free rap shared memory */
		psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1789

1790 1791 1792 1793
		dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
			 ret, status);

		return ret;
1794 1795 1796 1797 1798 1799 1800 1801 1802
	}

	return 0;
}

static int psp_rap_terminate(struct psp_context *psp)
{
	int ret;

1803
	if (!psp->rap_context.context.initialized)
1804 1805
		return 0;

1806
	ret = psp_ta_unload(psp, &psp->rap_context.context);
1807

1808
	psp->rap_context.context.initialized = false;
1809 1810 1811 1812

	return ret;
}

1813
int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1814 1815
{
	struct ta_rap_shared_memory *rap_cmd;
1816
	int ret = 0;
1817

1818
	if (!psp->rap_context.context.initialized)
1819
		return 0;
1820 1821 1822 1823 1824 1825 1826 1827

	if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
	    ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
		return -EINVAL;

	mutex_lock(&psp->rap_context.mutex);

	rap_cmd = (struct ta_rap_shared_memory *)
1828
		  psp->rap_context.context.mem_context.shared_buf;
1829 1830 1831 1832 1833
	memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));

	rap_cmd->cmd_id = ta_cmd_id;
	rap_cmd->validation_method_id = METHOD_A;

1834
	ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1835 1836 1837 1838 1839
	if (ret)
		goto out_unlock;

	if (status)
		*status = rap_cmd->rap_status;
1840

1841
out_unlock:
1842 1843
	mutex_unlock(&psp->rap_context.mutex);

1844
	return ret;
1845 1846 1847
}
// RAP end

1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
/* securedisplay start */
static int psp_securedisplay_initialize(struct psp_context *psp)
{
	int ret;
	struct securedisplay_cmd *securedisplay_cmd;

	/*
	 * TODO: bypass the initialize in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1860 1861
	if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
	    !psp->securedisplay_context.context.bin_desc.start_addr) {
1862 1863 1864 1865
		dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
		return 0;
	}

1866 1867
	psp->securedisplay_context.context.mem_context.shared_mem_size =
		PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1868
	psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1869

1870
	if (!psp->securedisplay_context.context.initialized) {
1871 1872
		ret = psp_ta_init_shared_buf(psp,
					     &psp->securedisplay_context.context.mem_context);
1873 1874 1875 1876
		if (ret)
			return ret;
	}

1877
	ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1878 1879 1880 1881
	if (!ret) {
		psp->securedisplay_context.context.initialized = true;
		mutex_init(&psp->securedisplay_context.mutex);
	} else
1882 1883 1884 1885 1886 1887 1888
		return ret;

	psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
			TA_SECUREDISPLAY_COMMAND__QUERY_TA);

	ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
	if (ret) {
1889
		psp_securedisplay_terminate(psp);
1890 1891
		/* free securedisplay shared memory */
		psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914
		dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
		return -EINVAL;
	}

	if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
		psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
		dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
			securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
	}

	return 0;
}

static int psp_securedisplay_terminate(struct psp_context *psp)
{
	int ret;

	/*
	 * TODO:bypass the terminate in sriov for now
	 */
	if (amdgpu_sriov_vf(psp->adev))
		return 0;

1915
	if (!psp->securedisplay_context.context.initialized)
1916 1917
		return 0;

1918
	ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1919

1920
	psp->securedisplay_context.context.initialized = false;
1921 1922 1923 1924 1925 1926 1927 1928

	return ret;
}

int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
	int ret;

1929
	if (!psp->securedisplay_context.context.initialized)
1930 1931 1932 1933 1934 1935 1936 1937
		return -EINVAL;

	if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
	    ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
		return -EINVAL;

	mutex_lock(&psp->securedisplay_context.mutex);

1938
	ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1939 1940 1941 1942 1943 1944 1945

	mutex_unlock(&psp->securedisplay_context.mutex);

	return ret;
}
/* SECUREDISPLAY end */

1946
static int psp_hw_start(struct psp_context *psp)
1947
{
1948
	struct amdgpu_device *adev = psp->adev;
1949 1950
	int ret;

1951
	if (!amdgpu_sriov_vf(adev)) {
1952
		if ((is_psp_fw_valid(psp->kdb)) &&
1953 1954 1955 1956
		    (psp->funcs->bootloader_load_kdb != NULL)) {
			ret = psp_bootloader_load_kdb(psp);
			if (ret) {
				DRM_ERROR("PSP load kdb failed!\n");
1957 1958 1959 1960
				return ret;
			}
		}

1961 1962
		if ((is_psp_fw_valid(psp->spl)) &&
		    (psp->funcs->bootloader_load_spl != NULL)) {
1963 1964 1965
			ret = psp_bootloader_load_spl(psp);
			if (ret) {
				DRM_ERROR("PSP load spl failed!\n");
1966 1967 1968 1969
				return ret;
			}
		}

1970 1971 1972 1973
		if ((is_psp_fw_valid(psp->sys)) &&
		    (psp->funcs->bootloader_load_sysdrv != NULL)) {
			ret = psp_bootloader_load_sysdrv(psp);
			if (ret) {
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
				DRM_ERROR("PSP load sys drv failed!\n");
				return ret;
			}
		}

		if ((is_psp_fw_valid(psp->soc_drv)) &&
		    (psp->funcs->bootloader_load_soc_drv != NULL)) {
			ret = psp_bootloader_load_soc_drv(psp);
			if (ret) {
				DRM_ERROR("PSP load soc drv failed!\n");
				return ret;
			}
		}

		if ((is_psp_fw_valid(psp->intf_drv)) &&
		    (psp->funcs->bootloader_load_intf_drv != NULL)) {
			ret = psp_bootloader_load_intf_drv(psp);
			if (ret) {
				DRM_ERROR("PSP load intf drv failed!\n");
				return ret;
			}
		}

		if ((is_psp_fw_valid(psp->dbg_drv)) &&
		    (psp->funcs->bootloader_load_dbg_drv != NULL)) {
			ret = psp_bootloader_load_dbg_drv(psp);
			if (ret) {
				DRM_ERROR("PSP load dbg drv failed!\n");
2002 2003
				return ret;
			}
2004
		}
2005

2006 2007 2008 2009 2010 2011 2012
		if ((is_psp_fw_valid(psp->sos)) &&
		    (psp->funcs->bootloader_load_sos != NULL)) {
			ret = psp_bootloader_load_sos(psp);
			if (ret) {
				DRM_ERROR("PSP load sos failed!\n");
				return ret;
			}
2013
		}
2014
	}
2015

2016
	ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2017 2018
	if (ret) {
		DRM_ERROR("PSP create ring failed!\n");
2019
		return ret;
2020
	}
2021

2022 2023 2024
	if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
		goto skip_pin_bo;

2025 2026 2027 2028 2029 2030
	ret = psp_tmr_init(psp);
	if (ret) {
		DRM_ERROR("PSP tmr init failed!\n");
		return ret;
	}

2031
skip_pin_bo:
2032
	/*
2033
	 * For ASICs with DF Cstate management centralized
2034 2035 2036
	 * to PMFW, TMR setup should be performed after PMFW
	 * loaded and before other non-psp firmware loaded.
	 */
2037 2038 2039
	if (psp->pmfw_centralized_cstate_management) {
		ret = psp_load_smu_fw(psp);
		if (ret)
2040
			return ret;
2041 2042 2043 2044 2045 2046
	}

	ret = psp_tmr_load(psp);
	if (ret) {
		DRM_ERROR("PSP load tmr failed!\n");
		return ret;
2047
	}
2048

2049 2050 2051
	return 0;
}

2052 2053 2054 2055
static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
			   enum psp_gfx_fw_type *type)
{
	switch (ucode->ucode_id) {
2056 2057 2058
	case AMDGPU_UCODE_ID_CAP:
		*type = GFX_FW_TYPE_CAP;
		break;
2059 2060 2061 2062 2063 2064
	case AMDGPU_UCODE_ID_SDMA0:
		*type = GFX_FW_TYPE_SDMA0;
		break;
	case AMDGPU_UCODE_ID_SDMA1:
		*type = GFX_FW_TYPE_SDMA1;
		break;
2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082
	case AMDGPU_UCODE_ID_SDMA2:
		*type = GFX_FW_TYPE_SDMA2;
		break;
	case AMDGPU_UCODE_ID_SDMA3:
		*type = GFX_FW_TYPE_SDMA3;
		break;
	case AMDGPU_UCODE_ID_SDMA4:
		*type = GFX_FW_TYPE_SDMA4;
		break;
	case AMDGPU_UCODE_ID_SDMA5:
		*type = GFX_FW_TYPE_SDMA5;
		break;
	case AMDGPU_UCODE_ID_SDMA6:
		*type = GFX_FW_TYPE_SDMA6;
		break;
	case AMDGPU_UCODE_ID_SDMA7:
		*type = GFX_FW_TYPE_SDMA7;
		break;
2083 2084 2085 2086 2087 2088
	case AMDGPU_UCODE_ID_CP_MES:
		*type = GFX_FW_TYPE_CP_MES;
		break;
	case AMDGPU_UCODE_ID_CP_MES_DATA:
		*type = GFX_FW_TYPE_MES_STACK;
		break;
2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121
	case AMDGPU_UCODE_ID_CP_CE:
		*type = GFX_FW_TYPE_CP_CE;
		break;
	case AMDGPU_UCODE_ID_CP_PFP:
		*type = GFX_FW_TYPE_CP_PFP;
		break;
	case AMDGPU_UCODE_ID_CP_ME:
		*type = GFX_FW_TYPE_CP_ME;
		break;
	case AMDGPU_UCODE_ID_CP_MEC1:
		*type = GFX_FW_TYPE_CP_MEC;
		break;
	case AMDGPU_UCODE_ID_CP_MEC1_JT:
		*type = GFX_FW_TYPE_CP_MEC_ME1;
		break;
	case AMDGPU_UCODE_ID_CP_MEC2:
		*type = GFX_FW_TYPE_CP_MEC;
		break;
	case AMDGPU_UCODE_ID_CP_MEC2_JT:
		*type = GFX_FW_TYPE_CP_MEC_ME2;
		break;
	case AMDGPU_UCODE_ID_RLC_G:
		*type = GFX_FW_TYPE_RLC_G;
		break;
	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
		break;
	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
		break;
	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
		break;
2122 2123 2124 2125 2126 2127
	case AMDGPU_UCODE_ID_RLC_IRAM:
		*type = GFX_FW_TYPE_RLC_IRAM;
		break;
	case AMDGPU_UCODE_ID_RLC_DRAM:
		*type = GFX_FW_TYPE_RLC_DRAM_BOOT;
		break;
2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142
	case AMDGPU_UCODE_ID_SMC:
		*type = GFX_FW_TYPE_SMU;
		break;
	case AMDGPU_UCODE_ID_UVD:
		*type = GFX_FW_TYPE_UVD;
		break;
	case AMDGPU_UCODE_ID_UVD1:
		*type = GFX_FW_TYPE_UVD1;
		break;
	case AMDGPU_UCODE_ID_VCE:
		*type = GFX_FW_TYPE_VCE;
		break;
	case AMDGPU_UCODE_ID_VCN:
		*type = GFX_FW_TYPE_VCN;
		break;
2143 2144 2145
	case AMDGPU_UCODE_ID_VCN1:
		*type = GFX_FW_TYPE_VCN1;
		break;
2146 2147 2148 2149 2150 2151
	case AMDGPU_UCODE_ID_DMCU_ERAM:
		*type = GFX_FW_TYPE_DMCU_ERAM;
		break;
	case AMDGPU_UCODE_ID_DMCU_INTV:
		*type = GFX_FW_TYPE_DMCU_ISR;
		break;
2152 2153 2154 2155 2156 2157
	case AMDGPU_UCODE_ID_VCN0_RAM:
		*type = GFX_FW_TYPE_VCN0_RAM;
		break;
	case AMDGPU_UCODE_ID_VCN1_RAM:
		*type = GFX_FW_TYPE_VCN1_RAM;
		break;
2158 2159 2160
	case AMDGPU_UCODE_ID_DMCUB:
		*type = GFX_FW_TYPE_DMUB;
		break;
2161 2162 2163 2164 2165 2166 2167 2168
	case AMDGPU_UCODE_ID_MAXIMUM:
	default:
		return -EINVAL;
	}

	return 0;
}

2169 2170 2171 2172
static void psp_print_fw_hdr(struct psp_context *psp,
			     struct amdgpu_firmware_info *ucode)
{
	struct amdgpu_device *adev = psp->adev;
2173
	struct common_firmware_header *hdr;
2174 2175 2176 2177 2178 2179 2180 2181 2182 2183

	switch (ucode->ucode_id) {
	case AMDGPU_UCODE_ID_SDMA0:
	case AMDGPU_UCODE_ID_SDMA1:
	case AMDGPU_UCODE_ID_SDMA2:
	case AMDGPU_UCODE_ID_SDMA3:
	case AMDGPU_UCODE_ID_SDMA4:
	case AMDGPU_UCODE_ID_SDMA5:
	case AMDGPU_UCODE_ID_SDMA6:
	case AMDGPU_UCODE_ID_SDMA7:
2184 2185 2186
		hdr = (struct common_firmware_header *)
			adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
		amdgpu_ucode_print_sdma_hdr(hdr);
2187 2188
		break;
	case AMDGPU_UCODE_ID_CP_CE:
2189 2190
		hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
		amdgpu_ucode_print_gfx_hdr(hdr);
2191 2192
		break;
	case AMDGPU_UCODE_ID_CP_PFP:
2193 2194
		hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
		amdgpu_ucode_print_gfx_hdr(hdr);
2195 2196
		break;
	case AMDGPU_UCODE_ID_CP_ME:
2197 2198
		hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
		amdgpu_ucode_print_gfx_hdr(hdr);
2199 2200
		break;
	case AMDGPU_UCODE_ID_CP_MEC1:
2201 2202
		hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
		amdgpu_ucode_print_gfx_hdr(hdr);
2203 2204
		break;
	case AMDGPU_UCODE_ID_RLC_G:
2205 2206
		hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
		amdgpu_ucode_print_rlc_hdr(hdr);
2207 2208
		break;
	case AMDGPU_UCODE_ID_SMC:
2209 2210
		hdr = (struct common_firmware_header *)adev->pm.fw->data;
		amdgpu_ucode_print_smc_hdr(hdr);
2211 2212 2213 2214 2215 2216
		break;
	default:
		break;
	}
}

2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234
static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
				       struct psp_gfx_cmd_resp *cmd)
{
	int ret;
	uint64_t fw_mem_mc_addr = ucode->mc_addr;

	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;

	ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
	if (ret)
		DRM_ERROR("Unknown firmware type\n");

	return ret;
}

2235
static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2236
			          struct amdgpu_firmware_info *ucode)
2237 2238
{
	int ret = 0;
2239
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2240

2241 2242 2243 2244 2245
	ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
	if (!ret) {
		ret = psp_cmd_submit_buf(psp, ucode, cmd,
					 psp->fence_buf_mc_addr);
	}
2246

2247
	release_psp_cmd_buf(psp);
2248 2249 2250 2251

	return ret;
}

2252 2253 2254
static int psp_load_smu_fw(struct psp_context *psp)
{
	int ret;
2255
	struct amdgpu_device *adev = psp->adev;
2256
	struct amdgpu_firmware_info *ucode =
2257
			&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2258
	struct amdgpu_ras *ras = psp->ras_context.ras;
2259 2260 2261 2262

	if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
		return 0;

2263
	if ((amdgpu_in_reset(adev) &&
2264
	     ras && adev->ras_enabled &&
2265 2266
	     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
	      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2267 2268 2269 2270 2271 2272
		ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
		if (ret) {
			DRM_WARN("Failed to set MP1 state prepare for reload\n");
		}
	}

2273
	ret = psp_execute_non_psp_fw_load(psp, ucode);
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318

	if (ret)
		DRM_ERROR("PSP load smu failed!\n");

	return ret;
}

static bool fw_load_skip_check(struct psp_context *psp,
			       struct amdgpu_firmware_info *ucode)
{
	if (!ucode->fw)
		return true;

	if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
	    (psp_smu_reload_quirk(psp) ||
	     psp->autoload_supported ||
	     psp->pmfw_centralized_cstate_management))
		return true;

	if (amdgpu_sriov_vf(psp->adev) &&
	   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
	    || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
		/*skip ucode loading in SRIOV VF */
		return true;

	if (psp->autoload_supported &&
	    (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
	     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
		/* skip mec JT when autoload is enabled */
		return true;

	return false;
}

2319 2320 2321 2322 2323 2324 2325 2326 2327
int psp_load_fw_list(struct psp_context *psp,
		     struct amdgpu_firmware_info **ucode_list, int ucode_count)
{
	int ret = 0, i;
	struct amdgpu_firmware_info *ucode;

	for (i = 0; i < ucode_count; ++i) {
		ucode = ucode_list[i];
		psp_print_fw_hdr(psp, ucode);
2328
		ret = psp_execute_non_psp_fw_load(psp, ucode);
2329 2330 2331 2332 2333 2334
		if (ret)
			return ret;
	}
	return ret;
}

2335
static int psp_load_non_psp_fw(struct psp_context *psp)
2336 2337
{
	int i, ret;
2338
	struct amdgpu_firmware_info *ucode;
2339
	struct amdgpu_device *adev = psp->adev;
2340

2341 2342 2343
	if (psp->autoload_supported &&
	    !psp->pmfw_centralized_cstate_management) {
		ret = psp_load_smu_fw(psp);
2344 2345 2346 2347
		if (ret)
			return ret;
	}

2348 2349 2350 2351
	for (i = 0; i < adev->firmware.max_ucodes; i++) {
		ucode = &adev->firmware.ucode[i];

		if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2352 2353 2354 2355
		    !fw_load_skip_check(psp, ucode)) {
			ret = psp_load_smu_fw(psp);
			if (ret)
				return ret;
2356
			continue;
2357
		}
2358

2359
		if (fw_load_skip_check(psp, ucode))
2360
			continue;
2361

2362
		if (psp->autoload_supported &&
2363 2364 2365
		    (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
		     adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
		     adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2366 2367 2368 2369 2370 2371 2372
		    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
			/* PSP only receive one SDMA fw for sienna_cichlid,
			 * as all four sdma fw are same */
			continue;

2373 2374
		psp_print_fw_hdr(psp, ucode);

2375
		ret = psp_execute_non_psp_fw_load(psp, ucode);
2376
		if (ret)
2377
			return ret;
2378

2379
		/* Start rlc autoload after psp recieved all the gfx firmware */
2380
		if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2381
		    AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2382
			ret = psp_rlc_autoload_start(psp);
2383 2384 2385 2386 2387
			if (ret) {
				DRM_ERROR("Failed to start rlc autoload\n");
				return ret;
			}
		}
2388 2389
	}

2390 2391 2392 2393 2394 2395
	return 0;
}

static int psp_load_fw(struct amdgpu_device *adev)
{
	int ret;
2396 2397
	struct psp_context *psp = &adev->psp;

2398
	if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2399 2400
		/* should not destroy ring, only stop */
		psp_ring_stop(psp, PSP_RING_TYPE__KM);
2401
	} else {
2402
		memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2403

2404 2405 2406 2407 2408
		ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
		if (ret) {
			DRM_ERROR("PSP ring init failed!\n");
			goto failed;
		}
2409
	}
2410

2411
	ret = psp_hw_start(psp);
2412
	if (ret)
2413
		goto failed;
2414

2415
	ret = psp_load_non_psp_fw(psp);
2416
	if (ret)
2417
		goto failed1;
2418

2419
	ret = psp_asd_initialize(psp);
2420 2421
	if (ret) {
		DRM_ERROR("PSP load asd failed!\n");
2422
		goto failed1;
2423 2424
	}

2425 2426 2427
	ret = psp_rl_load(adev);
	if (ret) {
		DRM_ERROR("PSP load RL failed!\n");
2428
		goto failed1;
2429 2430
	}

2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442
	if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
		if (adev->gmc.xgmi.num_physical_nodes > 1) {
			ret = psp_xgmi_initialize(psp, false, true);
			/* Warning the XGMI seesion initialize failure
			* Instead of stop driver initialization
			*/
			if (ret)
				dev_err(psp->adev->dev,
					"XGMI: Failed to initialize XGMI session\n");
		}
	}

2443
	if (psp->ta_fw) {
2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457
		ret = psp_ras_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
					"RAS: Failed to initialize RAS\n");

		ret = psp_hdcp_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"HDCP: Failed to initialize HDCP\n");

		ret = psp_dtm_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"DTM: Failed to initialize DTM\n");
2458 2459 2460 2461 2462

		ret = psp_rap_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"RAP: Failed to initialize RAP\n");
2463 2464 2465 2466 2467

		ret = psp_securedisplay_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2468 2469
	}

2470 2471
	return 0;

2472 2473
failed1:
	psp_free_shared_bufs(psp);
2474
failed:
2475 2476 2477 2478 2479
	/*
	 * all cleanup jobs (xgmi terminate, ras terminate,
	 * ring destroy, cmd/fence/fw buffers destory,
	 * psp->cmd destory) are delayed to psp_hw_fini
	 */
2480
	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2481 2482 2483 2484 2485 2486 2487 2488 2489
	return ret;
}

static int psp_hw_init(void *handle)
{
	int ret;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	mutex_lock(&adev->firmware.mutex);
2490 2491 2492 2493 2494 2495 2496
	/*
	 * This sequence is just used on hw_init only once, no need on
	 * resume.
	 */
	ret = amdgpu_ucode_init_bo(adev);
	if (ret)
		goto failed;
2497 2498 2499 2500 2501 2502 2503 2504

	ret = psp_load_fw(adev);
	if (ret) {
		DRM_ERROR("PSP firmware loading failed\n");
		goto failed;
	}

	mutex_unlock(&adev->firmware.mutex);
2505
	return 0;
2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517

failed:
	adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
	mutex_unlock(&adev->firmware.mutex);
	return -EINVAL;
}

static int psp_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct psp_context *psp = &adev->psp;

2518
	if (psp->ta_fw) {
2519
		psp_ras_terminate(psp);
2520
		psp_securedisplay_terminate(psp);
2521
		psp_rap_terminate(psp);
2522
		psp_dtm_terminate(psp);
2523 2524
		psp_hdcp_terminate(psp);
	}
2525

2526
	psp_asd_terminate(psp);
2527
	psp_tmr_terminate(psp);
2528

2529
	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2530

2531 2532
	psp_free_shared_bufs(psp);

2533 2534 2535 2536 2537
	return 0;
}

static int psp_suspend(void *handle)
{
2538
	int ret = 0;
2539 2540 2541
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct psp_context *psp = &adev->psp;

2542
	if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2543
	    psp->xgmi_context.context.initialized) {
2544 2545 2546
		ret = psp_xgmi_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate xgmi ta\n");
2547
			goto out;
2548 2549 2550
		}
	}

2551
	if (psp->ta_fw) {
2552 2553 2554
		ret = psp_ras_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate ras ta\n");
2555
			goto out;
2556
		}
2557 2558 2559
		ret = psp_hdcp_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate hdcp ta\n");
2560
			goto out;
2561
		}
2562 2563 2564
		ret = psp_dtm_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate dtm ta\n");
2565
			goto out;
2566
		}
2567 2568 2569
		ret = psp_rap_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate rap ta\n");
2570
			goto out;
2571
		}
2572 2573 2574
		ret = psp_securedisplay_terminate(psp);
		if (ret) {
			DRM_ERROR("Failed to terminate securedisplay ta\n");
2575
			goto out;
2576
		}
2577 2578
	}

2579
	ret = psp_asd_terminate(psp);
2580
	if (ret) {
2581
		DRM_ERROR("Failed to terminate asd\n");
2582
		goto out;
2583 2584
	}

2585 2586
	ret = psp_tmr_terminate(psp);
	if (ret) {
2587
		DRM_ERROR("Failed to terminate tmr\n");
2588
		goto out;
2589 2590
	}

2591 2592 2593 2594 2595
	ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
	if (ret) {
		DRM_ERROR("PSP ring stop failed\n");
	}

2596 2597 2598 2599
out:
	psp_free_shared_bufs(psp);

	return ret;
2600 2601 2602 2603 2604 2605
}

static int psp_resume(void *handle)
{
	int ret;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2606
	struct psp_context *psp = &adev->psp;
2607

2608 2609
	DRM_INFO("PSP is resuming...\n");

2610 2611 2612 2613 2614 2615
	if (psp->mem_train_ctx.enable_mem_training) {
		ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
		if (ret) {
			DRM_ERROR("Failed to process memory training!\n");
			return ret;
		}
2616 2617
	}

2618 2619
	mutex_lock(&adev->firmware.mutex);

2620
	ret = psp_hw_start(psp);
2621
	if (ret)
2622 2623
		goto failed;

2624
	ret = psp_load_non_psp_fw(psp);
2625 2626
	if (ret)
		goto failed;
2627

2628
	ret = psp_asd_initialize(psp);
2629 2630 2631 2632 2633
	if (ret) {
		DRM_ERROR("PSP load asd failed!\n");
		goto failed;
	}

2634 2635 2636 2637 2638 2639
	ret = psp_rl_load(adev);
	if (ret) {
		dev_err(adev->dev, "PSP load RL failed!\n");
		goto failed;
	}

2640
	if (adev->gmc.xgmi.num_physical_nodes > 1) {
2641
		ret = psp_xgmi_initialize(psp, false, true);
2642 2643 2644 2645 2646 2647 2648 2649
		/* Warning the XGMI seesion initialize failure
		 * Instead of stop driver initialization
		 */
		if (ret)
			dev_err(psp->adev->dev,
				"XGMI: Failed to initialize XGMI session\n");
	}

2650
	if (psp->ta_fw) {
2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664
		ret = psp_ras_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
					"RAS: Failed to initialize RAS\n");

		ret = psp_hdcp_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"HDCP: Failed to initialize HDCP\n");

		ret = psp_dtm_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"DTM: Failed to initialize DTM\n");
2665 2666 2667 2668 2669

		ret = psp_rap_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"RAP: Failed to initialize RAP\n");
2670 2671 2672 2673 2674

		ret = psp_securedisplay_initialize(psp);
		if (ret)
			dev_err(psp->adev->dev,
				"SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2675 2676
	}

2677 2678
	mutex_unlock(&adev->firmware.mutex);

2679 2680 2681 2682 2683
	return 0;

failed:
	DRM_ERROR("PSP resume failed\n");
	mutex_unlock(&adev->firmware.mutex);
2684 2685 2686
	return ret;
}

2687
int psp_gpu_reset(struct amdgpu_device *adev)
2688
{
2689 2690
	int ret;

2691 2692 2693
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
		return 0;

2694 2695 2696 2697 2698
	mutex_lock(&adev->psp.mutex);
	ret = psp_mode1_reset(&adev->psp);
	mutex_unlock(&adev->psp.mutex);

	return ret;
2699 2700
}

2701 2702 2703
int psp_rlc_autoload_start(struct psp_context *psp)
{
	int ret;
2704
	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2705 2706 2707 2708 2709

	cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;

	ret = psp_cmd_submit_buf(psp, NULL, cmd,
				 psp->fence_buf_mc_addr);
2710

2711 2712
	release_psp_cmd_buf(psp);

2713 2714 2715
	return ret;
}

2716 2717 2718 2719 2720 2721 2722 2723 2724 2725
int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
			uint64_t cmd_gpu_addr, int cmd_size)
{
	struct amdgpu_firmware_info ucode = {0};

	ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
		AMDGPU_UCODE_ID_VCN0_RAM;
	ucode.mc_addr = cmd_gpu_addr;
	ucode.ucode_size = cmd_size;

2726
	return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2727 2728
}

2729 2730 2731 2732 2733 2734
int psp_ring_cmd_submit(struct psp_context *psp,
			uint64_t cmd_buf_mc_addr,
			uint64_t fence_mc_addr,
			int index)
{
	unsigned int psp_write_ptr_reg = 0;
2735
	struct psp_gfx_rb_frame *write_frame;
2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770
	struct psp_ring *ring = &psp->km_ring;
	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
	struct amdgpu_device *adev = psp->adev;
	uint32_t ring_size_dw = ring->ring_size / 4;
	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;

	/* KM (GPCOM) prepare write pointer */
	psp_write_ptr_reg = psp_ring_get_wptr(psp);

	/* Update KM RB frame pointer to new frame */
	/* write_frame ptr increments by size of rb_frame in bytes */
	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
	if ((psp_write_ptr_reg % ring_size_dw) == 0)
		write_frame = ring_buffer_start;
	else
		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
	/* Check invalid write_frame ptr address */
	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
			  ring_buffer_start, ring_buffer_end, write_frame);
		DRM_ERROR("write_frame is pointing to address out of bounds\n");
		return -EINVAL;
	}

	/* Initialize KM RB frame */
	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));

	/* Update KM RB frame */
	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
	write_frame->fence_value = index;
2771
	amdgpu_device_flush_hdp(adev, NULL);
2772 2773 2774 2775 2776 2777 2778

	/* Update the write Pointer in DWORDs */
	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
	psp_ring_set_wptr(psp, psp_write_ptr_reg);
	return 0;
}

2779 2780 2781 2782
int psp_init_asd_microcode(struct psp_context *psp,
			   const char *chip_name)
{
	struct amdgpu_device *adev = psp->adev;
2783
	char fw_name[PSP_FW_NAME_LEN];
2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801
	const struct psp_firmware_header_v1_0 *asd_hdr;
	int err = 0;

	if (!chip_name) {
		dev_err(adev->dev, "invalid chip name for asd microcode\n");
		return -EINVAL;
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = amdgpu_ucode_validate(adev->psp.asd_fw);
	if (err)
		goto out;

	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2802 2803 2804 2805
	adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
	adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
	adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
	adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2806 2807 2808 2809 2810 2811 2812 2813 2814
				le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
	return 0;
out:
	dev_err(adev->dev, "fail to initialize asd microcode\n");
	release_firmware(adev->psp.asd_fw);
	adev->psp.asd_fw = NULL;
	return err;
}

2815 2816 2817 2818
int psp_init_toc_microcode(struct psp_context *psp,
			   const char *chip_name)
{
	struct amdgpu_device *adev = psp->adev;
2819
	char fw_name[PSP_FW_NAME_LEN];
2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837
	const struct psp_firmware_header_v1_0 *toc_hdr;
	int err = 0;

	if (!chip_name) {
		dev_err(adev->dev, "invalid chip name for toc microcode\n");
		return -EINVAL;
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
	err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = amdgpu_ucode_validate(adev->psp.toc_fw);
	if (err)
		goto out;

	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2838 2839 2840 2841
	adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
	adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
	adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
	adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2842 2843 2844 2845 2846 2847 2848 2849 2850
				le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
	return 0;
out:
	dev_err(adev->dev, "fail to request/validate toc microcode\n");
	release_firmware(adev->psp.toc_fw);
	adev->psp.toc_fw = NULL;
	return err;
}

2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
static int parse_sos_bin_descriptor(struct psp_context *psp,
				   const struct psp_fw_bin_desc *desc,
				   const struct psp_firmware_header_v2_0 *sos_hdr)
{
	uint8_t *ucode_start_addr  = NULL;

	if (!psp || !desc || !sos_hdr)
		return -EINVAL;

	ucode_start_addr  = (uint8_t *)sos_hdr +
			    le32_to_cpu(desc->offset_bytes) +
			    le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);

	switch (desc->fw_type) {
	case PSP_FW_TYPE_PSP_SOS:
		psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
		psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
		psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->sos.start_addr 	   = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_SYS_DRV:
		psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
		psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
		psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->sys.start_addr        = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_KDB:
		psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
		psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
		psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->kdb.start_addr        = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_TOC:
		psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
		psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
		psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->toc.start_addr        = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_SPL:
		psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
		psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
		psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->spl.start_addr        = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_RL:
		psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
		psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
		psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
		psp->rl.start_addr         = ucode_start_addr;
		break;
2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918
	case PSP_FW_TYPE_PSP_SOC_DRV:
		psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
		psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
		psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
		psp->soc_drv.start_addr         = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_INTF_DRV:
		psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
		psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
		psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->intf_drv.start_addr        = ucode_start_addr;
		break;
	case PSP_FW_TYPE_PSP_DBG_DRV:
		psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
		psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
		psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
		psp->dbg_drv.start_addr         = ucode_start_addr;
		break;
2919 2920 2921 2922 2923 2924 2925 2926
	default:
		dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
		break;
	}

	return 0;
}

2927 2928 2929 2930
static int psp_init_sos_base_fw(struct amdgpu_device *adev)
{
	const struct psp_firmware_header_v1_0 *sos_hdr;
	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2931
	uint8_t *ucode_array_start_addr;
2932 2933

	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2934 2935
	ucode_array_start_addr = (uint8_t *)sos_hdr +
		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2936

2937
	if (adev->gmc.xgmi.connected_to_cpu ||
2938
	    (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
2939 2940
		adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
		adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
2941

2942 2943
		adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
		adev->psp.sys.start_addr = ucode_array_start_addr;
2944

2945 2946
		adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
		adev->psp.sos.start_addr = ucode_array_start_addr +
2947 2948 2949 2950 2951
				le32_to_cpu(sos_hdr->sos.offset_bytes);
	} else {
		/* Load alternate PSP SOS FW */
		sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;

2952 2953
		adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
		adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2954

2955 2956
		adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
		adev->psp.sys.start_addr = ucode_array_start_addr +
2957 2958
			le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);

2959 2960
		adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
		adev->psp.sos.start_addr = ucode_array_start_addr +
2961 2962 2963
			le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
	}

2964
	if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
2965 2966 2967 2968 2969 2970 2971
		dev_warn(adev->dev, "PSP SOS FW not available");
		return -EINVAL;
	}

	return 0;
}

2972 2973 2974 2975
int psp_init_sos_microcode(struct psp_context *psp,
			   const char *chip_name)
{
	struct amdgpu_device *adev = psp->adev;
2976
	char fw_name[PSP_FW_NAME_LEN];
2977 2978 2979
	const struct psp_firmware_header_v1_0 *sos_hdr;
	const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2980
	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2981
	const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
2982
	int err = 0;
2983
	uint8_t *ucode_array_start_addr;
2984
	int fw_index = 0;
2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000

	if (!chip_name) {
		dev_err(adev->dev, "invalid chip name for sos microcode\n");
		return -EINVAL;
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = amdgpu_ucode_validate(adev->psp.sos_fw);
	if (err)
		goto out;

	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3001 3002
	ucode_array_start_addr = (uint8_t *)sos_hdr +
		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3003 3004 3005 3006
	amdgpu_ucode_print_psp_hdr(&sos_hdr->header);

	switch (sos_hdr->header.header_version_major) {
	case 1:
3007 3008 3009 3010
		err = psp_init_sos_base_fw(adev);
		if (err)
			goto out;

3011 3012
		if (sos_hdr->header.header_version_minor == 1) {
			sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3013 3014
			adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
			adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3015
					le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3016 3017
			adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
			adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3018
					le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3019 3020 3021
		}
		if (sos_hdr->header.header_version_minor == 2) {
			sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3022 3023
			adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
			adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3024
						    le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3025
		}
3026 3027
		if (sos_hdr->header.header_version_minor == 3) {
			sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3028 3029
			adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
			adev->psp.toc.start_addr = ucode_array_start_addr +
3030
				le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3031 3032
			adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
			adev->psp.kdb.start_addr = ucode_array_start_addr +
3033
				le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3034 3035
			adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
			adev->psp.spl.start_addr = ucode_array_start_addr +
3036
				le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3037 3038
			adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
			adev->psp.rl.start_addr = ucode_array_start_addr +
3039
				le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3040
		}
3041
		break;
3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058
	case 2:
		sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;

		if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
			dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
			err = -EINVAL;
			goto out;
		}

		for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
			err = parse_sos_bin_descriptor(psp,
						       &sos_hdr_v2_0->psp_fw_bin[fw_index],
						       sos_hdr_v2_0);
			if (err)
				goto out;
		}
		break;
3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075
	default:
		dev_err(adev->dev,
			"unsupported psp sos firmware\n");
		err = -EINVAL;
		goto out;
	}

	return 0;
out:
	dev_err(adev->dev,
		"failed to init sos firmware\n");
	release_firmware(adev->psp.sos_fw);
	adev->psp.sos_fw = NULL;

	return err;
}

3076
static int parse_ta_bin_descriptor(struct psp_context *psp,
3077
				   const struct psp_fw_bin_desc *desc,
3078
				   const struct ta_firmware_header_v2_0 *ta_hdr)
3079 3080 3081 3082 3083 3084
{
	uint8_t *ucode_start_addr  = NULL;

	if (!psp || !desc || !ta_hdr)
		return -EINVAL;

3085 3086 3087
	ucode_start_addr  = (uint8_t *)ta_hdr +
			    le32_to_cpu(desc->offset_bytes) +
			    le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3088 3089 3090

	switch (desc->fw_type) {
	case TA_FW_TYPE_PSP_ASD:
3091 3092 3093 3094
		psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
		psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
		psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3095 3096
		break;
	case TA_FW_TYPE_PSP_XGMI:
3097
		psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3098 3099
		psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
		psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3100 3101
		break;
	case TA_FW_TYPE_PSP_RAS:
3102
		psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3103 3104
		psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
		psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3105 3106
		break;
	case TA_FW_TYPE_PSP_HDCP:
3107
		psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3108 3109
		psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
		psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3110 3111
		break;
	case TA_FW_TYPE_PSP_DTM:
3112
		psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3113 3114
		psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
		psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3115
		break;
3116
	case TA_FW_TYPE_PSP_RAP:
3117
		psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3118 3119
		psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
		psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3120
		break;
3121
	case TA_FW_TYPE_PSP_SECUREDISPLAY:
3122
		psp->securedisplay_context.context.bin_desc.fw_version =
3123 3124 3125 3126 3127
			le32_to_cpu(desc->fw_version);
		psp->securedisplay_context.context.bin_desc.size_bytes =
			le32_to_cpu(desc->size_bytes);
		psp->securedisplay_context.context.bin_desc.start_addr =
			ucode_start_addr;
3128
		break;
3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140
	default:
		dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
		break;
	}

	return 0;
}

int psp_init_ta_microcode(struct psp_context *psp,
			  const char *chip_name)
{
	struct amdgpu_device *adev = psp->adev;
3141
	char fw_name[PSP_FW_NAME_LEN];
3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
	const struct ta_firmware_header_v2_0 *ta_hdr;
	int err = 0;
	int ta_index = 0;

	if (!chip_name) {
		dev_err(adev->dev, "invalid chip name for ta microcode\n");
		return -EINVAL;
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
	err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = amdgpu_ucode_validate(adev->psp.ta_fw);
	if (err)
		goto out;

	ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;

	if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
		dev_err(adev->dev, "unsupported TA header version\n");
		err = -EINVAL;
		goto out;
	}

3168
	if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189
		dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
		err = -EINVAL;
		goto out;
	}

	for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
		err = parse_ta_bin_descriptor(psp,
					      &ta_hdr->ta_fw_bin[ta_index],
					      ta_hdr);
		if (err)
			goto out;
	}

	return 0;
out:
	dev_err(adev->dev, "fail to initialize ta microcode\n");
	release_firmware(adev->psp.ta_fw);
	adev->psp.ta_fw = NULL;
	return err;
}

3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241
int psp_init_cap_microcode(struct psp_context *psp,
			  const char *chip_name)
{
	struct amdgpu_device *adev = psp->adev;
	char fw_name[PSP_FW_NAME_LEN];
	const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
	struct amdgpu_firmware_info *info = NULL;
	int err = 0;

	if (!chip_name) {
		dev_err(adev->dev, "invalid chip name for cap microcode\n");
		return -EINVAL;
	}

	if (!amdgpu_sriov_vf(adev)) {
		dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
		return -EINVAL;
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
	err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
	if (err) {
		dev_warn(adev->dev, "cap microcode does not exist, skip\n");
		err = 0;
		goto out;
	}

	err = amdgpu_ucode_validate(adev->psp.cap_fw);
	if (err) {
		dev_err(adev->dev, "fail to initialize cap microcode\n");
		goto out;
	}

	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
	info->ucode_id = AMDGPU_UCODE_ID_CAP;
	info->fw = adev->psp.cap_fw;
	cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
		adev->psp.cap_fw->data;
	adev->firmware.fw_size += ALIGN(
			le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
	adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
	adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
	adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);

	return 0;

out:
	release_firmware(adev->psp.cap_fw);
	adev->psp.cap_fw = NULL;
	return err;
}

3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253
static int psp_set_clockgating_state(void *handle,
				     enum amd_clockgating_state state)
{
	return 0;
}

static int psp_set_powergating_state(void *handle,
				     enum amd_powergating_state state)
{
	return 0;
}

3254 3255 3256 3257 3258
static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
					 struct device_attribute *attr,
					 char *buf)
{
	struct drm_device *ddev = dev_get_drvdata(dev);
3259
	struct amdgpu_device *adev = drm_to_adev(ddev);
3260 3261 3262
	uint32_t fw_ver;
	int ret;

3263 3264 3265 3266 3267
	if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
		DRM_INFO("PSP block is not ready yet.");
		return -EBUSY;
	}

3268 3269 3270 3271 3272 3273 3274 3275 3276
	mutex_lock(&adev->psp.mutex);
	ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
	mutex_unlock(&adev->psp.mutex);

	if (ret) {
		DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
		return ret;
	}

3277
	return sysfs_emit(buf, "%x\n", fw_ver);
3278 3279 3280 3281 3282 3283 3284 3285
}

static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
						       struct device_attribute *attr,
						       const char *buf,
						       size_t count)
{
	struct drm_device *ddev = dev_get_drvdata(dev);
3286
	struct amdgpu_device *adev = drm_to_adev(ddev);
3287
	int ret, idx;
3288 3289
	char fw_name[100];
	const struct firmware *usbc_pd_fw;
3290 3291 3292
	struct amdgpu_bo *fw_buf_bo = NULL;
	uint64_t fw_pri_mc_addr;
	void *fw_pri_cpu_addr;
3293

3294 3295 3296 3297
	if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
		DRM_INFO("PSP block is not ready yet.");
		return -EBUSY;
	}
3298

3299 3300 3301
	if (!drm_dev_enter(ddev, &idx))
		return -ENODEV;

3302 3303 3304 3305 3306
	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
	ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
	if (ret)
		goto fail;

3307 3308 3309 3310 3311 3312
	/* LFB address which is aligned to 1MB boundary per PSP request */
	ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
						AMDGPU_GEM_DOMAIN_VRAM,
						&fw_buf_bo,
						&fw_pri_mc_addr,
						&fw_pri_cpu_addr);
3313 3314 3315
	if (ret)
		goto rel_buf;

3316
	memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3317 3318

	mutex_lock(&adev->psp.mutex);
3319
	ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3320 3321
	mutex_unlock(&adev->psp.mutex);

3322 3323
	amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);

3324 3325 3326 3327 3328
rel_buf:
	release_firmware(usbc_pd_fw);
fail:
	if (ret) {
		DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3329
		count = ret;
3330 3331
	}

3332
	drm_dev_exit(idx);
3333 3334 3335
	return count;
}

3336 3337 3338 3339
void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
{
	int idx;

3340
	if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3341 3342 3343 3344 3345 3346 3347 3348
		return;

	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
	memcpy(psp->fw_pri_buf, start_addr, bin_size);

	drm_dev_exit(idx);
}

3349 3350 3351 3352
static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
		   psp_usbc_pd_fw_sysfs_read,
		   psp_usbc_pd_fw_sysfs_write);

3353 3354 3355 3356
int is_psp_fw_valid(struct psp_bin_desc bin)
{
	return bin.size_bytes;
}
3357

3358 3359 3360
const struct amd_ip_funcs psp_ip_funcs = {
	.name = "psp",
	.early_init = psp_early_init,
3361
	.late_init = NULL,
3362 3363 3364 3365 3366 3367 3368
	.sw_init = psp_sw_init,
	.sw_fini = psp_sw_fini,
	.hw_init = psp_hw_init,
	.hw_fini = psp_hw_fini,
	.suspend = psp_suspend,
	.resume = psp_resume,
	.is_idle = NULL,
3369
	.check_soft_reset = NULL,
3370
	.wait_for_idle = NULL,
3371
	.soft_reset = NULL,
3372 3373 3374 3375
	.set_clockgating_state = psp_set_clockgating_state,
	.set_powergating_state = psp_set_powergating_state,
};

3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390
static int psp_sysfs_init(struct amdgpu_device *adev)
{
	int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);

	if (ret)
		DRM_ERROR("Failed to create USBC PD FW control file!");

	return ret;
}

static void psp_sysfs_fini(struct amdgpu_device *adev)
{
	device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
}

3391 3392 3393 3394 3395 3396 3397 3398
const struct amdgpu_ip_block_version psp_v3_1_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 3,
	.minor = 1,
	.rev = 0,
	.funcs = &psp_ip_funcs,
};
3399 3400 3401 3402 3403 3404 3405 3406 3407

const struct amdgpu_ip_block_version psp_v10_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 10,
	.minor = 0,
	.rev = 0,
	.funcs = &psp_ip_funcs,
};
3408 3409 3410 3411 3412 3413 3414 3415 3416

const struct amdgpu_ip_block_version psp_v11_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 11,
	.minor = 0,
	.rev = 0,
	.funcs = &psp_ip_funcs,
};
3417

3418 3419 3420 3421 3422 3423 3424 3425
const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 11,
	.minor = 0,
	.rev = 8,
	.funcs = &psp_ip_funcs,
};

3426 3427 3428 3429 3430 3431 3432 3433
const struct amdgpu_ip_block_version psp_v12_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 12,
	.minor = 0,
	.rev = 0,
	.funcs = &psp_ip_funcs,
};
3434 3435 3436 3437 3438 3439 3440 3441

const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
	.type = AMD_IP_BLOCK_TYPE_PSP,
	.major = 13,
	.minor = 0,
	.rev = 0,
	.funcs = &psp_ip_funcs,
};