arm-smmu.c 57.3 KB
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/*
 * IOMMU API for ARM architected SMMU implementations.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2013 ARM Limited
 *
 * Author: Will Deacon <will.deacon@arm.com>
 *
 * This driver currently supports:
 *	- SMMUv1 and v2 implementations
 *	- Stream-matching and stream-indexing
 *	- v7/v8 long-descriptor format
 *	- Non-secure access to the SMMU
 *	- Context fault reporting
 */

#define pr_fmt(fmt) "arm-smmu: " fmt

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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_iommu.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/amba/bus.h>

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#include "io-pgtable.h"
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/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS		128

/* SMMU global address space */
#define ARM_SMMU_GR0(smmu)		((smmu)->base)
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#define ARM_SMMU_GR1(smmu)		((smmu)->base + (1 << (smmu)->pgshift))
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/*
 * SMMU global address space with conditional offset to access secure
 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
 * nsGFSYNR0: 0x450)
 */
#define ARM_SMMU_GR0_NS(smmu)						\
	((smmu)->base +							\
		((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)	\
			? 0x400 : 0))

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/*
 * Some 64-bit registers only make sense to write atomically, but in such
 * cases all the data relevant to AArch32 formats lies within the lower word,
 * therefore this actually makes more sense than it might first appear.
 */
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#ifdef CONFIG_64BIT
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#define smmu_write_atomic_lq		writeq_relaxed
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#else
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#define smmu_write_atomic_lq		writel_relaxed
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#endif

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/* Configuration registers */
#define ARM_SMMU_GR0_sCR0		0x0
#define sCR0_CLIENTPD			(1 << 0)
#define sCR0_GFRE			(1 << 1)
#define sCR0_GFIE			(1 << 2)
#define sCR0_GCFGFRE			(1 << 4)
#define sCR0_GCFGFIE			(1 << 5)
#define sCR0_USFCFG			(1 << 10)
#define sCR0_VMIDPNE			(1 << 11)
#define sCR0_PTM			(1 << 12)
#define sCR0_FB				(1 << 13)
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#define sCR0_VMID16EN			(1 << 31)
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#define sCR0_BSU_SHIFT			14
#define sCR0_BSU_MASK			0x3

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/* Auxiliary Configuration register */
#define ARM_SMMU_GR0_sACR		0x10

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/* Identification registers */
#define ARM_SMMU_GR0_ID0		0x20
#define ARM_SMMU_GR0_ID1		0x24
#define ARM_SMMU_GR0_ID2		0x28
#define ARM_SMMU_GR0_ID3		0x2c
#define ARM_SMMU_GR0_ID4		0x30
#define ARM_SMMU_GR0_ID5		0x34
#define ARM_SMMU_GR0_ID6		0x38
#define ARM_SMMU_GR0_ID7		0x3c
#define ARM_SMMU_GR0_sGFSR		0x48
#define ARM_SMMU_GR0_sGFSYNR0		0x50
#define ARM_SMMU_GR0_sGFSYNR1		0x54
#define ARM_SMMU_GR0_sGFSYNR2		0x58

#define ID0_S1TS			(1 << 30)
#define ID0_S2TS			(1 << 29)
#define ID0_NTS				(1 << 28)
#define ID0_SMS				(1 << 27)
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#define ID0_ATOSNS			(1 << 26)
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#define ID0_PTFS_NO_AARCH32		(1 << 25)
#define ID0_PTFS_NO_AARCH32S		(1 << 24)
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#define ID0_CTTW			(1 << 14)
#define ID0_NUMIRPT_SHIFT		16
#define ID0_NUMIRPT_MASK		0xff
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#define ID0_NUMSIDB_SHIFT		9
#define ID0_NUMSIDB_MASK		0xf
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#define ID0_NUMSMRG_SHIFT		0
#define ID0_NUMSMRG_MASK		0xff

#define ID1_PAGESIZE			(1 << 31)
#define ID1_NUMPAGENDXB_SHIFT		28
#define ID1_NUMPAGENDXB_MASK		7
#define ID1_NUMS2CB_SHIFT		16
#define ID1_NUMS2CB_MASK		0xff
#define ID1_NUMCB_SHIFT			0
#define ID1_NUMCB_MASK			0xff

#define ID2_OAS_SHIFT			4
#define ID2_OAS_MASK			0xf
#define ID2_IAS_SHIFT			0
#define ID2_IAS_MASK			0xf
#define ID2_UBS_SHIFT			8
#define ID2_UBS_MASK			0xf
#define ID2_PTFS_4K			(1 << 12)
#define ID2_PTFS_16K			(1 << 13)
#define ID2_PTFS_64K			(1 << 14)
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#define ID2_VMID16			(1 << 15)
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#define ID7_MAJOR_SHIFT			4
#define ID7_MAJOR_MASK			0xf
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/* Global TLB invalidation */
#define ARM_SMMU_GR0_TLBIVMID		0x64
#define ARM_SMMU_GR0_TLBIALLNSNH	0x68
#define ARM_SMMU_GR0_TLBIALLH		0x6c
#define ARM_SMMU_GR0_sTLBGSYNC		0x70
#define ARM_SMMU_GR0_sTLBGSTATUS	0x74
#define sTLBGSTATUS_GSACTIVE		(1 << 0)
#define TLB_LOOP_TIMEOUT		1000000	/* 1s! */

/* Stream mapping registers */
#define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
#define SMR_VALID			(1 << 31)
#define SMR_MASK_SHIFT			16
#define SMR_ID_SHIFT			0

#define ARM_SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
#define S2CR_CBNDX_SHIFT		0
#define S2CR_CBNDX_MASK			0xff
#define S2CR_TYPE_SHIFT			16
#define S2CR_TYPE_MASK			0x3
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enum arm_smmu_s2cr_type {
	S2CR_TYPE_TRANS,
	S2CR_TYPE_BYPASS,
	S2CR_TYPE_FAULT,
};
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#define S2CR_PRIVCFG_SHIFT		24
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#define S2CR_PRIVCFG_MASK		0x3
enum arm_smmu_s2cr_privcfg {
	S2CR_PRIVCFG_DEFAULT,
	S2CR_PRIVCFG_DIPAN,
	S2CR_PRIVCFG_UNPRIV,
	S2CR_PRIVCFG_PRIV,
};
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/* Context bank attribute registers */
#define ARM_SMMU_GR1_CBAR(n)		(0x0 + ((n) << 2))
#define CBAR_VMID_SHIFT			0
#define CBAR_VMID_MASK			0xff
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#define CBAR_S1_BPSHCFG_SHIFT		8
#define CBAR_S1_BPSHCFG_MASK		3
#define CBAR_S1_BPSHCFG_NSH		3
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#define CBAR_S1_MEMATTR_SHIFT		12
#define CBAR_S1_MEMATTR_MASK		0xf
#define CBAR_S1_MEMATTR_WB		0xf
#define CBAR_TYPE_SHIFT			16
#define CBAR_TYPE_MASK			0x3
#define CBAR_TYPE_S2_TRANS		(0 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_BYPASS	(1 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_FAULT	(2 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_TRANS	(3 << CBAR_TYPE_SHIFT)
#define CBAR_IRPTNDX_SHIFT		24
#define CBAR_IRPTNDX_MASK		0xff

#define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))
#define CBA2R_RW64_32BIT		(0 << 0)
#define CBA2R_RW64_64BIT		(1 << 0)
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#define CBA2R_VMID_SHIFT		16
#define CBA2R_VMID_MASK			0xffff
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/* Translation context bank */
#define ARM_SMMU_CB_BASE(smmu)		((smmu)->base + ((smmu)->size >> 1))
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#define ARM_SMMU_CB(smmu, n)		((n) * (1 << (smmu)->pgshift))
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#define ARM_SMMU_CB_SCTLR		0x0
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#define ARM_SMMU_CB_ACTLR		0x4
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#define ARM_SMMU_CB_RESUME		0x8
#define ARM_SMMU_CB_TTBCR2		0x10
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#define ARM_SMMU_CB_TTBR0		0x20
#define ARM_SMMU_CB_TTBR1		0x28
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#define ARM_SMMU_CB_TTBCR		0x30
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#define ARM_SMMU_CB_CONTEXTIDR		0x34
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#define ARM_SMMU_CB_S1_MAIR0		0x38
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#define ARM_SMMU_CB_S1_MAIR1		0x3c
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#define ARM_SMMU_CB_PAR			0x50
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#define ARM_SMMU_CB_FSR			0x58
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#define ARM_SMMU_CB_FAR			0x60
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#define ARM_SMMU_CB_FSYNR0		0x68
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#define ARM_SMMU_CB_S1_TLBIVA		0x600
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#define ARM_SMMU_CB_S1_TLBIASID		0x610
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#define ARM_SMMU_CB_S1_TLBIVAL		0x620
#define ARM_SMMU_CB_S2_TLBIIPAS2	0x630
#define ARM_SMMU_CB_S2_TLBIIPAS2L	0x638
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#define ARM_SMMU_CB_ATS1PR		0x800
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#define ARM_SMMU_CB_ATSR		0x8f0
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#define SCTLR_S1_ASIDPNE		(1 << 12)
#define SCTLR_CFCFG			(1 << 7)
#define SCTLR_CFIE			(1 << 6)
#define SCTLR_CFRE			(1 << 5)
#define SCTLR_E				(1 << 4)
#define SCTLR_AFE			(1 << 2)
#define SCTLR_TRE			(1 << 1)
#define SCTLR_M				(1 << 0)

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#define ARM_MMU500_ACTLR_CPRE		(1 << 1)

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#define ARM_MMU500_ACR_CACHE_LOCK	(1 << 26)

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#define CB_PAR_F			(1 << 0)

#define ATSR_ACTIVE			(1 << 0)

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#define RESUME_RETRY			(0 << 0)
#define RESUME_TERMINATE		(1 << 0)

#define TTBCR2_SEP_SHIFT		15
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#define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
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#define TTBRn_ASID_SHIFT		48
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#define FSR_MULTI			(1 << 31)
#define FSR_SS				(1 << 30)
#define FSR_UUT				(1 << 8)
#define FSR_ASF				(1 << 7)
#define FSR_TLBLKF			(1 << 6)
#define FSR_TLBMCF			(1 << 5)
#define FSR_EF				(1 << 4)
#define FSR_PF				(1 << 3)
#define FSR_AFF				(1 << 2)
#define FSR_TF				(1 << 1)

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#define FSR_IGN				(FSR_AFF | FSR_ASF | \
					 FSR_TLBMCF | FSR_TLBLKF)
#define FSR_FAULT			(FSR_MULTI | FSR_SS | FSR_UUT | \
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					 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR			(1 << 4)

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static int force_stage;
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module_param(force_stage, int, S_IRUGO);
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MODULE_PARM_DESC(force_stage,
	"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
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static bool disable_bypass;
module_param(disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
	"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
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enum arm_smmu_arch_version {
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	ARM_SMMU_V1,
	ARM_SMMU_V1_64K,
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	ARM_SMMU_V2,
};

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enum arm_smmu_implementation {
	GENERIC_SMMU,
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	ARM_MMU500,
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	CAVIUM_SMMUV2,
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	QCOM_SMMUV2,
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};

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struct arm_smmu_s2cr {
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	struct iommu_group		*group;
	int				count;
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	enum arm_smmu_s2cr_type		type;
	enum arm_smmu_s2cr_privcfg	privcfg;
	u8				cbndx;
};

#define s2cr_init_val (struct arm_smmu_s2cr){				\
	.type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS,	\
}

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struct arm_smmu_smr {
	u16				mask;
	u16				id;
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	bool				valid;
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};

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struct arm_smmu_master_cfg {
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	struct arm_smmu_device		*smmu;
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	s16				smendx[];
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};
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#define INVALID_SMENDX			-1
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#define __fwspec_cfg(fw) ((struct arm_smmu_master_cfg *)fw->iommu_priv)
#define fwspec_smmu(fw)  (__fwspec_cfg(fw)->smmu)
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#define fwspec_smendx(fw, i) \
	(i >= fw->num_ids ? INVALID_SMENDX : __fwspec_cfg(fw)->smendx[i])
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#define for_each_cfg_sme(fw, i, idx) \
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	for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
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struct arm_smmu_device {
	struct device			*dev;

	void __iomem			*base;
	unsigned long			size;
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	unsigned long			pgshift;
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#define ARM_SMMU_FEAT_COHERENT_WALK	(1 << 0)
#define ARM_SMMU_FEAT_STREAM_MATCH	(1 << 1)
#define ARM_SMMU_FEAT_TRANS_S1		(1 << 2)
#define ARM_SMMU_FEAT_TRANS_S2		(1 << 3)
#define ARM_SMMU_FEAT_TRANS_NESTED	(1 << 4)
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#define ARM_SMMU_FEAT_TRANS_OPS		(1 << 5)
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#define ARM_SMMU_FEAT_VMID16		(1 << 6)
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#define ARM_SMMU_FEAT_FMT_AARCH64_4K	(1 << 7)
#define ARM_SMMU_FEAT_FMT_AARCH64_16K	(1 << 8)
#define ARM_SMMU_FEAT_FMT_AARCH64_64K	(1 << 9)
#define ARM_SMMU_FEAT_FMT_AARCH32_L	(1 << 10)
#define ARM_SMMU_FEAT_FMT_AARCH32_S	(1 << 11)
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	u32				features;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
	u32				options;
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	enum arm_smmu_arch_version	version;
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	enum arm_smmu_implementation	model;
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	u32				num_context_banks;
	u32				num_s2_context_banks;
	DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
	atomic_t			irptndx;

	u32				num_mapping_groups;
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	u16				streamid_mask;
	u16				smr_mask_mask;
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	struct arm_smmu_smr		*smrs;
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	struct arm_smmu_s2cr		*s2crs;
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	struct mutex			stream_map_mutex;
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	unsigned long			va_size;
	unsigned long			ipa_size;
	unsigned long			pa_size;
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	unsigned long			pgsize_bitmap;
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	u32				num_global_irqs;
	u32				num_context_irqs;
	unsigned int			*irqs;

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	u32				cavium_id_base; /* Specific to Cavium */
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};

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enum arm_smmu_context_fmt {
	ARM_SMMU_CTX_FMT_NONE,
	ARM_SMMU_CTX_FMT_AARCH64,
	ARM_SMMU_CTX_FMT_AARCH32_L,
	ARM_SMMU_CTX_FMT_AARCH32_S,
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};

struct arm_smmu_cfg {
	u8				cbndx;
	u8				irptndx;
	u32				cbar;
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	enum arm_smmu_context_fmt	fmt;
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};
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#define INVALID_IRPTNDX			0xff
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#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
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enum arm_smmu_domain_stage {
	ARM_SMMU_DOMAIN_S1 = 0,
	ARM_SMMU_DOMAIN_S2,
	ARM_SMMU_DOMAIN_NESTED,
};

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struct arm_smmu_domain {
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	struct arm_smmu_device		*smmu;
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	struct io_pgtable_ops		*pgtbl_ops;
	spinlock_t			pgtbl_lock;
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	struct arm_smmu_cfg		cfg;
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	enum arm_smmu_domain_stage	stage;
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	struct mutex			init_mutex; /* Protects smmu pointer */
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	struct iommu_domain		domain;
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};

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struct arm_smmu_option_prop {
	u32 opt;
	const char *prop;
};

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static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);

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static bool using_legacy_binding, using_generic_binding;

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static struct arm_smmu_option_prop arm_smmu_options[] = {
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	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
	{ 0, NULL},
};

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static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct arm_smmu_domain, domain);
}

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static void parse_driver_options(struct arm_smmu_device *smmu)
{
	int i = 0;
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	do {
		if (of_property_read_bool(smmu->dev->of_node,
						arm_smmu_options[i].prop)) {
			smmu->options |= arm_smmu_options[i].opt;
			dev_notice(smmu->dev, "option %s\n",
				arm_smmu_options[i].prop);
		}
	} while (arm_smmu_options[++i].opt);
}

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static struct device_node *dev_get_dev_node(struct device *dev)
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{
	if (dev_is_pci(dev)) {
		struct pci_bus *bus = to_pci_dev(dev)->bus;
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		while (!pci_is_root_bus(bus))
			bus = bus->parent;
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		return of_node_get(bus->bridge->parent->of_node);
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	}

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	return of_node_get(dev->of_node);
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}

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static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
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{
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	*((__be32 *)data) = cpu_to_be32(alias);
	return 0; /* Continue walking */
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}

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static int __find_legacy_master_phandle(struct device *dev, void *data)
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{
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	struct of_phandle_iterator *it = *(void **)data;
	struct device_node *np = it->node;
	int err;

	of_for_each_phandle(it, err, dev->of_node, "mmu-masters",
			    "#stream-id-cells", 0)
		if (it->node == np) {
			*(void **)data = dev;
			return 1;
		}
	it->node = np;
	return err == -ENOENT ? 0 : err;
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}

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static struct platform_driver arm_smmu_driver;
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static struct iommu_ops arm_smmu_ops;
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static int arm_smmu_register_legacy_master(struct device *dev,
					   struct arm_smmu_device **smmu)
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{
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	struct device *smmu_dev;
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	struct device_node *np;
	struct of_phandle_iterator it;
	void *data = &it;
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	u32 *sids;
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	__be32 pci_sid;
	int err;
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	np = dev_get_dev_node(dev);
	if (!np || !of_find_property(np, "#stream-id-cells", NULL)) {
		of_node_put(np);
		return -ENODEV;
	}
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	it.node = np;
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	err = driver_for_each_device(&arm_smmu_driver.driver, NULL, &data,
				     __find_legacy_master_phandle);
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	smmu_dev = data;
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	of_node_put(np);
	if (err == 0)
		return -ENODEV;
	if (err < 0)
		return err;
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	if (dev_is_pci(dev)) {
		/* "mmu-masters" assumes Stream ID == Requester ID */
		pci_for_each_dma_alias(to_pci_dev(dev), __arm_smmu_get_pci_sid,
				       &pci_sid);
		it.cur = &pci_sid;
		it.cur_count = 1;
	}
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	err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode,
				&arm_smmu_ops);
	if (err)
		return err;
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	sids = kcalloc(it.cur_count, sizeof(*sids), GFP_KERNEL);
	if (!sids)
		return -ENOMEM;
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	*smmu = dev_get_drvdata(smmu_dev);
	of_phandle_iterator_args(&it, sids, it.cur_count);
	err = iommu_fwspec_add_ids(dev, sids, it.cur_count);
	kfree(sids);
	return err;
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}

static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
{
	int idx;

	do {
		idx = find_next_zero_bit(map, end, start);
		if (idx == end)
			return -ENOSPC;
	} while (test_and_set_bit(idx, map));

	return idx;
}

static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
{
	clear_bit(idx, map);
}

/* Wait for any pending TLB invalidations to complete */
558
static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575
{
	int count = 0;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
	while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
	       & sTLBGSTATUS_GSACTIVE) {
		cpu_relax();
		if (++count == TLB_LOOP_TIMEOUT) {
			dev_err_ratelimited(smmu->dev,
			"TLB sync timed out -- SMMU may be deadlocked\n");
			return;
		}
		udelay(1);
	}
}

576 577 578 579 580 581 582
static void arm_smmu_tlb_sync(void *cookie)
{
	struct arm_smmu_domain *smmu_domain = cookie;
	__arm_smmu_tlb_sync(smmu_domain->smmu);
}

static void arm_smmu_tlb_inv_context(void *cookie)
583
{
584
	struct arm_smmu_domain *smmu_domain = cookie;
585 586
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
587
	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
588
	void __iomem *base;
589 590 591

	if (stage1) {
		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
592
		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
593
			       base + ARM_SMMU_CB_S1_TLBIASID);
594 595
	} else {
		base = ARM_SMMU_GR0(smmu);
596
		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
597
			       base + ARM_SMMU_GR0_TLBIVMID);
598 599
	}

600 601 602 603
	__arm_smmu_tlb_sync(smmu);
}

static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
604
					  size_t granule, bool leaf, void *cookie)
605 606 607 608 609 610 611 612 613 614 615
{
	struct arm_smmu_domain *smmu_domain = cookie;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
	void __iomem *reg;

	if (stage1) {
		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
		reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;

616
		if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) {
617
			iova &= ~12UL;
618
			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
619 620 621 622
			do {
				writel_relaxed(iova, reg);
				iova += granule;
			} while (size -= granule);
623 624
		} else {
			iova >>= 12;
625
			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
626 627 628 629
			do {
				writeq_relaxed(iova, reg);
				iova += granule >> 12;
			} while (size -= granule);
630 631 632 633 634
		}
	} else if (smmu->version == ARM_SMMU_V2) {
		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
		reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
			      ARM_SMMU_CB_S2_TLBIIPAS2;
635 636
		iova >>= 12;
		do {
637
			smmu_write_atomic_lq(iova, reg);
638 639
			iova += granule >> 12;
		} while (size -= granule);
640 641
	} else {
		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
642
		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
643 644 645 646 647 648 649 650 651
	}
}

static struct iommu_gather_ops arm_smmu_gather_ops = {
	.tlb_flush_all	= arm_smmu_tlb_inv_context,
	.tlb_add_flush	= arm_smmu_tlb_inv_range_nosync,
	.tlb_sync	= arm_smmu_tlb_sync,
};

652 653
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
{
654
	u32 fsr, fsynr;
655 656
	unsigned long iova;
	struct iommu_domain *domain = dev;
657
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
658 659
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
660 661
	void __iomem *cb_base;

662
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
663 664 665 666 667 668
	fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);

	if (!(fsr & FSR_FAULT))
		return IRQ_NONE;

	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
669
	iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
670

671 672 673
	dev_err_ratelimited(smmu->dev,
	"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
			    fsr, iova, fsynr, cfg->cbndx);
674

675 676
	writel(fsr, cb_base + ARM_SMMU_CB_FSR);
	return IRQ_HANDLED;
677 678 679 680 681 682
}

static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
{
	u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
	struct arm_smmu_device *smmu = dev;
683
	void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
684 685 686 687 688 689

	gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
	gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
	gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
	gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);

690 691 692
	if (!gfsr)
		return IRQ_NONE;

693 694 695 696 697 698 699
	dev_err_ratelimited(smmu->dev,
		"Unexpected global fault, this could be serious\n");
	dev_err_ratelimited(smmu->dev,
		"\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
		gfsr, gfsynr0, gfsynr1, gfsynr2);

	writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
700
	return IRQ_HANDLED;
701 702
}

703 704
static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
				       struct io_pgtable_cfg *pgtbl_cfg)
705
{
706
	u32 reg, reg2;
707
	u64 reg64;
708
	bool stage1;
709 710
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
711
	void __iomem *cb_base, *gr1_base;
712 713

	gr1_base = ARM_SMMU_GR1(smmu);
714 715
	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
716

717
	if (smmu->version > ARM_SMMU_V1) {
718 719 720 721
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
			reg = CBA2R_RW64_64BIT;
		else
			reg = CBA2R_RW64_32BIT;
722 723
		/* 16-bit VMIDs live in CBA2R */
		if (smmu->features & ARM_SMMU_FEAT_VMID16)
724
			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;
725

726 727 728
		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
	}

729
	/* CBAR */
730
	reg = cfg->cbar;
731
	if (smmu->version < ARM_SMMU_V2)
732
		reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
733

734 735 736 737 738 739 740
	/*
	 * Use the weakest shareability/memory types, so they are
	 * overridden by the ttbcr/pte.
	 */
	if (stage1) {
		reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
741 742
	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
		/* 8-bit VMIDs live in CBAR */
743
		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
744
	}
745
	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
746

747 748
	/* TTBRs */
	if (stage1) {
749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
		u16 asid = ARM_SMMU_CB_ASID(smmu, cfg);

		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
			reg = pgtbl_cfg->arm_v7s_cfg.ttbr[0];
			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0);
			reg = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1);
			writel_relaxed(asid, cb_base + ARM_SMMU_CB_CONTEXTIDR);
		} else {
			reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
			reg64 |= (u64)asid << TTBRn_ASID_SHIFT;
			writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
			reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
			reg64 |= (u64)asid << TTBRn_ASID_SHIFT;
			writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR1);
		}
765
	} else {
766
		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
767
		writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
768
	}
769

770 771
	/* TTBCR */
	if (stage1) {
772 773 774 775 776 777 778
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
			reg = pgtbl_cfg->arm_v7s_cfg.tcr;
			reg2 = 0;
		} else {
			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
			reg2 |= TTBCR2_SEP_UPSTREAM;
779
		}
780 781
		if (smmu->version > ARM_SMMU_V1)
			writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
782
	} else {
783
		reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
784
	}
785
	writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
786

787
	/* MAIRs (stage-1 only) */
788
	if (stage1) {
789 790 791 792 793 794 795
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
			reg = pgtbl_cfg->arm_v7s_cfg.prrr;
			reg2 = pgtbl_cfg->arm_v7s_cfg.nmrr;
		} else {
			reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
			reg2 = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
		}
796
		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
797
		writel_relaxed(reg2, cb_base + ARM_SMMU_CB_S1_MAIR1);
798 799 800
	}

	/* SCTLR */
801
	reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M;
802 803 804 805 806
	if (stage1)
		reg |= SCTLR_S1_ASIDPNE;
#ifdef __BIG_ENDIAN
	reg |= SCTLR_E;
#endif
807
	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
808 809 810
}

static int arm_smmu_init_domain_context(struct iommu_domain *domain,
811
					struct arm_smmu_device *smmu)
812
{
813
	int irq, start, ret = 0;
814 815 816 817
	unsigned long ias, oas;
	struct io_pgtable_ops *pgtbl_ops;
	struct io_pgtable_cfg pgtbl_cfg;
	enum io_pgtable_fmt fmt;
818
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
819
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
820

821
	mutex_lock(&smmu_domain->init_mutex);
822 823 824
	if (smmu_domain->smmu)
		goto out_unlock;

825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847
	/*
	 * Mapping the requested stage onto what we support is surprisingly
	 * complicated, mainly because the spec allows S1+S2 SMMUs without
	 * support for nested translation. That means we end up with the
	 * following table:
	 *
	 * Requested        Supported        Actual
	 *     S1               N              S1
	 *     S1             S1+S2            S1
	 *     S1               S2             S2
	 *     S1               S1             S1
	 *     N                N              N
	 *     N              S1+S2            S2
	 *     N                S2             S2
	 *     N                S1             S1
	 *
	 * Note that you can't actually request stage-2 mappings.
	 */
	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
		smmu_domain->stage = ARM_SMMU_DOMAIN_S1;

848 849 850 851 852 853 854 855 856 857
	/*
	 * Choosing a suitable context format is even more fiddly. Until we
	 * grow some way for the caller to express a preference, and/or move
	 * the decision into the io-pgtable code where it arguably belongs,
	 * just aim for the closest thing to the rest of the system, and hope
	 * that the hardware isn't esoteric enough that we can't assume AArch64
	 * support to be a superset of AArch32 support...
	 */
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L)
		cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L;
858 859 860 861 862
	if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) &&
	    !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) &&
	    (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) &&
	    (smmu_domain->stage == ARM_SMMU_DOMAIN_S1))
		cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S;
863 864 865 866 867 868 869 870 871 872 873
	if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) &&
	    (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K |
			       ARM_SMMU_FEAT_FMT_AARCH64_16K |
			       ARM_SMMU_FEAT_FMT_AARCH64_4K)))
		cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64;

	if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) {
		ret = -EINVAL;
		goto out_unlock;
	}

874 875 876 877
	switch (smmu_domain->stage) {
	case ARM_SMMU_DOMAIN_S1:
		cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
		start = smmu->num_s2_context_banks;
878 879
		ias = smmu->va_size;
		oas = smmu->ipa_size;
880
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
881
			fmt = ARM_64_LPAE_S1;
882
		} else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) {
883
			fmt = ARM_32_LPAE_S1;
884 885
			ias = min(ias, 32UL);
			oas = min(oas, 40UL);
886 887 888 889
		} else {
			fmt = ARM_V7S;
			ias = min(ias, 32UL);
			oas = min(oas, 32UL);
890
		}
891 892
		break;
	case ARM_SMMU_DOMAIN_NESTED:
893 894 895 896
		/*
		 * We will likely want to change this if/when KVM gets
		 * involved.
		 */
897
	case ARM_SMMU_DOMAIN_S2:
898 899
		cfg->cbar = CBAR_TYPE_S2_TRANS;
		start = 0;
900 901
		ias = smmu->ipa_size;
		oas = smmu->pa_size;
902
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
903
			fmt = ARM_64_LPAE_S2;
904
		} else {
905
			fmt = ARM_32_LPAE_S2;
906 907 908
			ias = min(ias, 40UL);
			oas = min(oas, 40UL);
		}
909 910 911 912
		break;
	default:
		ret = -EINVAL;
		goto out_unlock;
913 914 915 916
	}

	ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
				      smmu->num_context_banks);
917
	if (ret < 0)
918
		goto out_unlock;
919

920
	cfg->cbndx = ret;
921
	if (smmu->version < ARM_SMMU_V2) {
922 923
		cfg->irptndx = atomic_inc_return(&smmu->irptndx);
		cfg->irptndx %= smmu->num_context_irqs;
924
	} else {
925
		cfg->irptndx = cfg->cbndx;
926 927
	}

928
	pgtbl_cfg = (struct io_pgtable_cfg) {
929
		.pgsize_bitmap	= smmu->pgsize_bitmap,
930 931 932
		.ias		= ias,
		.oas		= oas,
		.tlb		= &arm_smmu_gather_ops,
933
		.iommu_dev	= smmu->dev,
934 935 936 937 938 939 940 941 942
	};

	smmu_domain->smmu = smmu;
	pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
	if (!pgtbl_ops) {
		ret = -ENOMEM;
		goto out_clear_smmu;
	}

943 944
	/* Update the domain's page sizes to reflect the page table format */
	domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
945 946
	domain->geometry.aperture_end = (1UL << ias) - 1;
	domain->geometry.force_aperture = true;
947

948 949 950 951 952 953 954
	/* Initialise the context bank with our page table cfg */
	arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);

	/*
	 * Request context fault interrupt. Do this last to avoid the
	 * handler seeing a half-initialised domain state.
	 */
955
	irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
956 957
	ret = devm_request_irq(smmu->dev, irq, arm_smmu_context_fault,
			       IRQF_SHARED, "arm-smmu-context-fault", domain);
958
	if (ret < 0) {
959
		dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
960 961
			cfg->irptndx, irq);
		cfg->irptndx = INVALID_IRPTNDX;
962 963
	}

964 965 966 967
	mutex_unlock(&smmu_domain->init_mutex);

	/* Publish page table ops for map/unmap */
	smmu_domain->pgtbl_ops = pgtbl_ops;
968
	return 0;
969

970 971
out_clear_smmu:
	smmu_domain->smmu = NULL;
972
out_unlock:
973
	mutex_unlock(&smmu_domain->init_mutex);
974 975 976 977 978
	return ret;
}

static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
{
979
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
980 981
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
982
	void __iomem *cb_base;
983 984
	int irq;

985
	if (!smmu)
986 987
		return;

988 989 990 991
	/*
	 * Disable the context bank and free the page tables before freeing
	 * it.
	 */
992
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
993 994
	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);

995 996
	if (cfg->irptndx != INVALID_IRPTNDX) {
		irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
997
		devm_free_irq(smmu->dev, irq, domain);
998 999
	}

1000
	free_io_pgtable_ops(smmu_domain->pgtbl_ops);
1001
	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
1002 1003
}

1004
static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
1005 1006 1007
{
	struct arm_smmu_domain *smmu_domain;

1008
	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1009
		return NULL;
1010 1011 1012 1013 1014 1015 1016
	/*
	 * Allocate the domain and initialise some of its data structures.
	 * We can't really do anything meaningful until we've added a
	 * master.
	 */
	smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
	if (!smmu_domain)
1017
		return NULL;
1018

1019 1020
	if (type == IOMMU_DOMAIN_DMA && (using_legacy_binding ||
	    iommu_get_dma_cookie(&smmu_domain->domain))) {
1021 1022 1023 1024
		kfree(smmu_domain);
		return NULL;
	}

1025 1026
	mutex_init(&smmu_domain->init_mutex);
	spin_lock_init(&smmu_domain->pgtbl_lock);
1027 1028

	return &smmu_domain->domain;
1029 1030
}

1031
static void arm_smmu_domain_free(struct iommu_domain *domain)
1032
{
1033
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1034 1035 1036 1037 1038

	/*
	 * Free the domain resources. We assume that all devices have
	 * already been detached.
	 */
1039
	iommu_put_dma_cookie(domain);
1040 1041 1042 1043
	arm_smmu_destroy_domain_context(domain);
	kfree(smmu_domain);
}

1044 1045 1046
static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
{
	struct arm_smmu_smr *smr = smmu->smrs + idx;
1047
	u32 reg = smr->id << SMR_ID_SHIFT | smr->mask << SMR_MASK_SHIFT;
1048 1049 1050 1051 1052 1053

	if (smr->valid)
		reg |= SMR_VALID;
	writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
}

1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070
static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
{
	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
	u32 reg = (s2cr->type & S2CR_TYPE_MASK) << S2CR_TYPE_SHIFT |
		  (s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
		  (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT;

	writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
}

static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
{
	arm_smmu_write_s2cr(smmu, idx);
	if (smmu->smrs)
		arm_smmu_write_smr(smmu, idx);
}

1071
static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
1072 1073
{
	struct arm_smmu_smr *smrs = smmu->smrs;
1074
	int i, free_idx = -ENOSPC;
1075

1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
	/* Stream indexing is blissfully easy */
	if (!smrs)
		return id;

	/* Validating SMRs is... less so */
	for (i = 0; i < smmu->num_mapping_groups; ++i) {
		if (!smrs[i].valid) {
			/*
			 * Note the first free entry we come across, which
			 * we'll claim in the end if nothing else matches.
			 */
			if (free_idx < 0)
				free_idx = i;
1089 1090
			continue;
		}
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
		/*
		 * If the new entry is _entirely_ matched by an existing entry,
		 * then reuse that, with the guarantee that there also cannot
		 * be any subsequent conflicting entries. In normal use we'd
		 * expect simply identical entries for this case, but there's
		 * no harm in accommodating the generalisation.
		 */
		if ((mask & smrs[i].mask) == mask &&
		    !((id ^ smrs[i].id) & ~smrs[i].mask))
			return i;
		/*
		 * If the new entry has any other overlap with an existing one,
		 * though, then there always exists at least one stream ID
		 * which would cause a conflict, and we can't allow that risk.
		 */
		if (!((id ^ smrs[i].id) & ~(smrs[i].mask | mask)))
			return -EINVAL;
	}
1109

1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
	return free_idx;
}

static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx)
{
	if (--smmu->s2crs[idx].count)
		return false;

	smmu->s2crs[idx] = s2cr_init_val;
	if (smmu->smrs)
		smmu->smrs[idx].valid = false;

	return true;
}

static int arm_smmu_master_alloc_smes(struct device *dev)
{
1127 1128
	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
	struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
1129 1130 1131 1132 1133 1134 1135
	struct arm_smmu_device *smmu = cfg->smmu;
	struct arm_smmu_smr *smrs = smmu->smrs;
	struct iommu_group *group;
	int i, idx, ret;

	mutex_lock(&smmu->stream_map_mutex);
	/* Figure out a viable stream map entry allocation */
1136
	for_each_cfg_sme(fwspec, i, idx) {
1137 1138 1139
		u16 sid = fwspec->ids[i];
		u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;

1140 1141 1142
		if (idx != INVALID_SMENDX) {
			ret = -EEXIST;
			goto out_err;
1143 1144
		}

1145
		ret = arm_smmu_find_sme(smmu, sid, mask);
1146 1147 1148 1149 1150
		if (ret < 0)
			goto out_err;

		idx = ret;
		if (smrs && smmu->s2crs[idx].count == 0) {
1151 1152
			smrs[idx].id = sid;
			smrs[idx].mask = mask;
1153 1154 1155 1156
			smrs[idx].valid = true;
		}
		smmu->s2crs[idx].count++;
		cfg->smendx[i] = (s16)idx;
1157 1158
	}

1159 1160 1161 1162 1163 1164 1165 1166
	group = iommu_group_get_for_dev(dev);
	if (!group)
		group = ERR_PTR(-ENOMEM);
	if (IS_ERR(group)) {
		ret = PTR_ERR(group);
		goto out_err;
	}
	iommu_group_put(group);
1167

1168
	/* It worked! Now, poke the actual hardware */
1169
	for_each_cfg_sme(fwspec, i, idx) {
1170 1171 1172
		arm_smmu_write_sme(smmu, idx);
		smmu->s2crs[idx].group = group;
	}
1173

1174
	mutex_unlock(&smmu->stream_map_mutex);
1175 1176
	return 0;

1177
out_err:
1178
	while (i--) {
1179
		arm_smmu_free_sme(smmu, cfg->smendx[i]);
1180 1181
		cfg->smendx[i] = INVALID_SMENDX;
	}
1182 1183
	mutex_unlock(&smmu->stream_map_mutex);
	return ret;
1184 1185
}

1186
static void arm_smmu_master_free_smes(struct iommu_fwspec *fwspec)
1187
{
1188 1189
	struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
	struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
1190
	int i, idx;
1191

1192
	mutex_lock(&smmu->stream_map_mutex);
1193
	for_each_cfg_sme(fwspec, i, idx) {
1194 1195
		if (arm_smmu_free_sme(smmu, idx))
			arm_smmu_write_sme(smmu, idx);
1196
		cfg->smendx[i] = INVALID_SMENDX;
1197
	}
1198
	mutex_unlock(&smmu->stream_map_mutex);
1199 1200 1201
}

static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1202
				      struct iommu_fwspec *fwspec)
1203
{
1204
	struct arm_smmu_device *smmu = smmu_domain->smmu;
1205 1206 1207
	struct arm_smmu_s2cr *s2cr = smmu->s2crs;
	enum arm_smmu_s2cr_type type = S2CR_TYPE_TRANS;
	u8 cbndx = smmu_domain->cfg.cbndx;
1208
	int i, idx;
1209

1210
	for_each_cfg_sme(fwspec, i, idx) {
1211
		if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
1212
			continue;
1213

1214
		s2cr[idx].type = type;
1215
		s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT;
1216 1217
		s2cr[idx].cbndx = cbndx;
		arm_smmu_write_s2cr(smmu, idx);
1218
	}
1219
	return 0;
1220 1221
}

1222 1223
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
{
1224
	int ret;
1225 1226
	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
	struct arm_smmu_device *smmu;
1227
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1228

1229
	if (!fwspec || fwspec->ops != &arm_smmu_ops) {
1230 1231 1232 1233
		dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
		return -ENXIO;
	}

1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	/*
	 * FIXME: The arch/arm DMA API code tries to attach devices to its own
	 * domains between of_xlate() and add_device() - we have no way to cope
	 * with that, so until ARM gets converted to rely on groups and default
	 * domains, just say no (but more politely than by dereferencing NULL).
	 * This should be at least a WARN_ON once that's sorted.
	 */
	if (!fwspec->iommu_priv)
		return -ENODEV;

1244
	smmu = fwspec_smmu(fwspec);
1245
	/* Ensure that the domain is finalised */
1246
	ret = arm_smmu_init_domain_context(domain, smmu);
1247
	if (ret < 0)
1248 1249
		return ret;

1250
	/*
1251 1252
	 * Sanity check the domain. We don't support domains across
	 * different SMMUs.
1253
	 */
1254
	if (smmu_domain->smmu != smmu) {
1255 1256
		dev_err(dev,
			"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1257
			dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1258
		return -EINVAL;
1259 1260 1261
	}

	/* Looks ok, so add the device to the domain */
1262
	return arm_smmu_domain_add_master(smmu_domain, fwspec);
1263 1264 1265
}

static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1266
			phys_addr_t paddr, size_t size, int prot)
1267
{
1268 1269
	int ret;
	unsigned long flags;
1270
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1271
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1272

1273
	if (!ops)
1274 1275
		return -ENODEV;

1276 1277 1278 1279
	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
	ret = ops->map(ops, iova, paddr, size, prot);
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
	return ret;
1280 1281 1282 1283 1284
}

static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
			     size_t size)
{
1285 1286
	size_t ret;
	unsigned long flags;
1287
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1288
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1289

1290 1291 1292 1293 1294 1295 1296
	if (!ops)
		return 0;

	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
	ret = ops->unmap(ops, iova, size);
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
	return ret;
1297 1298
}

1299 1300 1301
static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
					      dma_addr_t iova)
{
1302
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1303 1304 1305 1306 1307 1308 1309
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
	struct device *dev = smmu->dev;
	void __iomem *cb_base;
	u32 tmp;
	u64 phys;
1310
	unsigned long va;
1311 1312 1313

	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);

1314 1315 1316
	/* ATS1 registers can only be written atomically */
	va = iova & ~0xfffUL;
	if (smmu->version == ARM_SMMU_V2)
1317 1318
		smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
	else /* Register is only 32-bit in v1 */
1319
		writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1320 1321 1322 1323

	if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
				      !(tmp & ATSR_ACTIVE), 5, 50)) {
		dev_err(dev,
1324
			"iova to phys timed out on %pad. Falling back to software table walk.\n",
1325 1326 1327 1328
			&iova);
		return ops->iova_to_phys(ops, iova);
	}

1329
	phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
1330 1331 1332 1333 1334 1335 1336 1337 1338
	if (phys & CB_PAR_F) {
		dev_err(dev, "translation fault!\n");
		dev_err(dev, "PAR = 0x%llx\n", phys);
		return 0;
	}

	return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
}

1339
static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1340
					dma_addr_t iova)
1341
{
1342 1343
	phys_addr_t ret;
	unsigned long flags;
1344
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1345
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1346

1347
	if (!ops)
1348
		return 0;
1349

1350
	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1351 1352
	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
			smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1353
		ret = arm_smmu_iova_to_phys_hard(domain, iova);
1354
	} else {
1355
		ret = ops->iova_to_phys(ops, iova);
1356 1357
	}

1358
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1359

1360
	return ret;
1361 1362
}

1363
static bool arm_smmu_capable(enum iommu_cap cap)
1364
{
1365 1366
	switch (cap) {
	case IOMMU_CAP_CACHE_COHERENCY:
1367 1368 1369 1370 1371
		/*
		 * Return true here as the SMMU can always send out coherent
		 * requests.
		 */
		return true;
1372
	case IOMMU_CAP_INTR_REMAP:
1373
		return true; /* MSIs are just memory writes */
1374 1375
	case IOMMU_CAP_NOEXEC:
		return true;
1376
	default:
1377
		return false;
1378
	}
1379 1380
}

1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393
static int arm_smmu_match_node(struct device *dev, void *data)
{
	return dev->of_node == data;
}

static struct arm_smmu_device *arm_smmu_get_by_node(struct device_node *np)
{
	struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
						np, arm_smmu_match_node);
	put_device(dev);
	return dev ? dev_get_drvdata(dev) : NULL;
}

1394
static int arm_smmu_add_device(struct device *dev)
1395
{
1396
	struct arm_smmu_device *smmu;
1397
	struct arm_smmu_master_cfg *cfg;
1398
	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1399
	int i, ret;
1400

1401 1402 1403 1404 1405
	if (using_legacy_binding) {
		ret = arm_smmu_register_legacy_master(dev, &smmu);
		fwspec = dev->iommu_fwspec;
		if (ret)
			goto out_free;
1406
	} else if (fwspec && fwspec->ops == &arm_smmu_ops) {
1407 1408 1409 1410
		smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
	} else {
		return -ENODEV;
	}
1411

1412
	ret = -EINVAL;
1413 1414
	for (i = 0; i < fwspec->num_ids; i++) {
		u16 sid = fwspec->ids[i];
1415
		u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
1416

1417
		if (sid & ~smmu->streamid_mask) {
1418
			dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n",
1419 1420 1421 1422 1423 1424
				sid, smmu->streamid_mask);
			goto out_free;
		}
		if (mask & ~smmu->smr_mask_mask) {
			dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n",
				sid, smmu->smr_mask_mask);
1425 1426
			goto out_free;
		}
1427
	}
1428

1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
	ret = -ENOMEM;
	cfg = kzalloc(offsetof(struct arm_smmu_master_cfg, smendx[i]),
		      GFP_KERNEL);
	if (!cfg)
		goto out_free;

	cfg->smmu = smmu;
	fwspec->iommu_priv = cfg;
	while (i--)
		cfg->smendx[i] = INVALID_SMENDX;

1440
	ret = arm_smmu_master_alloc_smes(dev);
1441 1442 1443 1444
	if (ret)
		goto out_free;

	return 0;
1445 1446

out_free:
1447 1448 1449
	if (fwspec)
		kfree(fwspec->iommu_priv);
	iommu_fwspec_free(dev);
1450
	return ret;
1451 1452
}

1453 1454
static void arm_smmu_remove_device(struct device *dev)
{
1455
	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1456

1457
	if (!fwspec || fwspec->ops != &arm_smmu_ops)
1458
		return;
1459

1460
	arm_smmu_master_free_smes(fwspec);
1461
	iommu_group_remove_device(dev);
1462 1463
	kfree(fwspec->iommu_priv);
	iommu_fwspec_free(dev);
1464 1465
}

1466 1467
static struct iommu_group *arm_smmu_device_group(struct device *dev)
{
1468 1469
	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
	struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
1470 1471 1472
	struct iommu_group *group = NULL;
	int i, idx;

1473
	for_each_cfg_sme(fwspec, i, idx) {
1474 1475 1476 1477 1478 1479 1480 1481 1482
		if (group && smmu->s2crs[idx].group &&
		    group != smmu->s2crs[idx].group)
			return ERR_PTR(-EINVAL);

		group = smmu->s2crs[idx].group;
	}

	if (group)
		return group;
1483 1484 1485 1486 1487 1488 1489 1490 1491

	if (dev_is_pci(dev))
		group = pci_device_group(dev);
	else
		group = generic_device_group(dev);

	return group;
}

1492 1493 1494
static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
				    enum iommu_attr attr, void *data)
{
1495
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508

	switch (attr) {
	case DOMAIN_ATTR_NESTING:
		*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
		return 0;
	default:
		return -ENODEV;
	}
}

static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
				    enum iommu_attr attr, void *data)
{
1509
	int ret = 0;
1510
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1511

1512 1513
	mutex_lock(&smmu_domain->init_mutex);

1514 1515
	switch (attr) {
	case DOMAIN_ATTR_NESTING:
1516 1517 1518 1519 1520
		if (smmu_domain->smmu) {
			ret = -EPERM;
			goto out_unlock;
		}

1521 1522 1523 1524 1525
		if (*(int *)data)
			smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
		else
			smmu_domain->stage = ARM_SMMU_DOMAIN_S1;

1526
		break;
1527
	default:
1528
		ret = -ENODEV;
1529
	}
1530 1531 1532 1533

out_unlock:
	mutex_unlock(&smmu_domain->init_mutex);
	return ret;
1534 1535
}

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548
static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
{
	u32 fwid = 0;

	if (args->args_count > 0)
		fwid |= (u16)args->args[0];

	if (args->args_count > 1)
		fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;

	return iommu_fwspec_add_ids(dev, &fwid, 1);
}

1549
static struct iommu_ops arm_smmu_ops = {
1550
	.capable		= arm_smmu_capable,
1551 1552
	.domain_alloc		= arm_smmu_domain_alloc,
	.domain_free		= arm_smmu_domain_free,
1553 1554 1555
	.attach_dev		= arm_smmu_attach_dev,
	.map			= arm_smmu_map,
	.unmap			= arm_smmu_unmap,
1556
	.map_sg			= default_iommu_map_sg,
1557 1558 1559
	.iova_to_phys		= arm_smmu_iova_to_phys,
	.add_device		= arm_smmu_add_device,
	.remove_device		= arm_smmu_remove_device,
1560
	.device_group		= arm_smmu_device_group,
1561 1562
	.domain_get_attr	= arm_smmu_domain_get_attr,
	.domain_set_attr	= arm_smmu_domain_set_attr,
1563
	.of_xlate		= arm_smmu_of_xlate,
1564
	.pgsize_bitmap		= -1UL, /* Restricted during device attach */
1565 1566 1567 1568 1569
};

static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
{
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1570
	void __iomem *cb_base;
1571
	int i;
1572
	u32 reg, major;
1573

1574 1575 1576
	/* clear global FSR */
	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1577

1578 1579 1580 1581
	/*
	 * Reset stream mapping groups: Initial values mark all SMRn as
	 * invalid and all S2CRn as bypass unless overridden.
	 */
1582 1583
	for (i = 0; i < smmu->num_mapping_groups; ++i)
		arm_smmu_write_sme(smmu, i);
1584

1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597
	/*
	 * Before clearing ARM_MMU500_ACTLR_CPRE, need to
	 * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
	 * bit is only present in MMU-500r2 onwards.
	 */
	reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
	major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
	if ((smmu->model == ARM_MMU500) && (major >= 2)) {
		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
		reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
	}

1598 1599 1600 1601 1602
	/* Make sure all context banks are disabled and clear CB_FSR  */
	for (i = 0; i < smmu->num_context_banks; ++i) {
		cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1603 1604 1605 1606 1607 1608 1609 1610 1611
		/*
		 * Disable MMU-500's not-particularly-beneficial next-page
		 * prefetcher for the sake of errata #841119 and #826419.
		 */
		if (smmu->model == ARM_MMU500) {
			reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
			reg &= ~ARM_MMU500_ACTLR_CPRE;
			writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
		}
1612
	}
1613

1614 1615 1616 1617
	/* Invalidate the TLB, just in case */
	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);

1618
	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1619

1620
	/* Enable fault reporting */
1621
	reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1622 1623

	/* Disable TLB broadcasting. */
1624
	reg |= (sCR0_VMIDPNE | sCR0_PTM);
1625

1626 1627 1628 1629 1630 1631
	/* Enable client access, handling unmatched streams as appropriate */
	reg &= ~sCR0_CLIENTPD;
	if (disable_bypass)
		reg |= sCR0_USFCFG;
	else
		reg &= ~sCR0_USFCFG;
1632 1633

	/* Disable forced broadcasting */
1634
	reg &= ~sCR0_FB;
1635 1636

	/* Don't upgrade barriers */
1637
	reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1638

1639 1640 1641
	if (smmu->features & ARM_SMMU_FEAT_VMID16)
		reg |= sCR0_VMID16EN;

1642
	/* Push the button */
1643
	__arm_smmu_tlb_sync(smmu);
1644
	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670
}

static int arm_smmu_id_size_to_bits(int size)
{
	switch (size) {
	case 0:
		return 32;
	case 1:
		return 36;
	case 2:
		return 40;
	case 3:
		return 42;
	case 4:
		return 44;
	case 5:
	default:
		return 48;
	}
}

static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
{
	unsigned long size;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
	u32 id;
1671
	bool cttw_dt, cttw_reg;
1672
	int i;
1673 1674

	dev_notice(smmu->dev, "probing hardware configuration...\n");
1675 1676
	dev_notice(smmu->dev, "SMMUv%d with:\n",
			smmu->version == ARM_SMMU_V2 ? 2 : 1);
1677 1678 1679

	/* ID0 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1680 1681 1682 1683 1684 1685 1686

	/* Restrict available stages based on module parameter */
	if (force_stage == 1)
		id &= ~(ID0_S2TS | ID0_NTS);
	else if (force_stage == 2)
		id &= ~(ID0_S1TS | ID0_NTS);

1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702
	if (id & ID0_S1TS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
		dev_notice(smmu->dev, "\tstage 1 translation\n");
	}

	if (id & ID0_S2TS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
		dev_notice(smmu->dev, "\tstage 2 translation\n");
	}

	if (id & ID0_NTS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
		dev_notice(smmu->dev, "\tnested translation\n");
	}

	if (!(smmu->features &
1703
		(ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1704 1705 1706 1707
		dev_err(smmu->dev, "\tno translation support!\n");
		return -ENODEV;
	}

1708 1709
	if ((id & ID0_S1TS) &&
		((smmu->version < ARM_SMMU_V2) || !(id & ID0_ATOSNS))) {
1710 1711 1712 1713
		smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
		dev_notice(smmu->dev, "\taddress translation ops\n");
	}

1714 1715 1716 1717 1718 1719 1720 1721 1722
	/*
	 * In order for DMA API calls to work properly, we must defer to what
	 * the DT says about coherency, regardless of what the hardware claims.
	 * Fortunately, this also opens up a workaround for systems where the
	 * ID register value has ended up configured incorrectly.
	 */
	cttw_dt = of_dma_is_coherent(smmu->dev->of_node);
	cttw_reg = !!(id & ID0_CTTW);
	if (cttw_dt)
1723
		smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1724 1725 1726 1727 1728 1729
	if (cttw_dt || cttw_reg)
		dev_notice(smmu->dev, "\t%scoherent table walk\n",
			   cttw_dt ? "" : "non-");
	if (cttw_dt != cttw_reg)
		dev_notice(smmu->dev,
			   "\t(IDR0.CTTW overridden by dma-coherent property)\n");
1730

1731 1732 1733
	/* Max. number of entries we have for stream matching/indexing */
	size = 1 << ((id >> ID0_NUMSIDB_SHIFT) & ID0_NUMSIDB_MASK);
	smmu->streamid_mask = size - 1;
1734
	if (id & ID0_SMS) {
1735
		u32 smr;
1736 1737

		smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1738 1739
		size = (id >> ID0_NUMSMRG_SHIFT) & ID0_NUMSMRG_MASK;
		if (size == 0) {
1740 1741 1742 1743 1744
			dev_err(smmu->dev,
				"stream-matching supported, but no SMRs present!\n");
			return -ENODEV;
		}

1745 1746 1747 1748 1749 1750
		/*
		 * SMR.ID bits may not be preserved if the corresponding MASK
		 * bits are set, so check each one separately. We can reject
		 * masters later if they try to claim IDs outside these masks.
		 */
		smr = smmu->streamid_mask << SMR_ID_SHIFT;
1751 1752
		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1753
		smmu->streamid_mask = smr >> SMR_ID_SHIFT;
1754

1755 1756 1757 1758
		smr = smmu->streamid_mask << SMR_MASK_SHIFT;
		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
		smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
1759

1760 1761 1762 1763 1764 1765
		/* Zero-initialised to mark as invalid */
		smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs),
					  GFP_KERNEL);
		if (!smmu->smrs)
			return -ENOMEM;

1766
		dev_notice(smmu->dev,
1767 1768
			   "\tstream matching with %lu register groups, mask 0x%x",
			   size, smmu->smr_mask_mask);
1769
	}
1770 1771 1772 1773 1774 1775 1776 1777
	/* s2cr->type == 0 means translation, so initialise explicitly */
	smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs),
					 GFP_KERNEL);
	if (!smmu->s2crs)
		return -ENOMEM;
	for (i = 0; i < size; i++)
		smmu->s2crs[i] = s2cr_init_val;

1778
	smmu->num_mapping_groups = size;
1779
	mutex_init(&smmu->stream_map_mutex);
1780

1781 1782 1783 1784 1785 1786
	if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
		smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
		if (!(id & ID0_PTFS_NO_AARCH32S))
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S;
	}

1787 1788
	/* ID1 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1789
	smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1790

1791
	/* Check for size mismatch of SMMU address space from mapped region */
1792
	size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1793
	size *= 2 << smmu->pgshift;
1794
	if (smmu->size != size)
1795 1796 1797
		dev_warn(smmu->dev,
			"SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
			size, smmu->size);
1798

1799
	smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1800 1801 1802 1803 1804 1805 1806
	smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
	if (smmu->num_s2_context_banks > smmu->num_context_banks) {
		dev_err(smmu->dev, "impossible number of S2 context banks!\n");
		return -ENODEV;
	}
	dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
		   smmu->num_context_banks, smmu->num_s2_context_banks);
1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817
	/*
	 * Cavium CN88xx erratum #27704.
	 * Ensure ASID and VMID allocation is unique across all SMMUs in
	 * the system.
	 */
	if (smmu->model == CAVIUM_SMMUV2) {
		smmu->cavium_id_base =
			atomic_add_return(smmu->num_context_banks,
					  &cavium_smmu_context_count);
		smmu->cavium_id_base -= smmu->num_context_banks;
	}
1818 1819 1820 1821

	/* ID2 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
	size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1822
	smmu->ipa_size = size;
1823

1824
	/* The output mask is also applied for bypass */
1825
	size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1826
	smmu->pa_size = size;
1827

1828 1829 1830
	if (id & ID2_VMID16)
		smmu->features |= ARM_SMMU_FEAT_VMID16;

1831 1832 1833 1834 1835 1836 1837 1838 1839
	/*
	 * What the page table walker can address actually depends on which
	 * descriptor format is in use, but since a) we don't know that yet,
	 * and b) it can vary per context bank, this will have to do...
	 */
	if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
		dev_warn(smmu->dev,
			 "failed to set DMA mask for table walker\n");

1840
	if (smmu->version < ARM_SMMU_V2) {
1841
		smmu->va_size = smmu->ipa_size;
1842 1843
		if (smmu->version == ARM_SMMU_V1_64K)
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1844 1845
	} else {
		size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1846 1847
		smmu->va_size = arm_smmu_id_size_to_bits(size);
		if (id & ID2_PTFS_4K)
1848
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K;
1849
		if (id & ID2_PTFS_16K)
1850
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K;
1851
		if (id & ID2_PTFS_64K)
1852
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1853 1854
	}

1855 1856
	/* Now we've corralled the various formats, what'll it do? */
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S)
1857
		smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
1858 1859
	if (smmu->features &
	    (ARM_SMMU_FEAT_FMT_AARCH32_L | ARM_SMMU_FEAT_FMT_AARCH64_4K))
1860
		smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
1861
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K)
1862
		smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
1863
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K)
1864 1865 1866 1867 1868 1869 1870 1871
		smmu->pgsize_bitmap |= SZ_64K | SZ_512M;

	if (arm_smmu_ops.pgsize_bitmap == -1UL)
		arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
	else
		arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
	dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n",
		   smmu->pgsize_bitmap);
1872

1873

1874 1875
	if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
		dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1876
			   smmu->va_size, smmu->ipa_size);
1877 1878 1879

	if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
		dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1880
			   smmu->ipa_size, smmu->pa_size);
1881

1882 1883 1884
	return 0;
}

1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
struct arm_smmu_match_data {
	enum arm_smmu_arch_version version;
	enum arm_smmu_implementation model;
};

#define ARM_SMMU_MATCH_DATA(name, ver, imp)	\
static struct arm_smmu_match_data name = { .version = ver, .model = imp }

ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
1895
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
1896
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
1897
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
1898
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
1899

1900
static const struct of_device_id arm_smmu_of_match[] = {
1901 1902 1903
	{ .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
	{ .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
	{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
1904
	{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
1905
	{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
1906
	{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1907
	{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
1908 1909 1910 1911
	{ },
};
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);

1912 1913
static int arm_smmu_device_dt_probe(struct platform_device *pdev)
{
1914
	const struct arm_smmu_match_data *data;
1915 1916 1917 1918
	struct resource *res;
	struct arm_smmu_device *smmu;
	struct device *dev = &pdev->dev;
	int num_irqs, i, err;
1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931
	bool legacy_binding;

	legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL);
	if (legacy_binding && !using_generic_binding) {
		if (!using_legacy_binding)
			pr_notice("deprecated \"mmu-masters\" DT property in use; DMA API support unavailable\n");
		using_legacy_binding = true;
	} else if (!legacy_binding && !using_legacy_binding) {
		using_generic_binding = true;
	} else {
		dev_err(dev, "not probing due to mismatched DT properties\n");
		return -ENODEV;
	}
1932 1933 1934 1935 1936 1937 1938 1939

	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
	if (!smmu) {
		dev_err(dev, "failed to allocate arm_smmu_device\n");
		return -ENOMEM;
	}
	smmu->dev = dev;

1940
	data = of_device_get_match_data(dev);
1941 1942
	smmu->version = data->version;
	smmu->model = data->model;
1943

1944
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1945 1946 1947
	smmu->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(smmu->base))
		return PTR_ERR(smmu->base);
1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
	smmu->size = resource_size(res);

	if (of_property_read_u32(dev->of_node, "#global-interrupts",
				 &smmu->num_global_irqs)) {
		dev_err(dev, "missing #global-interrupts property\n");
		return -ENODEV;
	}

	num_irqs = 0;
	while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
		num_irqs++;
		if (num_irqs > smmu->num_global_irqs)
			smmu->num_context_irqs++;
	}

1963 1964 1965 1966
	if (!smmu->num_context_irqs) {
		dev_err(dev, "found %d interrupts but expected at least %d\n",
			num_irqs, smmu->num_global_irqs + 1);
		return -ENODEV;
1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
	}

	smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
				  GFP_KERNEL);
	if (!smmu->irqs) {
		dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
		return -ENOMEM;
	}

	for (i = 0; i < num_irqs; ++i) {
		int irq = platform_get_irq(pdev, i);
1978

1979 1980 1981 1982 1983 1984 1985
		if (irq < 0) {
			dev_err(dev, "failed to get irq index %d\n", i);
			return -ENODEV;
		}
		smmu->irqs[i] = irq;
	}

1986 1987 1988 1989
	err = arm_smmu_device_cfg_probe(smmu);
	if (err)
		return err;

1990 1991
	parse_driver_options(smmu);

1992
	if (smmu->version == ARM_SMMU_V2 &&
1993 1994 1995 1996
	    smmu->num_context_banks != smmu->num_context_irqs) {
		dev_err(dev,
			"found only %d context interrupt(s) but %d required\n",
			smmu->num_context_irqs, smmu->num_context_banks);
1997
		return -ENODEV;
1998 1999 2000
	}

	for (i = 0; i < smmu->num_global_irqs; ++i) {
2001 2002 2003 2004 2005
		err = devm_request_irq(smmu->dev, smmu->irqs[i],
				       arm_smmu_global_fault,
				       IRQF_SHARED,
				       "arm-smmu global fault",
				       smmu);
2006 2007 2008
		if (err) {
			dev_err(dev, "failed to request global IRQ %d (%u)\n",
				i, smmu->irqs[i]);
2009
			return err;
2010 2011 2012
		}
	}

2013
	of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
2014
	platform_set_drvdata(pdev, smmu);
2015
	arm_smmu_device_reset(smmu);
2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029

	/* Oh, for a proper bus abstraction */
	if (!iommu_present(&platform_bus_type))
		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
#ifdef CONFIG_ARM_AMBA
	if (!iommu_present(&amba_bustype))
		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
#endif
#ifdef CONFIG_PCI
	if (!iommu_present(&pci_bus_type)) {
		pci_request_acs();
		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
	}
#endif
2030 2031 2032 2033 2034
	return 0;
}

static int arm_smmu_device_remove(struct platform_device *pdev)
{
2035
	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
2036 2037 2038 2039

	if (!smmu)
		return -ENODEV;

2040
	if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2041
		dev_err(&pdev->dev, "removing device with active domains!\n");
2042 2043

	/* Turn the thing off */
2044
	writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058
	return 0;
}

static struct platform_driver arm_smmu_driver = {
	.driver	= {
		.name		= "arm-smmu",
		.of_match_table	= of_match_ptr(arm_smmu_of_match),
	},
	.probe	= arm_smmu_device_dt_probe,
	.remove	= arm_smmu_device_remove,
};

static int __init arm_smmu_init(void)
{
2059 2060
	static bool registered;
	int ret = 0;
2061

2062 2063 2064
	if (!registered) {
		ret = platform_driver_register(&arm_smmu_driver);
		registered = !ret;
2065
	}
2066
	return ret;
2067 2068 2069 2070 2071 2072 2073
}

static void __exit arm_smmu_exit(void)
{
	return platform_driver_unregister(&arm_smmu_driver);
}

2074
subsys_initcall(arm_smmu_init);
2075 2076
module_exit(arm_smmu_exit);

2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
static int __init arm_smmu_of_init(struct device_node *np)
{
	int ret = arm_smmu_init();

	if (ret)
		return ret;

	if (!of_platform_device_create(np, NULL, platform_bus_type.dev_root))
		return -ENODEV;

	return 0;
}
IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", arm_smmu_of_init);
IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", arm_smmu_of_init);
IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", arm_smmu_of_init);
IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);

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MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
MODULE_LICENSE("GPL v2");