• Christoffer Dall's avatar
    arm/arm64: KVM: Rework the arch timer to use level-triggered semantics · 4b4b4512
    Christoffer Dall authored
    The arch timer currently uses edge-triggered semantics in the sense that
    the line is never sampled by the vgic and lowering the line from the
    timer to the vgic doesn't have any effect on the pending state of
    virtual interrupts in the vgic.  This means that we do not support a
    guest with the otherwise valid behavior of (1) disable interrupts (2)
    enable the timer (3) disable the timer (4) enable interrupts.  Such a
    guest would validly not expect to see any interrupts on real hardware,
    but will see interrupts on KVM.
    
    This patch fixes this shortcoming through the following series of
    changes.
    
    First, we change the flow of the timer/vgic sync/flush operations.  Now
    the timer is always flushed/synced before the vgic, because the vgic
    samples the state of the timer output.  This has the implication that we
    move the timer operations in to non-preempible sections, but that is
    fine after the previous commit getting rid of hrtimer schedules on every
    entry/exit.
    
    Second, we change the internal behavior of the timer, letting the timer
    keep track of its previous output state, and only lower/raise the line
    to the vgic when the state changes.  Note that in theory this could have
    been accomplished more simply by signalling the vgic every time the
    state *potentially* changed, but we don't want to be hitting the vgic
    more often than necessary.
    
    Third, we get rid of the use of the map->active field in the vgic and
    instead simply set the interrupt as active on the physical distributor
    whenever the input to the GIC is asserted and conversely clear the
    physical active state when the input to the GIC is deasserted.
    
    Fourth, and finally, we now initialize the timer PPIs (and all the other
    unused PPIs for now), to be level-triggered, and modify the sync code to
    sample the line state on HW sync and re-inject a new interrupt if it is
    still pending at that time.
    Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
    4b4b4512
arm_arch_timer.h 2.19 KB