• Stephane Eranian's avatar
    perf_events, x86: AMD event scheduling · 38331f62
    Stephane Eranian authored
    This patch adds correct AMD NorthBridge event scheduling.
    
    NB events are events measuring L3 cache, Hypertransport traffic. They are
    identified by an event code >= 0xe0. They measure events on the
    Northbride which is shared by all cores on a package. NB events are
    counted on a shared set of counters. When a NB event is programmed in a
    counter, the data actually comes from a shared counter. Thus, access to
    those counters needs to be synchronized.
    
    We implement the synchronization such that no two cores can be measuring
    NB events using the same counters. Thus, we maintain a per-NB allocation
    table. The available slot is propagated using the event_constraint
    structure.
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
    LKML-Reference: <4b703957.0702d00a.6bf2.7b7d@mx.google.com>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    38331f62
perf_event.c 126 KB