• Xiong Zhang's avatar
    drm/i915: Add ppgtt to GVT GEM context · 4f15665c
    Xiong Zhang authored
    Currently the guest couldn't boot up under GVT-g environment as the
    following call trace exists:
    [  272.504762] BUG: unable to handle kernel NULL pointer dereference at 0000000000000100
    [  272.504834] Call Trace:
    [  272.504852]  execlists_context_pin+0x2b2/0x520 [i915]
    [  272.504869]  intel_gvt_scan_and_shadow_workload+0x50/0x4d0 [i915]
    [  272.504887]  intel_vgpu_create_workload+0x3e2/0x570 [i915]
    [  272.504901]  intel_vgpu_submit_execlist+0xc0/0x2a0 [i915]
    [  272.504916]  elsp_mmio_write+0xc7/0x130 [i915]
    [  272.504930]  intel_vgpu_mmio_reg_rw+0x24a/0x4c0 [i915]
    [  272.504944]  intel_vgpu_emulate_mmio_write+0xac/0x240 [i915]
    [  272.504947]  intel_vgpu_rw+0x22d/0x270 [kvmgt]
    [  272.504949]  intel_vgpu_write+0x164/0x1f0 [kvmgt]
    
    GVT GEM context is created by i915_gem_context_create_gvt() which
    doesn't allocate ppgtt. So GVT GEM context structure doesn't have
    a valid i915_hw_ppgtt.
    
    This patch create ppgtt table at GVT GEM context creation, then assign
    shadow ppgtt's root table address to this ppgtt when shadow ppgtt will
    be used on GPU. So GVT GEM context has valid ppgtt address. But note
    that this ppgtt only contain valid ppgtt root table address, the table
    entry in this ppgtt structure are invalid.
    
    Fixes:4a3d3f67("drm/i915: Match code to comment and enforce ppgtt for execlists")
    Signed-off-by: default avatarXiong Zhang <xiong.y.zhang@intel.com>
    Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/1539841231-3157-1-git-send-email-xiong.y.zhang@intel.com
    4f15665c
i915_gem_context.c 27.5 KB