• Yijing Wang's avatar
    PCI: Add dev->has_secondary_link to track downstream PCIe links · 517a021f
    Yijing Wang authored
    [ Upstream commit d0751b98 ]
    
    A PCIe Port is an interface to a Link.  A Root Port is a PCI-PCI bridge in
    a Root Complex and has a Link on its secondary (downstream) side.  For
    other Ports, the Link may be on either the upstream (closer to the Root
    Complex) or downstream side of the Port.
    
    The usual topology has a Root Port connected to an Upstream Port.  We
    previously assumed this was the only possible topology, and that a
    Downstream Port's Link was always on its downstream side, like this:
    
                      +---------------------+
      +------+        |          Downstream |
      | Root |        | Upstream       Port +--Link--
      | Port +--Link--+ Port                |
      +------+        |          Downstream |
                      |                Port +--Link--
                      +---------------------+
    
    But systems do exist (see URL below) where the Root Port is connected to a
    Downstream Port.  In this case, a Downstream Port's Link may be on either
    the upstream or downstream side:
    
                      +---------------------+
      +------+        |            Upstream |
      | Root |        | Downstream     Port +--Link--
      | Port +--Link--+ Port                |
      +------+        |          Downstream |
                      |                Port +--Link--
                      +---------------------+
    
    We can't use the Port type to determine which side the Link is on, so add a
    bit in struct pci_dev to keep track.
    
    A Root Port's Link is always on the Port's secondary side.  A component
    (Endpoint or Port) on the other end of the Link obviously has the Link on
    its upstream side.  If that component is a Port, it is part of a Switch or
    a Bridge.  A Bridge has a PCI or PCI-X bus on its secondary side, not a
    Link.  The internal bus of a Switch connects the Port to another Port whose
    Link is on the downstream side.
    
    [bhelgaas: changelog, comment, cache "type", use if/else]
    Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.com
    Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361Suggested-by: default avatarBjorn Helgaas <bhelgaas@google.com>
    Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
    Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
    Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
    517a021f
probe.c 57.8 KB