• Varun Sethi's avatar
    powerpc/mpic: FSL MPIC error interrupt support. · 0a408164
    Varun Sethi authored
    All SOC device error interrupts are muxed and delivered to the core
    as a single MPIC error interrupt. Currently all the device drivers
    requiring access to device errors have to register for the MPIC error
    interrupt as a shared interrupt.
    
    With this patch we add interrupt demuxing capability in the mpic driver,
    allowing device drivers to register for their individual error interrupts.
    This is achieved by handling error interrupts in a cascaded fashion.
    
    MPIC error interrupt is handled by the "error_int_handler", which
    subsequently demuxes it using the EISR and delivers it to the respective
    drivers.
    
    The error interrupt capability is dependent on the MPIC EIMR register,
    which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error
    interrupt demuxing capability is dependent on the MPIC version and can
    be used for versions >= 4.1.
    Signed-off-by: default avatarVarun Sethi <Varun.Sethi@freescale.com>
    Signed-off-by: default avatarBogdan Hamciuc <bogdan.hamciuc@freescale.com>
    Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    0a408164
mpic.c 50.1 KB