• Daniel Vetter's avatar
    drm/i915: hw state readout and cross-checking for shared dplls · 66e985c0
    Daniel Vetter authored
    Just the plumbing, all the modeset and enable code has not yet been
    switched over to use the new state. It seems to be decently broken
    anyway, at least wrt to handling of the special pixel mutliplier
    enabling sequence. Follow-up patches will clean up that mess.
    
    Another missing piece is more careful handling (and fixup) of the fp1
    alternate divisor state. The BIOS most likely doesn't bother to
    program that one to what we expect. So we need to be more careful with
    comparing that state, both for cross checking but also when checking
    for dpll sharing when acquiring shared dpll. Otherwise fastboot will
    deny a few shared dpll configurations which would otherwise work.
    
    v2: We need to memcpy the pipe config dpll hw state into the pll, for
    otherwise the cross-check code will get angry.
    
    v3: Don't forget to read the pch pll state in the crtc get_pipe_config
    function for ibx/ilk platforms.
    Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    66e985c0
intel_drv.h 27.7 KB