When enabling the core, make sure DRP (Dynamic Reconfiguration Port)
is locked. Most of the designs don't really use it but we still get the
lock bit set. So let's do it all the time so the code is generic.

While at it reduce the timeout time to 1 microsecond as it seems to be
enough and goes in line with what we have on the similar DAC core
(adi-axi-dac).
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240531-dev-axi-adc-drp-v3-2-e3fa79447c67@analog.comSigned-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>