• Mathieu Desnoyers's avatar
    Introduce cpu_dcache_is_aliasing() across all architectures · 8690bbcf
    Mathieu Desnoyers authored
    Introduce a generic way to query whether the data cache is virtually
    aliased on all architectures. Its purpose is to ensure that subsystems
    which are incompatible with virtually aliased data caches (e.g. FS_DAX)
    can reliably query this.
    
    For data cache aliasing, there are three scenarios dependending on the
    architecture. Here is a breakdown based on my understanding:
    
    A) The data cache is always aliasing:
    
    * arc
    * csky
    * m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.)
    * sh
    * parisc
    
    B) The data cache aliasing is statically known or depends on querying CPU
       state at runtime:
    
    * arm (cache_is_vivt() || cache_is_vipt_aliasing())
    * mips (cpu_has_dc_aliases)
    * nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE)
    * sparc32 (vac_cache_size > PAGE_SIZE)
    * sparc64 (L1DCACHE_SIZE > PAGE_SIZE)
    * xtensa (DCACHE_WAY_SIZE > PAGE_SIZE)
    
    C) The data cache is never aliasing:
    
    * alpha
    * arm64 (aarch64)
    * hexagon
    * loongarch (but with incoherent write buffers, which are disabled since
                 commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE"))
    * microblaze
    * openrisc
    * powerpc
    * riscv
    * s390
    * um
    * x86
    
    Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and
    implement "cpu_dcache_is_aliasing()".
    
    Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus
    cpu_dcache_is_aliasing() simply evaluates to "false".
    
    Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future
    work. This would be useful to gate features like XIP on architectures
    which have aliasing CPU dcache-icache but not CPU dcache-dcache.
    
    Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache"
    to clarify that we really mean "CPU data cache" and "CPU cache" to
    eliminate any possible confusion with VFS "dentry cache" and "page
    cache".
    
    Link: https://lore.kernel.org/lkml/20030910210416.GA24258@mail.jlokier.co.uk/
    Link: https://lkml.kernel.org/r/20240215144633.96437-9-mathieu.desnoyers@efficios.com
    Fixes: d92576f1 ("dax: does not work correctly with virtual aliasing caches")
    Signed-off-by: default avatarMathieu Desnoyers <mathieu.desnoyers@efficios.com>
    Cc: Dan Williams <dan.j.williams@intel.com>
    Cc: Vishal Verma <vishal.l.verma@intel.com>
    Cc: Dave Jiang <dave.jiang@intel.com>
    Cc: Matthew Wilcox <willy@infradead.org>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Russell King <linux@armlinux.org.uk>
    Cc: Alasdair Kergon <agk@redhat.com>
    Cc: Christoph Hellwig <hch@lst.de>
    Cc: Dave Chinner <david@fromorbit.com>
    Cc: Heiko Carstens <hca@linux.ibm.com>
    Cc: kernel test robot <lkp@intel.com>
    Cc: Michael Sclafani <dm-devel@lists.linux.dev>
    Cc: Mike Snitzer <snitzer@kernel.org>
    Cc: Mikulas Patocka <mpatocka@redhat.com>
    Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
    8690bbcf
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