• Stephane Eranian's avatar
    perf/x86: Add memory profiling via PEBS Load Latency · f20093ee
    Stephane Eranian authored
    This patch adds support for memory profiling using the
    PEBS Load Latency facility.
    
    Load accesses are sampled by HW and the instruction
    address, data address, load latency, data source, tlb,
    locked information can be saved in the sampling buffer
    if using the PERF_SAMPLE_COST (for latency),
    PERF_SAMPLE_ADDR, PERF_SAMPLE_DATA_SRC types.
    
    To enable PEBS Load Latency, users have to use the
    model specific event:
    
     - on NHM/WSM: MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD
     - on SNB/IVB: MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD
    
    To make things easier, this patch also exports a generic
    alias via sysfs: mem-loads. It export the right event
    encoding based on the host CPU and can be used directly
    by the perf tool.
    
    Loosely based on Intel's Lin Ming patch posted on LKML
    in July 2011.
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Cc: peterz@infradead.org
    Cc: ak@linux.intel.com
    Cc: acme@redhat.com
    Cc: jolsa@redhat.com
    Cc: namhyung.kim@lge.com
    Link: http://lkml.kernel.org/r/1359040242-8269-9-git-send-email-eranian@google.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
    f20093ee
msr-index.h 18.8 KB