• Linus Torvalds's avatar
    Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl · e62f81bb
    Linus Torvalds authored
    Pull CXL updates from Dave Jiang:
     "Core:
    
       - A CXL maturity map has been added to the documentation to detail
         the current state of CXL enabling.
    
         It provides the status of the current state of various CXL features
         to inform current and future contributors of where things are and
         which areas need contribution.
    
       - A notifier handler has been added in order for a newly created CXL
         memory region to trigger the abstract distance metrics calculation.
    
         This should bring parity for CXL memory to the same level vs
         hotplugged DRAM for NUMA abstract distance calculation. The
         abstract distance reflects relative performance used for memory
         tiering handling.
    
       - An addition for XOR math has been added to address the CXL DPA to
         SPA translation.
    
         CXL address translation did not support address interleave math
         with XOR prior to this change.
    
      Fixes:
    
       - Fix to address race condition in the CXL memory hotplug notifier
    
       - Add missing MODULE_DESCRIPTION() for CXL modules
    
       - Fix incorrect vendor debug UUID define
    
      Misc:
    
       - A warning has been added to inform users of an unsupported
         configuration when mixing CXL VH and RCH/RCD hierarchies
    
       - The ENXIO error code has been replaced with EBUSY for inject poison
         limit reached via debugfs and cxl-test support
    
       - Moving the PCI config read in cxl_dvsec_rr_decode() to avoid
         unnecessary PCI config reads
    
       - A refactor to a common struct for DRAM and general media CXL
         events"
    
    * tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
      cxl/core/pci: Move reading of control register to immediately before usage
      cxl: Remove defunct code calculating host bridge target positions
      cxl/region: Verify target positions using the ordered target list
      cxl: Restore XOR'd position bits during address translation
      cxl/core: Fold cxl_trace_hpa() into cxl_dpa_to_hpa()
      cxl/test: Replace ENXIO with EBUSY for inject poison limit reached
      cxl/memdev: Replace ENXIO with EBUSY for inject poison limit reached
      cxl/acpi: Warn on mixed CXL VH and RCH/RCD Hierarchy
      cxl/core: Fix incorrect vendor debug UUID define
      Documentation: CXL Maturity Map
      cxl/region: Simplify cxl_region_nid()
      cxl/region: Support to calculate memory tier abstract distance
      cxl/region: Fix a race condition in memory hotplug notifier
      cxl: add missing MODULE_DESCRIPTION() macros
      cxl/events: Use a common struct for DRAM and General Media events
    e62f81bb
port.c 57.7 KB