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Commit 0015cce5 authored by David Galiffi's avatar David Galiffi Committed by Alex Deucher
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drm/amd/display: Fix disabling dccg clocks 

[How & Why]
Updated procedure to match hardware programming guide.
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarEric Yang <Eric.Yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarDavid Galiffi <David.Galiffi@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f6a3795d
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Inline Side-by-side
Showing with 37 additions and 15 deletions
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
View file @ 0015cce5
...@@ -183,8 +183,14 @@ ...@@ -183,8 +183,14 @@
type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
type SYMCLK32_SE0_GATE_DISABLE;\
type SYMCLK32_SE1_GATE_DISABLE;\
type SYMCLK32_SE2_GATE_DISABLE;\
type SYMCLK32_SE3_GATE_DISABLE;\
type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
type SYMCLK32_LE0_GATE_DISABLE;\
type SYMCLK32_LE1_GATE_DISABLE;\
type DPSTREAMCLK_ROOT_GATE_DISABLE;\ type DPSTREAMCLK_ROOT_GATE_DISABLE;\
type DPSTREAMCLK_GATE_DISABLE;\ type DPSTREAMCLK_GATE_DISABLE;\
type HDMISTREAMCLK0_DTO_PHASE;\ type HDMISTREAMCLK0_DTO_PHASE;\
...@@ -233,6 +239,7 @@ struct dccg_registers { ...@@ -233,6 +239,7 @@ struct dccg_registers {
uint32_t DSCCLK2_DTO_PARAM; uint32_t DSCCLK2_DTO_PARAM;
uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
uint32_t DPSTREAMCLK_GATE_DISABLE; uint32_t DPSTREAMCLK_GATE_DISABLE;
uint32_t DCCG_GATE_DISABLE_CNTL2;
uint32_t DCCG_GATE_DISABLE_CNTL3; uint32_t DCCG_GATE_DISABLE_CNTL3;
uint32_t HDMISTREAMCLK0_DTO_PARAM; uint32_t HDMISTREAMCLK0_DTO_PARAM;
uint32_t DCCG_GATE_DISABLE_CNTL4; uint32_t DCCG_GATE_DISABLE_CNTL4;
......
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
View file @ 0015cce5
...@@ -121,7 +121,8 @@ static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) ...@@ -121,7 +121,8 @@ static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)
return; return;
} }
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
DPSTREAMCLK_GATE_DISABLE, 1,
DPSTREAMCLK_ROOT_GATE_DISABLE, 1); DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
} }
...@@ -130,8 +131,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) ...@@ -130,8 +131,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
DPSTREAMCLK_ROOT_GATE_DISABLE, 0); DPSTREAMCLK_ROOT_GATE_DISABLE, 0,
DPSTREAMCLK_GATE_DISABLE, 0);
switch (otg_inst) { switch (otg_inst) {
case 0: case 0:
...@@ -180,7 +182,8 @@ void dccg31_enable_symclk32_se( ...@@ -180,7 +182,8 @@ void dccg31_enable_symclk32_se(
switch (hpo_se_inst) { switch (hpo_se_inst) {
case 0: case 0:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE0_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE0_GATE_DISABLE, 1); SYMCLK32_ROOT_SE0_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL, REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE0_SRC_SEL, phyd32clk, SYMCLK32_SE0_SRC_SEL, phyd32clk,
...@@ -188,7 +191,8 @@ void dccg31_enable_symclk32_se( ...@@ -188,7 +191,8 @@ void dccg31_enable_symclk32_se(
break; break;
case 1: case 1:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE1_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE1_GATE_DISABLE, 1); SYMCLK32_ROOT_SE1_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL, REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE1_SRC_SEL, phyd32clk, SYMCLK32_SE1_SRC_SEL, phyd32clk,
...@@ -196,7 +200,8 @@ void dccg31_enable_symclk32_se( ...@@ -196,7 +200,8 @@ void dccg31_enable_symclk32_se(
break; break;
case 2: case 2:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE2_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE2_GATE_DISABLE, 1); SYMCLK32_ROOT_SE2_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL, REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE2_SRC_SEL, phyd32clk, SYMCLK32_SE2_SRC_SEL, phyd32clk,
...@@ -204,7 +209,8 @@ void dccg31_enable_symclk32_se( ...@@ -204,7 +209,8 @@ void dccg31_enable_symclk32_se(
break; break;
case 3: case 3:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE3_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE3_GATE_DISABLE, 1); SYMCLK32_ROOT_SE3_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL, REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE3_SRC_SEL, phyd32clk, SYMCLK32_SE3_SRC_SEL, phyd32clk,
...@@ -229,7 +235,8 @@ void dccg31_disable_symclk32_se( ...@@ -229,7 +235,8 @@ void dccg31_disable_symclk32_se(
SYMCLK32_SE0_SRC_SEL, 0, SYMCLK32_SE0_SRC_SEL, 0,
SYMCLK32_SE0_EN, 0); SYMCLK32_SE0_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE0_GATE_DISABLE, 0,
SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);
break; break;
case 1: case 1:
...@@ -237,7 +244,8 @@ void dccg31_disable_symclk32_se( ...@@ -237,7 +244,8 @@ void dccg31_disable_symclk32_se(
SYMCLK32_SE1_SRC_SEL, 0, SYMCLK32_SE1_SRC_SEL, 0,
SYMCLK32_SE1_EN, 0); SYMCLK32_SE1_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE1_GATE_DISABLE, 0,
SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);
break; break;
case 2: case 2:
...@@ -245,7 +253,8 @@ void dccg31_disable_symclk32_se( ...@@ -245,7 +253,8 @@ void dccg31_disable_symclk32_se(
SYMCLK32_SE2_SRC_SEL, 0, SYMCLK32_SE2_SRC_SEL, 0,
SYMCLK32_SE2_EN, 0); SYMCLK32_SE2_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE2_GATE_DISABLE, 0,
SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);
break; break;
case 3: case 3:
...@@ -253,7 +262,8 @@ void dccg31_disable_symclk32_se( ...@@ -253,7 +262,8 @@ void dccg31_disable_symclk32_se(
SYMCLK32_SE3_SRC_SEL, 0, SYMCLK32_SE3_SRC_SEL, 0,
SYMCLK32_SE3_EN, 0); SYMCLK32_SE3_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_SE3_GATE_DISABLE, 0,
SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);
break; break;
default: default:
...@@ -275,7 +285,8 @@ void dccg31_enable_symclk32_le( ...@@ -275,7 +285,8 @@ void dccg31_enable_symclk32_le(
switch (hpo_le_inst) { switch (hpo_le_inst) {
case 0: case 0:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE0_GATE_DISABLE, 1,
SYMCLK32_ROOT_LE0_GATE_DISABLE, 1); SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_LE_CNTL, REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE0_SRC_SEL, phyd32clk, SYMCLK32_LE0_SRC_SEL, phyd32clk,
...@@ -283,7 +294,8 @@ void dccg31_enable_symclk32_le( ...@@ -283,7 +294,8 @@ void dccg31_enable_symclk32_le(
break; break;
case 1: case 1:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE1_GATE_DISABLE, 1,
SYMCLK32_ROOT_LE1_GATE_DISABLE, 1); SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_LE_CNTL, REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE1_SRC_SEL, phyd32clk, SYMCLK32_LE1_SRC_SEL, phyd32clk,
...@@ -308,7 +320,8 @@ void dccg31_disable_symclk32_le( ...@@ -308,7 +320,8 @@ void dccg31_disable_symclk32_le(
SYMCLK32_LE0_SRC_SEL, 0, SYMCLK32_LE0_SRC_SEL, 0,
SYMCLK32_LE0_EN, 0); SYMCLK32_LE0_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE0_GATE_DISABLE, 0,
SYMCLK32_ROOT_LE0_GATE_DISABLE, 0); SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);
break; break;
case 1: case 1:
...@@ -316,7 +329,8 @@ void dccg31_disable_symclk32_le( ...@@ -316,7 +329,8 @@ void dccg31_disable_symclk32_le(
SYMCLK32_LE1_SRC_SEL, 0, SYMCLK32_LE1_SRC_SEL, 0,
SYMCLK32_LE1_EN, 0); SYMCLK32_LE1_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE1_GATE_DISABLE, 0,
SYMCLK32_ROOT_LE1_GATE_DISABLE, 0); SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);
break; break;
default: default:
......
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
View file @ 0015cce5
...@@ -66,6 +66,7 @@ ...@@ -66,6 +66,7 @@
SR(DSCCLK1_DTO_PARAM),\ SR(DSCCLK1_DTO_PARAM),\
SR(DSCCLK2_DTO_PARAM),\ SR(DSCCLK2_DTO_PARAM),\
SR(DSCCLK_DTO_CTRL),\ SR(DSCCLK_DTO_CTRL),\
SR(DCCG_GATE_DISABLE_CNTL2),\
SR(DCCG_GATE_DISABLE_CNTL3),\ SR(DCCG_GATE_DISABLE_CNTL3),\
SR(HDMISTREAMCLK0_DTO_PARAM) SR(HDMISTREAMCLK0_DTO_PARAM)
......
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