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Commit 0028e1e2 authored by Russell King's avatar Russell King
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Merge; remove pci_socket.o from export-objs, add sa1100_pcmcia.o

parents d52a86be 9b4e261a
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Showing with 1597 additions and 44 deletions
arch/arm/Makefile
View file @ 0028e1e2
...@@ -123,6 +123,10 @@ endif ...@@ -123,6 +123,10 @@ endif
MACHINE = sa1100 MACHINE = sa1100
endif endif
ifeq ($(CONFIG_ARCH_PXA),y)
MACHINE = pxa
endif
ifeq ($(CONFIG_ARCH_L7200),y) ifeq ($(CONFIG_ARCH_L7200),y)
MACHINE = l7200 MACHINE = l7200
endif endif
......
arch/arm/boot/Makefile
View file @ 0028e1e2
...@@ -87,6 +87,10 @@ ifeq ($(CONFIG_SA1111),y) ...@@ -87,6 +87,10 @@ ifeq ($(CONFIG_SA1111),y)
endif endif
endif endif
ifeq ($(CONFIG_ARCH_PXA),y)
ZRELADDR = 0xa0008000
endif
ifeq ($(CONFIG_ARCH_ANAKIN),y) ifeq ($(CONFIG_ARCH_ANAKIN),y)
ZRELADDR = 0x20008000 ZRELADDR = 0x20008000
endif endif
......
arch/arm/config.in
View file @ 0028e1e2
...@@ -26,6 +26,7 @@ choice 'ARM system type' \ ...@@ -26,6 +26,7 @@ choice 'ARM system type' \
Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \ Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \
CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \ CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \
Co-EBSA285 CONFIG_ARCH_CO285 \ Co-EBSA285 CONFIG_ARCH_CO285 \
PXA250/210-based CONFIG_ARCH_PXA \
EBSA-110 CONFIG_ARCH_EBSA110 \ EBSA-110 CONFIG_ARCH_EBSA110 \
Epxa10db CONFIG_ARCH_CAMELOT \ Epxa10db CONFIG_ARCH_CAMELOT \
FootBridge CONFIG_ARCH_FOOTBRIDGE \ FootBridge CONFIG_ARCH_FOOTBRIDGE \
...@@ -125,6 +126,16 @@ dep_tristate ' Support for SA11x0 USB character device emulation' CONFIG_SA1100 ...@@ -125,6 +126,16 @@ dep_tristate ' Support for SA11x0 USB character device emulation' CONFIG_SA1100
dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600 dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600
endmenu endmenu
mainmenu_option next_comment
comment 'Intel PXA250/210 Implementations'
dep_bool ' Intel DBPXA250 Development Platform' CONFIG_ARCH_LUBBOCK $CONFIG_ARCH_PXA
dep_bool ' Accelent Xscale IDP' CONFIG_ARCH_PXA_IDP $CONFIG_ARCH_PXA
if [ "$CONFIG_ARCH_LUBBOCK" = "y" ]; then
define_bool CONFIG_SA1111 y
fi
endmenu
mainmenu_option next_comment mainmenu_option next_comment
comment 'CLPS711X/EP721X Implementations' comment 'CLPS711X/EP721X Implementations'
dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X
...@@ -227,7 +238,9 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \ ...@@ -227,7 +238,9 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
else else
define_bool CONFIG_CPU_32v4 n define_bool CONFIG_CPU_32v4 n
fi fi
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then if [ "$CONFIG_ARCH_IOP310" = "y" -o \
"$CONFIG_ARCH_ADIFCC" = "y" -o \
"$CONFIG_ARCH_PXA" = "y" ]; then
define_bool CONFIG_CPU_32v5 y define_bool CONFIG_CPU_32v5 y
else else
define_bool CONFIG_CPU_32v5 n define_bool CONFIG_CPU_32v5 n
...@@ -317,7 +330,9 @@ else ...@@ -317,7 +330,9 @@ else
fi fi
# XScale # XScale
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then if [ "$CONFIG_ARCH_IOP310" = "y" -o \
"$CONFIG_ARCH_ADIFCC" = "y" -o \
"$CONFIG_ARCH_PXA" = "y" ]; then
define_bool CONFIG_CPU_XSCALE y define_bool CONFIG_CPU_XSCALE y
else else
define_bool CONFIG_CPU_XSCALE n define_bool CONFIG_CPU_XSCALE n
...@@ -467,6 +482,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ ...@@ -467,6 +482,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \
"$CONFIG_ARCH_CO285" = "y" -o \ "$CONFIG_ARCH_CO285" = "y" -o \
"$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_SA1100" = "y" -o \
"$CONFIG_ARCH_LUBBOCK" = "y" -o \
"$CONFIG_ARCH_PXA_IDP" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
"$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \
"$CONFIG_ARCH_P720T" = "y" ]; then "$CONFIG_ARCH_P720T" = "y" ]; then
...@@ -477,6 +494,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ ...@@ -477,6 +494,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \
"$CONFIG_ARCH_CO285" = "y" -o \ "$CONFIG_ARCH_CO285" = "y" -o \
"$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_SA1100" = "y" -o \
"$CONFIG_ARCH_LUBBOCK" = "y" -o \
"$CONFIG_ARCH_PXA_IDP" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
"$CONFIG_ARCH_P720T" = "y" ]; then "$CONFIG_ARCH_P720T" = "y" ]; then
bool ' Timer LED' CONFIG_LEDS_TIMER bool ' Timer LED' CONFIG_LEDS_TIMER
......
arch/arm/def-configs/lubbock 0 → 100644
View file @ 0028e1e2
#
# Automatically generated make config: don't edit
#
CONFIG_ARM=y
# CONFIG_EISA is not set
# CONFIG_SBUS is not set
# CONFIG_MCA is not set
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_GENERIC_BUST_SPINLOCK is not set
# CONFIG_GENERIC_ISA_DMA is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_NET=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
# CONFIG_KMOD is not set
#
# System Type
#
# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_ARCA5K is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP310 is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_SHARK is not set
#
# Archimedes/A5000 Implementations
#
#
# Archimedes/A5000 Implementations (select only ONE)
#
# CONFIG_ARCH_ARC is not set
# CONFIG_ARCH_A5K is not set
#
# Footbridge Implementations
#
# CONFIG_ARCH_CATS is not set
# CONFIG_ARCH_PERSONAL_SERVER is not set
# CONFIG_ARCH_EBSA285_ADDIN is not set
# CONFIG_ARCH_EBSA285_HOST is not set
# CONFIG_ARCH_NETWINDER is not set
#
# SA11x0 Implementations
#
# CONFIG_SA1100_ASSABET is not set
# CONFIG_ASSABET_NEPONSET is not set
# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
# CONFIG_SA1100_H3100 is not set
# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_H3800 is not set
# CONFIG_SA1100_H3XXX is not set
# CONFIG_SA1100_EXTENEX1 is not set
# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
# CONFIG_SA1100_GRAPHICSMASTER is not set
# CONFIG_SA1100_BADGE4 is not set
# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
# CONFIG_SA1100_ITSY is not set
# CONFIG_SA1100_LART is not set
# CONFIG_SA1100_NANOENGINE is not set
# CONFIG_SA1100_OMNIMETER is not set
# CONFIG_SA1100_PANGOLIN is not set
# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_PT_SYSTEM3 is not set
# CONFIG_SA1100_SHANNON is not set
# CONFIG_SA1100_SHERMAN is not set
# CONFIG_SA1100_SIMPAD is not set
# CONFIG_SA1100_PFS168 is not set
# CONFIG_SA1100_VICTOR is not set
# CONFIG_SA1100_XP860 is not set
# CONFIG_SA1100_YOPY is not set
# CONFIG_SA1100_STORK is not set
# CONFIG_SA1100_USB is not set
# CONFIG_SA1100_USB_NETLINK is not set
# CONFIG_SA1100_USB_CHAR is not set
# CONFIG_H3600_SLEEVE is not set
#
# Intel PXA250/210 Implementations
#
CONFIG_ARCH_LUBBOCK=y
# CONFIG_ARCH_PXA_IDP is not set
CONFIG_SA1111=y
#
# CLPS711X/EP721X Implementations
#
# CONFIG_ARCH_AUTCPU12 is not set
# CONFIG_ARCH_CDB89712 is not set
# CONFIG_ARCH_CLEP7312 is not set
# CONFIG_ARCH_EDB7211 is not set
# CONFIG_ARCH_P720T is not set
# CONFIG_ARCH_FORTUNET is not set
# CONFIG_ARCH_EP7211 is not set
# CONFIG_ARCH_EP7212 is not set
#
# IOP310 Implementation Options
#
# CONFIG_ARCH_IQ80310 is not set
#
# IOP310 Chipset Features
#
# CONFIG_IOP310_AAU is not set
# CONFIG_IOP310_DMA is not set
# CONFIG_IOP310_MU is not set
# CONFIG_IOP310_PMON is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
# CONFIG_FOOTBRIDGE_ADDIN is not set
CONFIG_CPU_32=y
# CONFIG_CPU_26 is not set
#
# Processor Type
#
# CONFIG_CPU_32v3 is not set
# CONFIG_CPU_32v4 is not set
CONFIG_CPU_32v5=y
# CONFIG_CPU_ARM610 is not set
# CONFIG_CPU_ARM710 is not set
# CONFIG_CPU_ARM720T is not set
# CONFIG_CPU_ARM920T is not set
# CONFIG_CPU_ARM922T is not set
# CONFIG_CPU_ARM926T is not set
# CONFIG_CPU_ARM1020 is not set
# CONFIG_CPU_SA110 is not set
# CONFIG_CPU_SA1100 is not set
CONFIG_CPU_XSCALE=y
CONFIG_XSCALE_CACHE_ERRATA=y
CONFIG_XSCALE_PMU=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
#
# General setup
#
# CONFIG_DISCONTIGMEM is not set
# CONFIG_PCI is not set
# CONFIG_ISA is not set
# CONFIG_ISA_DMA is not set
# CONFIG_FIQ is not set
# CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_HOTPLUG=y
#
# PCMCIA/CardBus support
#
CONFIG_PCMCIA=y
CONFIG_PCMCIA_PROBE=y
# CONFIG_I82092 is not set
# CONFIG_I82365 is not set
# CONFIG_TCIC is not set
# CONFIG_PCMCIA_CLPS6700 is not set
# CONFIG_PCMCIA_SA1100 is not set
CONFIG_PCMCIA_PXA=y
#
# At least one math emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_FASTFPE is not set
CONFIG_KCORE_ELF=y
# CONFIG_KCORE_AOUT is not set
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PM is not set
# CONFIG_PREEMPT is not set
# CONFIG_APM is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
CONFIG_LEDS=y
CONFIG_LEDS_TIMER=y
CONFIG_LEDS_CPU=y
CONFIG_ALIGNMENT_TRAP=y
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_REDBOOT_PARTS=y
# CONFIG_MTD_BOOTLDR_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_B1 is not set
# CONFIG_MTD_CFI_B2 is not set
CONFIG_MTD_CFI_B4=y
# CONFIG_MTD_CFI_I1 is not set
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
# CONFIG_MTD_AMDSTD is not set
# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_JEDEC is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_NORA is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_CDB89712 is not set
# CONFIG_MTD_SA1100 is not set
# CONFIG_MTD_2PARTS_IPAQ is not set
# CONFIG_MTD_DC21285 is not set
# CONFIG_MTD_IQ80310 is not set
CONFIG_MTD_LUBBOCK=y
# CONFIG_MTD_EPXA10DB is not set
# CONFIG_MTD_FORTUNET is not set
# CONFIG_MTD_PCI is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC1000 is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOCPROBE is not set
#
# NAND Flash Device Drivers
#
# CONFIG_MTD_NAND is not set
#
# Plug and Play configuration
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
# CONFIG_PNPBIOS is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_CISS_SCSI_TAPE is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK_DEV is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
#
#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
#
# Appletalk devices
#
# CONFIG_DEV_APPLETALK is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_ARM_AM79C961A is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
CONFIG_NET_VENDOR_SMC=y
# CONFIG_WD80x3 is not set
# CONFIG_ULTRAMCA is not set
# CONFIG_ULTRA is not set
# CONFIG_ULTRA32 is not set
CONFIG_SMC9194=y
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
#
# PCMCIA network device support
#
CONFIG_NET_PCMCIA=y
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_FMVJ18X is not set
CONFIG_PCMCIA_PCNET=y
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_PCMCIA_XIRC2PS is not set
# CONFIG_PCMCIA_AXNET is not set
# CONFIG_ARCNET_COM20020_CS is not set
# CONFIG_PCMCIA_IBMTR is not set
# CONFIG_NET_PCMCIA_RADIO is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
# CONFIG_SCSI is not set
#
# I2O device support
#
# CONFIG_I2O is not set
# CONFIG_I2O_BLOCK is not set
# CONFIG_I2O_LAN is not set
# CONFIG_I2O_SCSI is not set
# CONFIG_I2O_PROC is not set
#
# ISDN subsystem
#
# CONFIG_ISDN_BOOL is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_INPUT_EMU10K1 is not set
# CONFIG_GAMEPORT_PCIGAME is not set
# CONFIG_GAMEPORT_FM801 is not set
# CONFIG_GAMEPORT_CS461x is not set
# CONFIG_SERIO is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
# CONFIG_JOYSTICK_IFORCE_USB is not set
# CONFIG_JOYSTICK_IFORCE_232 is not set
# CONFIG_JOYSTICK_WARRIOR is not set
# CONFIG_JOYSTICK_MAGELLAN is not set
# CONFIG_JOYSTICK_SPACEORB is not set
# CONFIG_JOYSTICK_SPACEBALL is not set
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_DB9 is not set
# CONFIG_JOYSTICK_GAMECON is not set
# CONFIG_JOYSTICK_TURBOGRAFX is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_CS is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_SHARE_IRQ is not set
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_MULTIPORT is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
# CONFIG_ATOMWIDE_SERIAL is not set
# CONFIG_DUALSP_SERIAL is not set
# CONFIG_SERIAL_ANAKIN is not set
# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
# CONFIG_SERIAL_AMBA is not set
# CONFIG_SERIAL_AMBA_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X is not set
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X_OLD_NAME is not set
# CONFIG_SERIAL_21285 is not set
# CONFIG_SERIAL_21285_OLD is not set
# CONFIG_SERIAL_21285_CONSOLE is not set
# CONFIG_SERIAL_UART00 is not set
# CONFIG_SERIAL_UART00_CONSOLE is not set
# CONFIG_SERIAL_SA1100 is not set
# CONFIG_SERIAL_SA1100_CONSOLE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# L3 serial bus support
#
# CONFIG_L3 is not set
# CONFIG_L3_ALGOBIT is not set
# CONFIG_L3_BIT_SA1100_GPIO is not set
#
# Other L3 adapters
#
# CONFIG_L3_SA1111 is not set
# CONFIG_BIT_SA1100_GPIO is not set
#
# Mice
#
CONFIG_BUSMOUSE=y
# CONFIG_ATIXL_BUSMOUSE is not set
# CONFIG_LOGIBUSMOUSE is not set
# CONFIG_MS_BUSMOUSE is not set
CONFIG_MOUSE=y
CONFIG_PSMOUSE=y
# CONFIG_82C710_MOUSE is not set
# CONFIG_PC110_PAD is not set
# CONFIG_QIC02_TAPE is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
# CONFIG_QUOTA is not set
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_ZISOFS is not set
# CONFIG_JFS_FS is not set
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
# CONFIG_NFSD_TCP is not set
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_ZISOFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
# CONFIG_SMB_NLS is not set
CONFIG_NLS=y
#
# Native Language Support
#
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Sound
#
CONFIG_SOUND=y
#
# Open Sound System
#
CONFIG_SOUND_PRIME=y
# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_ES1371 is not set
# CONFIG_SOUND_ESSSOLO1 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_MIDI_VIA82CXXX is not set
# CONFIG_SOUND_OSS is not set
# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_PXA_AC97 is not set
# CONFIG_SOUND_TVMIXER is not set
#
# Advanced Linux Sound Architecture
#
# CONFIG_SND is not set
#
# Multimedia Capabilities Port drivers
#
# CONFIG_MCP is not set
# CONFIG_MCP_SA1100 is not set
# CONFIG_MCP_UCB1200 is not set
# CONFIG_MCP_UCB1200_AUDIO is not set
# CONFIG_MCP_UCB1200_TS is not set
# CONFIG_MCP_UCB1400_TS is not set
#
# Console Switches
#
# CONFIG_SWITCHES is not set
#
# USB support
#
# CONFIG_USB is not set
#
# Bluetooth support
#
# CONFIG_BLUEZ is not set
#
# Kernel hacking
#
# CONFIG_NO_FRAME_POINTER is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SLAB is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_WAITQ is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_DC21285_PORT is not set
# CONFIG_DEBUG_CLPS711X_UART2 is not set
#
# Library routines
#
CONFIG_CRC32=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/arm/kernel/debug.S
View file @ 0028e1e2
...@@ -215,8 +215,8 @@ ...@@ -215,8 +215,8 @@
.macro addruart,rx .macro addruart,rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #0x40000000 @ physical moveq \rx, #0x40000000 @ physical
movne \rx, #0xfc000000 @ virtual movne \rx, #io_p2v(0x40000000) @ virtual
orr \rx, \rx, #0x00100000 orr \rx, \rx, #0x00100000
.endm .endm
......
arch/arm/kernel/entry-armv.S
View file @ 0028e1e2
...@@ -590,7 +590,7 @@ ENTRY(anakin_active_irqs) ...@@ -590,7 +590,7 @@ ENTRY(anakin_active_irqs)
.endm .endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #0xfc000000 @ IIR Ctl = 0xfcd00000 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000 add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR ldr \irqnr, [\base, #4] @ ICMR
......
arch/arm/mach-pxa/Makefile
View file @ 0028e1e2
...@@ -29,4 +29,7 @@ leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o ...@@ -29,4 +29,7 @@ leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
obj-$(CONFIG_LEDS) += $(leds-y) obj-$(CONFIG_LEDS) += $(leds-y)
# Misc features
obj-$(CONFIG_PM) += pm.o sleep.o
include $(TOPDIR)/Rules.make include $(TOPDIR)/Rules.make
arch/arm/mach-pxa/generic.c
View file @ 0028e1e2
...@@ -91,9 +91,10 @@ static struct map_desc standard_io_desc[] __initdata = { ...@@ -91,9 +91,10 @@ static struct map_desc standard_io_desc[] __initdata = {
/* virtual physical length type */ /* virtual physical length type */
{ 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */ { 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
{ 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */ { 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
{ 0xfc000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */ { 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
{ 0xfe000000, 0x44000000, 0x00200000, MT_DEVICE }, /* LCD */ { 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
{ 0xff000000, 0x48000000, 0x00200000, MT_DEVICE } /* Mem Ctl */ { 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
{ 0xff000000, 0x00000000, 0x00100000, MT_DEVICE } /* UNCACHED_PHYS_0 */
}; };
void __init pxa_map_io(void) void __init pxa_map_io(void)
......
arch/arm/mach-pxa/lubbock.c
View file @ 0028e1e2
...@@ -142,11 +142,20 @@ static void __init lubbock_map_io(void) ...@@ -142,11 +142,20 @@ static void __init lubbock_map_io(void)
/* This is for the SMC chip select */ /* This is for the SMC chip select */
pxa_gpio_mode(GPIO79_nCS_3_MD); pxa_gpio_mode(GPIO79_nCS_3_MD);
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
} }
MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform") MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform")
MAINTAINER("MontaVista Software Inc.") MAINTAINER("MontaVista Software Inc.")
BOOT_MEM(0xa0000000, 0x40000000, 0xfc000000) BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
MAPIO(lubbock_map_io) MAPIO(lubbock_map_io)
INITIRQ(lubbock_init_irq) INITIRQ(lubbock_init_irq)
MACHINE_END MACHINE_END
arch/arm/mach-pxa/pm.c 0 → 100644
View file @ 0028e1e2
/*
* PXA250/210 Power Management Routines
*
* Original code for the SA11x0:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Modified for the PXA250 by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/sysctl.h>
#include <linux/errno.h>
#include <asm/hardware.h>
#include <asm/memory.h>
#include <asm/system.h>
#include <asm/leds.h>
/*
* Debug macros
*/
#undef DEBUG
extern void pxa_cpu_suspend(void);
extern void pxa_cpu_resume(void);
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
/*
* List of global PXA peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
* with the stack pointer in sleep.S.
*/
enum { SLEEP_SAVE_START = 0,
SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,
SLEEP_SAVE_ICMR,
SLEEP_SAVE_CKEN,
SLEEP_SAVE_CKSUM,
SLEEP_SAVE_SIZE
};
int pm_do_suspend(void)
{
unsigned long sleep_save[SLEEP_SAVE_SIZE];
unsigned long checksum = 0;
int i;
cli();
clf();
leds_event(led_stop);
/* preserve current time */
RCNR = xtime.tv_sec;
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial/* driver
* Save the FF UART
*/
SAVE(FFIER);
SAVE(FFLCR);
SAVE(FFMCR);
SAVE(FFSPR);
SAVE(FFISR);
FFLCR |= 0x80;
SAVE(FFDLL);
SAVE(FFDLH);
FFLCR &= 0xef;
/* save vital registers */
SAVE(OSCR);
SAVE(OSMR0);
SAVE(OSMR1);
SAVE(OSMR2);
SAVE(OSMR3);
SAVE(OIER);
SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
SAVE(GAFR0_L); SAVE(GAFR0_U);
SAVE(GAFR1_L); SAVE(GAFR1_U);
SAVE(GAFR2_L); SAVE(GAFR2_U);
SAVE(ICMR);
ICMR = 0;
SAVE(CKEN);
CKEN = 0;
/* Note: wake up source are set up in each machine specific files */
/* clear GPIO transition detect bits */
GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
/* Clear sleep reset status */
RCSR = RCSR_SMR;
/* set resume return address */
PSPR = virt_to_phys(pxa_cpu_resume);
/* before sleeping, calculate and save a checksum */
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
sleep_save[SLEEP_SAVE_CKSUM] = checksum;
/* *** go zzz *** */
pxa_cpu_suspend();
/* after sleeping, validate the checksum */
checksum = 0;
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
/* if invalid, display message and wait for a hardware reset */
if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
#ifdef CONFIG_ARCH_LUBBOCK
LUB_HEXLED = 0xbadbadc5;
#endif
while (1);
}
/* ensure not to come back here if it wasn't intended */
PSPR = 0;
/* restore registers */
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
PSSR = PSSR_PH;
RESTORE(OSMR0);
RESTORE(OSMR1);
RESTORE(OSMR2);
RESTORE(OSMR3);
RESTORE(OSCR);
RESTORE(OIER);
RESTORE(CKEN);
ICLR = 0;
ICCR = 1;
RESTORE(ICMR);
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial/* driver.
* Restore the FF UART.
*/
RESTORE(FFMCR);
RESTORE(FFSPR);
RESTORE(FFLCR);
FFLCR |= 0x80;
RESTORE(FFDLH);
RESTORE(FFDLL);
RESTORE(FFLCR);
RESTORE(FFISR);
FFFCR = 0x07;
RESTORE(FFIER);
/* restore current time */
xtime.tv_sec = RCNR;
#ifdef DEBUG
printk(KERN_DEBUG "*** made it back from resume\n");
#endif
leds_event(led_start);
sti();
return 0;
}
unsigned long sleep_phys_sp(void *sp)
{
return virt_to_phys(sp);
}
#ifdef CONFIG_SYSCTL
/*
* ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than
* linux/sysctl.h.
*
* This means our interface here won't survive long - it needs a new
* interface. Quick hack to get this working - use sysctl id 9999.
*/
#warning ACPI broke the kernel, this interface needs to be fixed up.
#define CTL_ACPI 9999
#define ACPI_S1_SLP_TYP 19
/*
* Send us to sleep.
*/
static int sysctl_pm_do_suspend(void)
{
int retval;
retval = pm_send_all(PM_SUSPEND, (void *)3);
if (retval == 0) {
retval = pm_do_suspend();
pm_send_all(PM_RESUME, (void *)0);
}
return retval;
}
static struct ctl_table pm_table[] =
{
{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
{0}
};
static struct ctl_table pm_dir_table[] =
{
{CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
{0}
};
/*
* Initialize power interface
*/
static int __init pm_init(void)
{
register_sysctl_table(pm_dir_table, 1);
return 0;
}
__initcall(pm_init);
#endif
arch/arm/mach-pxa/sleep.S 0 → 100644
View file @ 0028e1e2
/*
* Low-level PXA250/210 sleep/wakeUp support
*
* Initial SA1110 code:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Adapted for PXA by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
.text
/*
* pxa_cpu_suspend()
*
* Forces CPU into sleep state
*/
ENTRY(pxa_cpu_suspend)
mra r2, r3, acc0
stmfd sp!, {r2 - r12, lr} @ save registers on stack
@ get coprocessor registers
mrc p15, 0, r4, c15, c1, 0 @ CP access reg
mrc p15, 0, r5, c13, c0, 0 @ PID
mrc p15, 0, r6, c3, c0, 0 @ domain ID
mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
mrc p15, 0, r9, c1, c0, 0 @ control reg
@ store them plus current virtual stack ptr on stack
mov r10, sp
stmfd sp!, {r4 - r10}
@ preserve phys address of stack
mov r0, sp
bl sleep_phys_sp
ldr r1, =sleep_save_sp
str r0, [r1]
@ clean data cache
bl cpu_xscale_cache_clean_invalidate_all
@ Put the processor to sleep
@ (also workaround for sighting 28071)
@ prepare value for sleep mode
mov r1, #3 @ sleep mode
@ prepare to put SDRAM into self-refresh manually
ldr r4, =MDREFR
ldr r5, [r4]
orr r5, r5, #MDREFR_SLFRSH
@ prepare pointer to physical address 0 (virtual mapping in generic.c)
mov r2, #UNCACHED_PHYS_0
@ align execution to a cache line
b 1f
.ltorg
.align 5
1:
@ All needed values are now in registers.
@ These last instructions should be in cache
@ put SDRAM into self-refresh
str r5, [r4]
@ force address lines low by reading at physical address 0
ldr r3, [r2]
@ enter sleep mode
mcr p14, 0, r1, c7, c0, 0
20: nop
b 20b @ loop waiting for sleep
/*
* cpu_pxa_resume()
*
* entry point from bootloader into kernel during resume
*
* Note: Yes, part of the following code is located into the .data section.
* This is to allow sleep_save_sp to be accessed with a relative load
* while we can't rely on any MMU translation. We could have put
* sleep_save_sp in the .text section as well, but some setups might
* insist on it to be truely read-only.
*/
.data
.align 5
ENTRY(pxa_cpu_resume)
mov r0, #I_BIT | F_BIT | MODE_SVC @ set SVC, irqs off
msr cpsr_c, r0
ldr r0, sleep_save_sp @ stack phys addr
ldr r2, =resume_after_mmu @ its absolute virtual address
ldmfd r0, {r4 - r9, sp} @ CP regs + virt stack ptr
mov r1, #0
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
#ifdef CONFIG_XSCALE_CACHE_ERRATA
bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
#endif
mcr p15, 0, r4, c15, c1, 0 @ CP access reg
mcr p15, 0, r5, c13, c0, 0 @ PID
mcr p15, 0, r6, c3, c0, 0 @ domain ID
mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
b resume_turn_on_mmu @ cache align execution
.align 5
resume_turn_on_mmu:
mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
@ Let us ensure we jump to resume_after_mmu only when the mcr above
@ actually took effect. They call it the "cpwait" operation.
mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
sub pc, r2, r1, lsr #32 @ jump to virtual addr
nop
nop
nop
sleep_save_sp:
.word 0 @ preserve stack phys ptr here
.text
resume_after_mmu:
#ifdef CONFIG_XSCALE_CACHE_ERRATA
bl cpu_xscale_proc_init
#endif
ldmfd sp!, {r2, r3}
mar acc0, r2, r3
ldmfd sp!, {r4 - r12, pc} @ return to caller
arch/arm/mm/proc-xscale.S
View file @ 0028e1e2
...@@ -156,7 +156,7 @@ ENTRY(cpu_xscale_reset) ...@@ -156,7 +156,7 @@ ENTRY(cpu_xscale_reset)
msr cpsr_c, r1 @ reset CPSR msr cpsr_c, r1 @ reset CPSR
mrc p15, 0, r1, c1, c0, 0 @ ctrl register mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x0086 @ ........B....CA. bic r1, r1, #0x0086 @ ........B....CA.
bic r1, r1, #0x1900 @ ...IZ..S........ bic r1, r1, #0x3900 @ ..VIZ..S........
mcr p15, 0, r1, c1, c0, 0 @ ctrl register mcr p15, 0, r1, c1, c0, 0 @ ctrl register
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
bic r1, r1, #0x0001 @ ...............M bic r1, r1, #0x0001 @ ...............M
......
drivers/pcmcia/Makefile
View file @ 0028e1e2
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# Makefile for the kernel pcmcia subsystem (c/o David Hinds) # Makefile for the kernel pcmcia subsystem (c/o David Hinds)
# #
export-objs := ds.o cs.o yenta.o export-objs := ds.o cs.o yenta.o sa1100_pcmcia.o
obj-$(CONFIG_PCMCIA) += pcmcia_core.o ds.o obj-$(CONFIG_PCMCIA) += pcmcia_core.o ds.o
ifeq ($(CONFIG_CARDBUS),y) ifeq ($(CONFIG_CARDBUS),y)
......
drivers/pcmcia/sa1100_generic.c
View file @ 0028e1e2
...@@ -1052,6 +1052,7 @@ int sa1100_register_pcmcia(struct pcmcia_low_level *ops) ...@@ -1052,6 +1052,7 @@ int sa1100_register_pcmcia(struct pcmcia_low_level *ops)
pcmcia_low_level = NULL; pcmcia_low_level = NULL;
return ret; return ret;
} }
EXPORT_SYMBOL(sa1100_register_pcmcia);
/* sa1100_unregister_pcmcia() /* sa1100_unregister_pcmcia()
* ^^^^^^^^^^^^^^^^^^^^^^^^^^ * ^^^^^^^^^^^^^^^^^^^^^^^^^^
...@@ -1091,6 +1092,7 @@ void sa1100_unregister_pcmcia(struct pcmcia_low_level *ops) ...@@ -1091,6 +1092,7 @@ void sa1100_unregister_pcmcia(struct pcmcia_low_level *ops)
pcmcia_low_level = NULL; pcmcia_low_level = NULL;
} }
EXPORT_SYMBOL(sa1100_unregister_pcmcia);
/* sa1100_pcmcia_init() /* sa1100_pcmcia_init()
* ^^^^^^^^^^^^^^^^^^^^ * ^^^^^^^^^^^^^^^^^^^^
......
drivers/video/sa1100fb.c
View file @ 0028e1e2
...@@ -205,9 +205,6 @@ ...@@ -205,9 +205,6 @@
extern void (*sa1100fb_backlight_power)(int on); extern void (*sa1100fb_backlight_power)(int on);
extern void (*sa1100fb_lcd_power)(int on); extern void (*sa1100fb_lcd_power)(int on);
void (*sa1100fb_blank_helper)(int blank);
EXPORT_SYMBOL(sa1100fb_blank_helper);
/* /*
* IMHO this looks wrong. In 8BPP, length should be 8. * IMHO this looks wrong. In 8BPP, length should be 8.
*/ */
...@@ -262,7 +259,7 @@ static struct sa1100fb_mach_info pal_info __initdata = { ...@@ -262,7 +259,7 @@ static struct sa1100fb_mach_info pal_info __initdata = {
#endif #endif
#endif #endif
#ifdef CONFIG_SA1100_H3XXX #ifdef CONFIG_SA1100_H3800
static struct sa1100fb_mach_info h3800_info __initdata = { static struct sa1100fb_mach_info h3800_info __initdata = {
pixclock: 174757, bpp: 16, pixclock: 174757, bpp: 16,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -274,9 +271,12 @@ static struct sa1100fb_mach_info h3800_info __initdata = { ...@@ -274,9 +271,12 @@ static struct sa1100fb_mach_info h3800_info __initdata = {
sync: 0, cmap_static: 1, sync: 0, cmap_static: 1,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act, lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_ACBsCntOff | LCCR3_PixFlEdg | LCCR3_OutEnH, lccr3: LCCR3_ACBsDiv(2) | LCCR3_PixRsEdg | LCCR3_OutEnH |
LCCR3_ACBsCntOff,
}; };
#endif
#ifdef CONFIG_SA1100_H3600
static struct sa1100fb_mach_info h3600_info __initdata = { static struct sa1100fb_mach_info h3600_info __initdata = {
pixclock: 174757, bpp: 16, pixclock: 174757, bpp: 16,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -288,7 +288,8 @@ static struct sa1100fb_mach_info h3600_info __initdata = { ...@@ -288,7 +288,8 @@ static struct sa1100fb_mach_info h3600_info __initdata = {
sync: 0, cmap_static: 1, sync: 0, cmap_static: 1,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act, lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_ACBsCntOff | LCCR3_OutEnH | LCCR3_PixFlEdg, lccr3: LCCR3_ACBsDiv(2) | LCCR3_PixRsEdg | LCCR3_OutEnH |
LCCR3_ACBsCntOff,
}; };
static struct sa1100fb_rgb h3600_rgb_16 = { static struct sa1100fb_rgb h3600_rgb_16 = {
...@@ -297,7 +298,9 @@ static struct sa1100fb_rgb h3600_rgb_16 = { ...@@ -297,7 +298,9 @@ static struct sa1100fb_rgb h3600_rgb_16 = {
blue: { offset: 1, length: 4, }, blue: { offset: 1, length: 4, },
transp: { offset: 0, length: 0, }, transp: { offset: 0, length: 0, },
}; };
#endif
#ifdef CONFIG_SA1100_H3100
static struct sa1100fb_mach_info h3100_info __initdata = { static struct sa1100fb_mach_info h3100_info __initdata = {
pixclock: 406977, bpp: 4, pixclock: 406977, bpp: 4,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -680,14 +683,18 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi) ...@@ -680,14 +683,18 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
#endif #endif
} }
#endif #endif
#ifdef CONFIG_SA1100_H3XXX #ifdef CONFIG_SA1100_H3100
if (machine_is_h3100()) {
inf = &h3100_info;
}
#endif
#ifdef CONFIG_SA1100_H3600
if (machine_is_h3600()) { if (machine_is_h3600()) {
inf = &h3600_info; inf = &h3600_info;
fbi->rgb[RGB_16] = &h3600_rgb_16; fbi->rgb[RGB_16] = &h3600_rgb_16;
} }
if (machine_is_h3100()) { #endif
inf = &h3100_info; #ifdef CONFIG_SA1100_H3800
}
if (machine_is_h3800()) { if (machine_is_h3800()) {
inf = &h3800_info; inf = &h3800_info;
} }
...@@ -1310,13 +1317,9 @@ static int sa1100fb_blank(int blank, struct fb_info *info) ...@@ -1310,13 +1317,9 @@ static int sa1100fb_blank(int blank, struct fb_info *info)
for (i = 0; i < fbi->palette_size; i++) for (i = 0; i < fbi->palette_size; i++)
sa1100fb_setpalettereg(i, 0, 0, 0, 0, info); sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
sa1100fb_schedule_task(fbi, C_DISABLE); sa1100fb_schedule_task(fbi, C_DISABLE);
if (sa1100fb_blank_helper)
sa1100fb_blank_helper(blank);
break; break;
case VESA_NO_BLANKING: case VESA_NO_BLANKING:
if (sa1100fb_blank_helper)
sa1100fb_blank_helper(blank);
if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR || if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR) fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&fbi->fb.cmap, 1, info); fb_set_cmap(&fbi->fb.cmap, 1, info);
......
include/asm-arm/arch-pxa/hardware.h
View file @ 0028e1e2
...@@ -27,17 +27,27 @@ ...@@ -27,17 +27,27 @@
/* /*
* Intel PXA internal I/O mappings * We requires absolute addresses.
*/ */
#define PCIO_BASE 0
#define io_p2v(x) \ /*
(((x) < 0x44000000) ? ((x) - 0x40000000 + 0xfc000000) : \ * Workarounds for at least 2 errata so far require this.
((x) < 0x48000000) ? ((x) - 0x44000000 + 0xfe000000) : \ * The mapping is set in mach-pxa/generic.c.
((x) - 0x48000000 + 0xff000000)) */
#define io_v2p( x ) \ #define UNCACHED_PHYS_0 0xff000000
(((x) < 0xfe000000) ? ((x) - 0xfc000000 + 0x40000000) : \ #define UNCACHED_ADDR UNCACHED_PHYS_0
((x) < 0xff000000) ? ((x) - 0xfe000000 + 0x44000000) : \
((x) - 0xff000000 + 0x48000000)) /*
* Intel PXA internal I/O mappings:
*
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
...@@ -51,7 +61,7 @@ ...@@ -51,7 +61,7 @@
* doesn't guess this by itself. * doesn't guess this by itself.
*/ */
#include <asm/types.h> #include <asm/types.h>
typedef struct { volatile u32 offset[1024]; } __regbase; typedef struct { volatile u32 offset[4096]; } __regbase;
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] # define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
# define __REG(x) __REGP(io_p2v(x)) # define __REG(x) __REGP(io_p2v(x))
#endif #endif
...@@ -93,5 +103,6 @@ extern unsigned int get_lclk_frequency_10khz(void); ...@@ -93,5 +103,6 @@ extern unsigned int get_lclk_frequency_10khz(void);
#include "lubbock.h" #include "lubbock.h"
#include "idp.h" #include "idp.h"
#include "cerf.h"
#endif /* _ASM_ARCH_HARDWARE_H */ #endif /* _ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-pxa/pxa-regs.h
View file @ 0028e1e2
...@@ -262,6 +262,7 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -262,6 +262,7 @@ typedef void (*ExcpHndlr) (void) ;
/* default combinations */ /* default combinations */
#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
...@@ -361,7 +362,7 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -361,7 +362,7 @@ typedef void (*ExcpHndlr) (void) ;
#define LSR_OE (1 << 1) /* Overrun Error */ #define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */ #define LSR_DR (1 << 0) /* Data Ready */
#define MCR_LOOP (1 << 4) #define MCR_LOOP (1 << 4) */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */ #define MCR_RTS (1 << 1) /* Request to Send */
...@@ -376,6 +377,35 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -376,6 +377,35 @@ typedef void (*ExcpHndlr) (void) ;
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
/*
* IrSR (Infrared Selection Register)
*/
#define IrSR_OFFSET 0x20
#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
#define IrSR_RXPL_POS_IS_ZERO 0x0
#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
#define IrSR_TXPL_POS_IS_ZERO 0x0
#define IrSR_XMODE_PULSE_1_6 (1<<2)
#define IrSR_XMODE_PULSE_3_16 0x0
#define IrSR_RCVEIR_IR_MODE (1<<1)
#define IrSR_RCVEIR_UART_MODE 0x0
#define IrSR_XMITIR_IR_MODE (1<<0)
#define IrSR_XMITIR_UART_MODE 0x0
#define IrSR_IR_RECEIVE_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_IR_MODE | \
IrSR_XMITIR_UART_MODE)
#define IrSR_IR_TRANSMIT_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_UART_MODE | \
IrSR_XMITIR_IR_MODE)
/* /*
* I2C registers * I2C registers
...@@ -387,6 +417,37 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -387,6 +417,37 @@ typedef void (*ExcpHndlr) (void) ;
#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
/* ----- Control register bits ---------------------------------------- */
#define ICR_START 0x1 /* start bit */
#define ICR_STOP 0x2 /* stop bit */
#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
#define ICR_TB 0x8 /* transfer byte bit */
#define ICR_MA 0x10 /* master abort */
#define ICR_SCLE 0x20 /* master clock enable */
#define ICR_IUE 0x40 /* unit enable */
#define ICR_GCD 0x80 /* general call disable */
#define ICR_ITEIE 0x100 /* enable tx interrupts */
#define ICR_IRFIE 0x200 /* enable rx interrupts */
#define ICR_BEIE 0x400 /* enable bus error ints */
#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
#define ICR_SADIE 0x2000 /* slave address detected int enable */
#define ICR_UR 0x4000 /* unit reset */
/* ----- Status register bits ----------------------------------------- */
#define ISR_RWM 0x1 /* read/write mode */
#define ISR_ACKNAK 0x2 /* ack/nak status */
#define ISR_UB 0x4 /* unit busy */
#define ISR_IBB 0x8 /* bus busy */
#define ISR_SSD 0x10 /* slave stop detected */
#define ISR_ALD 0x20 /* arbitration loss detected */
#define ISR_ITE 0x40 /* tx buffer empty */
#define ISR_IRF 0x80 /* rx buffer full */
#define ISR_GCAD 0x100 /* general call address detected */
#define ISR_SAD 0x200 /* slave address detected */
#define ISR_BED 0x400 /* bus error no ACK/NAK */
/* /*
* Serial Audio Controller * Serial Audio Controller
...@@ -486,24 +547,92 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -486,24 +547,92 @@ typedef void (*ExcpHndlr) (void) ;
/* /*
* USB Device Controller * USB Device Controller
*/ */
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */ #define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
...@@ -528,11 +657,51 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -528,11 +657,51 @@ typedef void (*ExcpHndlr) (void) ;
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
/* /*
* Fast Infrared Communication Port * Fast Infrared Communication Port
...@@ -879,6 +1048,22 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -879,6 +1048,22 @@ typedef void (*ExcpHndlr) (void) ;
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
/* /*
* SSP Serial Port Registers * SSP Serial Port Registers
...@@ -1035,3 +1220,19 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -1035,3 +1220,19 @@ typedef void (*ExcpHndlr) (void) ;
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
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