Commit 006d9351 authored by Andrew Davis's avatar Andrew Davis Committed by Nishanth Menon

arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level

SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete
and will not be functional unless they are extended.

As the attached SD/eMMC is only known about at the board integration level,
these nodes should only be enabled when provided with this information.

Disable the SDHCI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: default avatarAndrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231117163339.89952-1-afd@ti.comSigned-off-by: default avatarNishanth Menon <nm@ti.com>
parent 1a4402e1
......@@ -1267,6 +1267,7 @@ &mcu_cpsw {
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
......
......@@ -449,6 +449,7 @@ sdhci0: mmc@4f80000 {
ti,otap-del-sel-hs400 = <0x0>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
sdhci1: mmc@4fa0000 {
......@@ -471,6 +472,7 @@ sdhci1: mmc@4fa0000 {
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
scm_conf: scm-conf@100000 {
......
......@@ -29,11 +29,6 @@ cpu-map {
/delete-node/ l2-cache1;
};
/* eMMC */
&sdhci0 {
status = "disabled";
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
......
......@@ -449,6 +449,7 @@ flash@0 {
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
......@@ -463,6 +464,7 @@ &sdhci0 {
* disable sdhci1
*/
&sdhci1 {
status = "okay";
vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
......
......@@ -43,6 +43,7 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
/* eMMC */
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
......
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