Commit 007d05d8 authored by Gregory CLEMENT's avatar Gregory CLEMENT

ARM: dts: armada-xp: Fixup pcie DT warnings

PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 1fc21295
......@@ -73,28 +73,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* First mini-PCIe port */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Renesas uPD720202 USB 3.0 controller */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
internal-regs {
/* UART0 */
serial@12000 {
......@@ -153,6 +131,28 @@ phy1: ethernet-phy@1 {
};
};
&pciec {
status = "okay";
/* First mini-PCIe port */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Renesas uPD720202 USB 3.0 controller */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
&pinctrl {
pinctrl-0 = <&phy_int_pin>;
pinctrl-names = "default";
......
......@@ -108,39 +108,6 @@ nor@0 {
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
......@@ -248,6 +215,39 @@ bm-bppi {
};
};
&pciec {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
......
......@@ -127,27 +127,6 @@ nor@0 {
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
......@@ -233,6 +212,27 @@ bm-bppi {
};
};
&pciec {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;
......
......@@ -68,22 +68,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Quad port sata: Marvell 88SX7042 */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* USB 3.0 xHCI controller: NEC D720200F1 */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
......@@ -285,6 +269,21 @@ gpio-poweroff {
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
};
&pciec {
status = "okay";
/* Quad port sata: Marvell 88SX7042 */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* USB 3.0 xHCI controller: NEC D720200F1 */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
......
......@@ -73,28 +73,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Etron EJ168 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* First mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
internal-regs {
rtc@10300 {
......@@ -369,6 +347,28 @@ port@5 {
};
};
&pciec {
status = "okay";
/* Etron EJ168 USB 3.0 controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* First mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
&pinctrl {
keys_pin: keys-pin {
......
......@@ -71,15 +71,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
......@@ -114,3 +105,12 @@ usb@50000 {
};
};
};
&pciec {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
......@@ -86,7 +86,7 @@ soc {
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
pciec: pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
......
......@@ -87,7 +87,7 @@ soc {
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
pciec: pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
......
......@@ -104,7 +104,7 @@ soc {
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pciec: pcie-controller {
pciec: pcie-controller@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
......
......@@ -67,28 +67,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Connected to first Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to second Marvell 88SE9170 SATA controller */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
......@@ -290,6 +268,28 @@ gpio-poweroff {
};
};
&pciec {
status = "okay";
/* Connected to first Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to second Marvell 88SE9170 SATA controller */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
......
......@@ -98,15 +98,6 @@ nor@0 {
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
internal-regs {
rtc@10300 {
/* No crystal connected to the internal RTC */
......@@ -222,6 +213,15 @@ bm-bppi {
};
};
&pciec {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
......
......@@ -81,28 +81,6 @@ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Seiko S-35390A below */
......@@ -230,6 +208,29 @@ sata4_regulator: sata4-regulator {
};
};
&pciec {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
......
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