Commit 01001712 authored by Hemant Pedanekar's avatar Hemant Pedanekar Committed by Tony Lindgren

TI816X: Update common OMAP machine specific sources

This patch updates the common machine specific source files with support for
TI816X.
Signed-off-by: default avatarHemant Pedanekar <hemantp@ti.com>
Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 4bd7be22
......@@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
......@@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void)
/*
* Lock DPLL5 and put it in autoidle.
*/
if (omap_rev() >= OMAP3430_REV_ES2_0)
if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
......
......@@ -108,6 +108,27 @@ void __init omap3_map_io(void)
omap2_set_globals_3xxx();
omap34xx_map_common_io();
}
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
* TI816X register for checking device ID (it adds 0x204 to tap base while
* TI816X DEVICE ID register is at offset 0x600 from control base).
*/
#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
TI816X_CONTROL_DEVICE_ID - 0x204)
static struct omap_globals ti816x_globals = {
.class = OMAP343X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
.ctrl = TI816X_CTRL_BASE,
.prm = TI816X_PRCM_BASE,
.cm = TI816X_PRCM_BASE,
};
void __init omap2_set_globals_ti816x(void)
{
__omap2_set_globals(&ti816x_globals);
}
#endif
#if defined(CONFIG_ARCH_OMAP4)
......
......@@ -52,6 +52,9 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
/* TI816X spefic control submodules */
#define TI816X_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
......@@ -241,6 +244,9 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
/* TI816X CONTROL_DEVCONF register offsets */
#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
......
......@@ -191,12 +191,19 @@ static void __init omap3_check_features(void)
if (!cpu_is_omap3505() && !cpu_is_omap3517())
omap3_features |= OMAP3_HAS_IO_WAKEUP;
omap3_features |= OMAP3_HAS_SDRC;
/*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
}
static void __init ti816x_check_features(void)
{
omap3_features = OMAP3_HAS_NEON;
}
static void __init omap3_check_revision(void)
{
u32 cpuid, idcode;
......@@ -287,6 +294,20 @@ static void __init omap3_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
}
break;
case 0xb81e:
omap_chip.oc = CHIP_IS_TI816X;
switch (rev) {
case 0:
omap_revision = TI8168_REV_ES1_0;
break;
case 1:
omap_revision = TI8168_REV_ES1_1;
break;
default:
omap_revision = TI8168_REV_ES1_1;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
......@@ -372,6 +393,8 @@ static void __init omap3_cpuinfo(void)
/* Already set in omap3_check_revision() */
strcpy(cpu_name, "AM3505");
}
} else if (cpu_is_ti816x()) {
strcpy(cpu_name, "TI816X");
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
......@@ -386,7 +409,7 @@ static void __init omap3_cpuinfo(void)
strcpy(cpu_name, "OMAP3503");
}
if (cpu_is_omap3630()) {
if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
......@@ -462,7 +485,13 @@ void __init omap2_check_revision(void)
omap24xx_check_revision();
} else if (cpu_is_omap34xx()) {
omap3_check_revision();
/* TI816X doesn't have feature register */
if (!cpu_is_ti816x())
omap3_check_features();
else
ti816x_check_features();
omap3_cpuinfo();
return;
} else if (cpu_is_omap44xx()) {
......
......@@ -61,6 +61,14 @@
bne 9998f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
bne 9998f
/*
* ti816x has additional IRQ pending register. Checking this
* register on omap2 & omap3 has no effect (read as 0).
*/
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
9998:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
......@@ -133,6 +141,11 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
#ifdef CONFIG_SOC_OMAPTI816X
bne 9999f
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
#endif
9999:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
......
......@@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
#endif
};
#endif
#ifdef CONFIG_SOC_OMAPTI816X
static struct map_desc omapti816x_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
......@@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAPTI816X
void __init omapti816x_map_common_io(void)
{
iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
_omap2_map_common_io();
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
......@@ -398,7 +418,7 @@ void __init omap2_init_common_infrastructure(void)
void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
......
......@@ -110,7 +110,7 @@ static void omap_mask_irq(struct irq_data *d)
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
int spurious = 0;
/*
......@@ -205,6 +205,9 @@ void __init omap_init_irq(void)
BUG_ON(!base);
if (cpu_is_ti816x())
bank->nr_irqs = 128;
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {
......
......@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
......@@ -762,13 +762,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
p->private_data = uart;
/*
* omap44xx: Never read empty UART fifo
* omap44xx, ti816x: Never read empty UART fifo
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
if (cpu_is_omap44xx())
if (cpu_is_omap44xx() || cpu_is_ti816x())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
......@@ -850,7 +850,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
if (cpu_is_omap34xx())
if (cpu_is_omap34xx() && !cpu_is_ti816x())
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}
......
......@@ -286,5 +286,6 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
#include <plat/ti816x.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
......@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAPTI816X
extern void omapti816x_map_common_io(void);
#else
static inline void omapti816x_map_common_io(void)
{
}
#endif
#ifdef CONFIG_ARCH_OMAP4
extern void omap44xx_map_common_io(void);
#else
......
/*
* This file contains the address data for various TI816X modules.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_TI816X_H
#define __ASM_ARCH_TI816X_H
#define L4_SLOW_TI816X_BASE 0x48000000
#define TI816X_SCM_BASE 0x48140000
#define TI816X_CTRL_BASE TI816X_SCM_BASE
#define TI816X_PRCM_BASE 0x48180000
#define TI816X_ARM_INTC_BASE 0x48200000
#endif /* __ASM_ARCH_TI816X_H */
......@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP3
if (cpu_is_omap34xx()) {
if (cpu_is_ti816x()) {
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
} else if (cpu_is_omap34xx()) {
if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
......
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