Commit 01561776 authored by Russell King's avatar Russell King

[ARM] Fix XScale "feature"

XScale does not guarantee that CPU control register writes complete
their side effects immediately.  In fact, Intel give sample code to
demonstrate a way to ensure that the effect of the write has occurred.
This is specific to Xscale, but the fix should work on any ARM CPU.
We therefore jump through the loops in "spirit" but not necessarily
in exactly the same way as the sample code.
parent 5e2076c4
...@@ -117,8 +117,8 @@ __turn_mmu_on: ...@@ -117,8 +117,8 @@ __turn_mmu_on:
#ifdef CONFIG_ALIGNMENT_TRAP #ifdef CONFIG_ALIGNMENT_TRAP
orr r0, r0, #2 @ ...........A. orr r0, r0, #2 @ ...........A.
#endif #endif
mcr p15, 0, r0, c1, c0 mcr p15, 0, r0, c1, c0, 0 @ write control reg
mov r0, r0 mrc p15, 0, r0, c1, c0, 0 @ read it back.
mov r0, r0 mov r0, r0
mov r0, r0 mov r0, r0
mov pc, lr mov pc, lr
......
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