Commit 015fc623 authored by Paul Burton's avatar Paul Burton Committed by Kamal Mostafa

MIPS: math-emu: Fix BC1{EQ,NE}Z emulation

commit 93583e17 upstream.

The conditions for branching when emulating the BC1EQZ & BC1NEZ
instructions were backwards, leading to each of those instructions being
treated as the other. Fix this by reversing the conditions, and clear up
the code a little for readability & checkpatch.

Fixes: c909ca71 ("MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions")
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13150/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
parent f1476aa5
...@@ -975,9 +975,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -975,9 +975,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
struct mm_decoded_insn dec_insn, void *__user *fault_addr) struct mm_decoded_insn dec_insn, void *__user *fault_addr)
{ {
unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
unsigned int cond, cbit; unsigned int cond, cbit, bit0;
mips_instruction ir; mips_instruction ir;
int likely, pc_inc; int likely, pc_inc;
union fpureg *fpr;
u32 __user *wva; u32 __user *wva;
u64 __user *dva; u64 __user *dva;
u32 wval; u32 wval;
...@@ -1189,14 +1190,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1189,14 +1190,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
return SIGILL; return SIGILL;
cond = likely = 0; cond = likely = 0;
fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
bit0 = get_fpr32(fpr, 0) & 0x1;
switch (MIPSInst_RS(ir)) { switch (MIPSInst_RS(ir)) {
case bc1eqz_op: case bc1eqz_op:
if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1) cond = bit0 == 0;
cond = 1;
break; break;
case bc1nez_op: case bc1nez_op:
if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)) cond = bit0 != 0;
cond = 1;
break; break;
} }
goto branch_common; goto branch_common;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment