Commit 01a18aa3 authored by Ryan Lin's avatar Ryan Lin Committed by Alex Deucher

drm/amd/display: Ext displays with dock can't recognized after resume

[Why]
Needs to set the default value of the LTTPR timeout after resume.

[How]
Set the default (3.2ms) timeout at resuming if the sink supports
LTTPR
Reviewed-by: default avatarJerry Zuo <Jerry.Zuo@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarRyan Lin <tsung-hua.lin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 23f4a2d2
...@@ -41,6 +41,8 @@ ...@@ -41,6 +41,8 @@
#include "dpcd_defs.h" #include "dpcd_defs.h"
#include "link/protocols/link_dpcd.h" #include "link/protocols/link_dpcd.h"
#include "link_service_types.h" #include "link_service_types.h"
#include "link/protocols/link_dp_capability.h"
#include "link/protocols/link_ddc.h"
#include "vid.h" #include "vid.h"
#include "amdgpu.h" #include "amdgpu.h"
...@@ -2302,6 +2304,14 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) ...@@ -2302,6 +2304,14 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
if (suspend) { if (suspend) {
drm_dp_mst_topology_mgr_suspend(mgr); drm_dp_mst_topology_mgr_suspend(mgr);
} else { } else {
/* if extended timeout is supported in hardware,
* default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
* CTS 4.2.1.1 regression introduced by CTS specs requirement update.
*/
try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
if (!dp_is_lttpr_present(aconnector->dc_link))
try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
ret = drm_dp_mst_topology_mgr_resume(mgr, true); ret = drm_dp_mst_topology_mgr_resume(mgr, true);
if (ret < 0) { if (ret < 0) {
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40 #define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40
#define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1 #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
#define EDID_SEGMENT_SIZE 256 #define EDID_SEGMENT_SIZE 256
......
...@@ -60,8 +60,6 @@ ...@@ -60,8 +60,6 @@
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif #endif
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
struct dp_lt_fallback_entry { struct dp_lt_fallback_entry {
enum dc_lane_count lane_count; enum dc_lane_count lane_count;
enum dc_link_rate link_rate; enum dc_link_rate link_rate;
......
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