Skip to content

L
linux
Commit 01a7ee36 authored by David S. Miller's avatar David S. Miller
Browse files
Options

Merge branch 'net-ipa-GSI' 

Alex Elder says:

====================
net: ipa: prepare for GSI register updtaes

An upcoming series (or two) will convert the definitions of GSI
registers used by IPA so they use the "IPA reg" mechanism to specify
register offsets and their fields.  This will simplify implementing
the fairly large number of changes required in GSI registers to
support more than 32 GSI channels (introduced in IPA v5.0).

A few minor problems and inconsistencies were found, and they're
fixed here.  The last three patches in this series change the
"ipa_reg" code to separate the IPA-specific part (the base virtual
address, basically) from the generic register part, and the now-
generic code is renamed to use just "reg_" or "REG_" as a prefix
rather than "ipa_reg" or "IPA_REG_".
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 47400aae f1470fd7
Hide whitespace changes
Inline Side-by-side
Showing with 1471 additions and 1422 deletions
drivers/net/ipa/gsi.c
View file @ 01a7ee36
......@@ -182,6 +182,41 @@ static bool gsi_channel_initialized(struct gsi_channel *channel)
return !!channel->gsi;
}
/* Encode the channel protocol for the CH_C_CNTXT_0 register */
static u32 ch_c_cntxt_0_type_encode(enum ipa_version version,
enum gsi_channel_type type)
{
u32 val;
val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK);
if (version < IPA_VERSION_4_5)
return val;
type >>= hweight32(CHTYPE_PROTOCOL_FMASK);
return val | u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK);
}
/* Encode a channel ring buffer length for the CH_C_CNTXT_1 register */
static u32 ch_c_cntxt_1_length_encode(enum ipa_version version, u32 length)
{
if (version < IPA_VERSION_4_9)
return u32_encode_bits(length, GENMASK(15, 0));
return u32_encode_bits(length, GENMASK(19, 0));
}
/* Encode the length of the event channel ring buffer for the
* EV_CH_E_CNTXT_1 register.
*/
static u32 ev_ch_e_cntxt_1_length_encode(enum ipa_version version, u32 length)
{
if (version < IPA_VERSION_4_9)
return u32_encode_bits(length, GENMASK(15, 0));
return u32_encode_bits(length, GENMASK(19, 0));
}
/* Update the GSI IRQ type register with the cached value */
static void gsi_irq_type_update(struct gsi *gsi, u32 val)
{
......@@ -191,12 +226,12 @@ static void gsi_irq_type_update(struct gsi *gsi, u32 val)
static void gsi_irq_type_enable(struct gsi *gsi, enum gsi_irq_type_id type_id)
{
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(type_id));
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | type_id);
}
static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id)
{
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~BIT(type_id));
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~type_id);
}
/* Event ring commands are performed one at a time. Their completion
......@@ -292,19 +327,19 @@ static void gsi_irq_enable(struct gsi *gsi)
/* Global interrupts include hardware error reports. Enable
* that so we can at least report the error should it occur.
*/
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE));
iowrite32(ERROR_INT, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GLOB_EE);
/* General GSI interrupts are reported to all EEs; if they occur
* they are unrecoverable (without reset). A breakpoint interrupt
* also exists, but we don't support that. We want to be notified
* of errors so we can report them, even if they can't be handled.
*/
val = BIT(BUS_ERROR);
val |= BIT(CMD_FIFO_OVRFLOW);
val |= BIT(MCS_STACK_OVRFLOW);
val = BUS_ERROR;
val |= CMD_FIFO_OVRFLOW;
val |= MCS_STACK_OVRFLOW;
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL));
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GENERAL);
}
/* Disable all GSI interrupt types */
......@@ -676,7 +711,7 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id));
size = ring->count * GSI_RING_ELEMENT_SIZE;
val = ev_r_length_encoded(gsi->version, size);
val = ev_ch_e_cntxt_1_length_encode(gsi->version, size);
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id));
/* The context 2 and 3 registers store the low-order and
......@@ -765,14 +800,14 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
u32 val;
/* We program all channels as GPI type/protocol */
val = chtype_protocol_encoded(gsi->version, GSI_CHANNEL_TYPE_GPI);
val = ch_c_cntxt_0_type_encode(gsi->version, GSI_CHANNEL_TYPE_GPI);
if (channel->toward_ipa)
val |= CHTYPE_DIR_FMASK;
val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK);
val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, ELEMENT_SIZE_FMASK);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id));
val = r_length_encoded(gsi->version, size);
val = ch_c_cntxt_1_length_encode(gsi->version, size);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id));
/* The context 2 and 3 registers store the low-order and
......@@ -1195,15 +1230,15 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET);
if (val & BIT(ERROR_INT))
if (val & ERROR_INT)
gsi_isr_glob_err(gsi);
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET);
val &= ~BIT(ERROR_INT);
val &= ~ERROR_INT;
if (val & BIT(GP_INT1)) {
val ^= BIT(GP_INT1);
if (val & GP_INT1) {
val ^= GP_INT1;
gsi_isr_gp_int1(gsi);
}
......@@ -1264,19 +1299,19 @@ static irqreturn_t gsi_isr(int irq, void *dev_id)
intr_mask ^= gsi_intr;
switch (gsi_intr) {
case BIT(GSI_CH_CTRL):
case GSI_CH_CTRL:
gsi_isr_chan_ctrl(gsi);
break;
case BIT(GSI_EV_CTRL):
case GSI_EV_CTRL:
gsi_isr_evt_ctrl(gsi);
break;
case BIT(GSI_GLOB_EE):
case GSI_GLOB_EE:
gsi_isr_glob_ee(gsi);
break;
case BIT(GSI_IEOB):
case GSI_IEOB:
gsi_isr_ieob(gsi);
break;
case BIT(GSI_GENERAL):
case GSI_GENERAL:
gsi_isr_general(gsi);
break;
default:
......@@ -1654,7 +1689,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
* channel), and only from this function. So we enable the GP_INT1
* IRQ type here, and disable it again after the command completes.
*/
val = BIT(ERROR_INT) | BIT(GP_INT1);
val = ERROR_INT | GP_INT1;
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
/* First zero the result code field */
......@@ -1666,12 +1701,13 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
val = u32_encode_bits(opcode, GENERIC_OPCODE_FMASK);
val |= u32_encode_bits(channel_id, GENERIC_CHID_FMASK);
val |= u32_encode_bits(GSI_EE_MODEM, GENERIC_EE_FMASK);
val |= u32_encode_bits(params, GENERIC_PARAMS_FMASK);
if (gsi->version >= IPA_VERSION_4_11)
val |= u32_encode_bits(params, GENERIC_PARAMS_FMASK);
timeout = !gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val);
/* Disable the GP_INT1 IRQ type again */
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(ERROR_INT, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
if (!timeout)
return gsi->result;
......
drivers/net/ipa/gsi_reg.h
View file @ 01a7ee36
......@@ -62,6 +62,18 @@
/* All other register offsets are relative to gsi->virt */
#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
(0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
#define CHTYPE_DIR_FMASK GENMASK(3, 3)
#define EE_FMASK GENMASK(7, 4)
#define CHID_FMASK GENMASK(12, 8)
/* The next field is present for IPA v4.5 and above */
#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
#define ERINDEX_FMASK GENMASK(18, 14)
#define CHSTATE_FMASK GENMASK(23, 20)
#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
enum gsi_channel_type {
GSI_CHANNEL_TYPE_MHI = 0x0,
......@@ -76,46 +88,9 @@ enum gsi_channel_type {
GSI_CHANNEL_TYPE_11AD = 0x9,
};
#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
(0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
#define CHTYPE_DIR_FMASK GENMASK(3, 3)
#define EE_FMASK GENMASK(7, 4)
#define CHID_FMASK GENMASK(12, 8)
/* The next field is present for IPA v4.5 and above */
#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
#define ERINDEX_FMASK GENMASK(18, 14)
#define CHSTATE_FMASK GENMASK(23, 20)
#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
/* Encoded value for CH_C_CNTXT_0 register channel protocol fields */
static inline u32
chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type)
{
u32 val;
val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK);
if (version < IPA_VERSION_4_5)
return val;
/* Encode upper bit(s) as well */
type >>= hweight32(CHTYPE_PROTOCOL_FMASK);
val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK);
return val;
}
#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
(0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
/* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */
static inline u32 r_length_encoded(enum ipa_version version, u32 length)
{
if (version < IPA_VERSION_4_9)
return u32_encode_bits(length, GENMASK(15, 0));
return u32_encode_bits(length, GENMASK(19, 0));
}
#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
(0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
......@@ -167,13 +142,6 @@ enum gsi_prefetch_mode {
#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
(0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
/* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */
static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length)
{
if (version < IPA_VERSION_4_9)
return u32_encode_bits(length, GENMASK(15, 0));
return u32_encode_bits(length, GENMASK(19, 0));
}
#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
(0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
......@@ -299,15 +267,25 @@ enum gsi_iram_size {
#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
(0x0001f088 + 0x4000 * GSI_EE_AP)
/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
/**
* enum gsi_irq_type_id: GSI IRQ types
* @GSI_CH_CTRL: Channel allocation, deallocation, etc.
* @GSI_EV_CTRL: Event ring allocation, deallocation, etc.
* @GSI_GLOB_EE: Global/general event
* @GSI_IEOB: Transfer (TRE) completion
* @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused)
* @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused)
* @GSI_GENERAL: General hardware event (bus error, etc.)
*/
enum gsi_irq_type_id {
GSI_CH_CTRL = 0x0, /* channel allocation, etc. */
GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */
GSI_GLOB_EE = 0x2, /* global/general event */
GSI_IEOB = 0x3, /* TRE completion */
GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */
GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */
GSI_GENERAL = 0x6, /* general-purpose event */
GSI_CH_CTRL = BIT(0),
GSI_EV_CTRL = BIT(1),
GSI_GLOB_EE = BIT(2),
GSI_IEOB = BIT(3),
GSI_INTER_EE_CH_CTRL = BIT(4),
GSI_INTER_EE_EV_CTRL = BIT(5),
GSI_GENERAL = BIT(6),
/* IRQ types 7-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
......@@ -343,12 +321,14 @@ enum gsi_irq_type_id {
(0x0001f108 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
(0x0001f110 + 0x4000 * GSI_EE_AP)
/* Values here are bit positions in the GLOB_IRQ_* registers */
/** enum gsi_global_irq_id: Global GSI interrupt events */
enum gsi_global_irq_id {
ERROR_INT = 0x0,
GP_INT1 = 0x1,
GP_INT2 = 0x2,
GP_INT3 = 0x3,
ERROR_INT = BIT(0),
GP_INT1 = BIT(1),
GP_INT2 = BIT(2),
GP_INT3 = BIT(3),
/* Global IRQ types 4-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
......@@ -357,12 +337,14 @@ enum gsi_global_irq_id {
(0x0001f120 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
(0x0001f128 + 0x4000 * GSI_EE_AP)
/* Values here are bit positions in the (general) GSI_IRQ_* registers */
enum gsi_general_id {
BREAK_POINT = 0x0,
BUS_ERROR = 0x1,
CMD_FIFO_OVRFLOW = 0x2,
MCS_STACK_OVRFLOW = 0x3,
/** enum gsi_general_irq_id: GSI general IRQ conditions */
enum gsi_general_irq_id {
BREAK_POINT = BIT(0),
BUS_ERROR = BIT(1),
CMD_FIFO_OVRFLOW = BIT(2),
MCS_STACK_OVRFLOW = BIT(3),
/* General IRQ types 4-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_INTSET_OFFSET \
......@@ -372,7 +354,6 @@ enum gsi_general_id {
#define GSI_ERROR_LOG_OFFSET \
(0x0001f200 + 0x4000 * GSI_EE_AP)
/* Fields below are present for IPA v3.5.1 and above */
#define ERR_ARG3_FMASK GENMASK(3, 0)
#define ERR_ARG2_FMASK GENMASK(7, 4)
#define ERR_ARG1_FMASK GENMASK(11, 8)
......
drivers/net/ipa/ipa.h
View file @ 01a7ee36
......@@ -45,7 +45,6 @@ struct ipa_interrupt;
* @interrupt: IPA Interrupt information
* @uc_powered: true if power is active by proxy for microcontroller
* @uc_loaded: true after microcontroller has reported it's ready
* @reg_addr: DMA address used for IPA register access
* @reg_virt: Virtual address used for IPA register access
* @regs: IPA register definitions
* @mem_addr: DMA address of IPA-local memory space
......@@ -97,9 +96,8 @@ struct ipa {
bool uc_powered;
bool uc_loaded;
dma_addr_t reg_addr;
void __iomem *reg_virt;
const struct ipa_regs *regs;
const struct regs *regs;
dma_addr_t mem_addr;
void *mem_virt;
......
drivers/net/ipa/ipa_cmd.c
View file @ 01a7ee36
......@@ -287,7 +287,7 @@ static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa,
/* Check whether offsets passed to register_write are valid */
static bool ipa_cmd_register_write_valid(struct ipa *ipa)
{
const struct ipa_reg *reg;
const struct reg *reg;
const char *name;
u32 offset;
......@@ -300,7 +300,7 @@ static bool ipa_cmd_register_write_valid(struct ipa *ipa)
else
reg = ipa_reg(ipa, FILT_ROUT_CACHE_FLUSH);
offset = ipa_reg_offset(reg);
offset = reg_offset(reg);
name = "filter/route hash flush";
if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
return false;
......@@ -314,7 +314,7 @@ static bool ipa_cmd_register_write_valid(struct ipa *ipa)
* fits in the register write command field(s) that must hold it.
*/
reg = ipa_reg(ipa, ENDP_STATUS);
offset = ipa_reg_n_offset(reg, IPA_ENDPOINT_COUNT - 1);
offset = reg_n_offset(reg, IPA_ENDPOINT_COUNT - 1);
name = "maximal endpoint status";
if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
return false;
......
drivers/net/ipa/ipa_endpoint.c
View file @ 01a7ee36
......@@ -241,7 +241,7 @@ static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count,
if (!data->toward_ipa) {
const struct ipa_endpoint_rx *rx_config;
const struct ipa_reg *reg;
const struct reg *reg;
u32 buffer_size;
u32 aggr_size;
u32 limit;
......@@ -304,7 +304,7 @@ static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count,
rx_config->aggr_hard_limit);
reg = ipa_reg(ipa, ENDP_INIT_AGGR);
limit = ipa_reg_field_max(reg, BYTE_LIMIT);
limit = reg_field_max(reg, BYTE_LIMIT);
if (aggr_size > limit) {
dev_err(dev, "aggregated size too large for RX endpoint %u (%u KB > %u KB)\n",
data->endpoint_id, aggr_size, limit);
......@@ -447,7 +447,7 @@ static bool
ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
{
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 field_id;
u32 offset;
bool state;
......@@ -460,11 +460,11 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
WARN_ON(ipa->version >= IPA_VERSION_4_0);
reg = ipa_reg(ipa, ENDP_INIT_CTRL);
offset = ipa_reg_n_offset(reg, endpoint->endpoint_id);
offset = reg_n_offset(reg, endpoint->endpoint_id);
val = ioread32(ipa->reg_virt + offset);
field_id = endpoint->toward_ipa ? ENDP_DELAY : ENDP_SUSPEND;
mask = ipa_reg_bit(reg, field_id);
mask = reg_bit(reg, field_id);
state = !!(val & mask);
......@@ -493,13 +493,13 @@ static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint)
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
u32 unit = endpoint_id / 32;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
WARN_ON(!test_bit(endpoint_id, ipa->available));
reg = ipa_reg(ipa, STATE_AGGR_ACTIVE);
val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit));
val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
return !!(val & BIT(endpoint_id % 32));
}
......@@ -510,12 +510,12 @@ static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint)
u32 mask = BIT(endpoint_id % 32);
struct ipa *ipa = endpoint->ipa;
u32 unit = endpoint_id / 32;
const struct ipa_reg *reg;
const struct reg *reg;
WARN_ON(!test_bit(endpoint_id, ipa->available));
reg = ipa_reg(ipa, AGGR_FORCE_CLOSE);
iowrite32(mask, ipa->reg_virt + ipa_reg_n_offset(reg, unit));
iowrite32(mask, ipa->reg_virt + reg_n_offset(reg, unit));
}
/**
......@@ -613,7 +613,7 @@ int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa)
for_each_set_bit(endpoint_id, ipa->defined, ipa->endpoint_count) {
struct ipa_endpoint *endpoint;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
/* We only reset modem TX endpoints */
......@@ -622,7 +622,7 @@ int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa)
continue;
reg = ipa_reg(ipa, ENDP_STATUS);
offset = ipa_reg_n_offset(reg, endpoint_id);
offset = reg_n_offset(reg, endpoint_id);
/* Value written is 0, and all bits are updated. That
* means status is disabled on the endpoint, and as a
......@@ -645,7 +645,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
enum ipa_cs_offload_en enabled;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
reg = ipa_reg(ipa, ENDP_INIT_CFG);
......@@ -658,7 +658,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
/* Checksum header offset is in 4-byte units */
off = sizeof(struct rmnet_map_header) / sizeof(u32);
val |= ipa_reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
val |= reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
enabled = version < IPA_VERSION_4_5
? IPA_CS_OFFLOAD_UL
......@@ -671,26 +671,26 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
} else {
enabled = IPA_CS_OFFLOAD_NONE;
}
val |= ipa_reg_encode(reg, CS_OFFLOAD_EN, enabled);
val |= reg_encode(reg, CS_OFFLOAD_EN, enabled);
/* CS_GEN_QMB_MASTER_SEL is 0 */
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
if (!endpoint->toward_ipa)
return;
reg = ipa_reg(ipa, ENDP_INIT_NAT);
val = ipa_reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS);
val = reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS);
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static u32
......@@ -716,13 +716,13 @@ ipa_qmap_header_size(enum ipa_version version, struct ipa_endpoint *endpoint)
/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */
static u32 ipa_header_size_encode(enum ipa_version version,
const struct ipa_reg *reg, u32 header_size)
const struct reg *reg, u32 header_size)
{
u32 field_max = ipa_reg_field_max(reg, HDR_LEN);
u32 field_max = reg_field_max(reg, HDR_LEN);
u32 val;
/* We know field_max can be used as a mask (2^n - 1) */
val = ipa_reg_encode(reg, HDR_LEN, header_size & field_max);
val = reg_encode(reg, HDR_LEN, header_size & field_max);
if (version < IPA_VERSION_4_5) {
WARN_ON(header_size > field_max);
return val;
......@@ -730,21 +730,21 @@ static u32 ipa_header_size_encode(enum ipa_version version,
/* IPA v4.5 adds a few more most-significant bits */
header_size >>= hweight32(field_max);
WARN_ON(header_size > ipa_reg_field_max(reg, HDR_LEN_MSB));
val |= ipa_reg_encode(reg, HDR_LEN_MSB, header_size);
WARN_ON(header_size > reg_field_max(reg, HDR_LEN_MSB));
val |= reg_encode(reg, HDR_LEN_MSB, header_size);
return val;
}
/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */
static u32 ipa_metadata_offset_encode(enum ipa_version version,
const struct ipa_reg *reg, u32 offset)
const struct reg *reg, u32 offset)
{
u32 field_max = ipa_reg_field_max(reg, HDR_OFST_METADATA);
u32 field_max = reg_field_max(reg, HDR_OFST_METADATA);
u32 val;
/* We know field_max can be used as a mask (2^n - 1) */
val = ipa_reg_encode(reg, HDR_OFST_METADATA, offset);
val = reg_encode(reg, HDR_OFST_METADATA, offset);
if (version < IPA_VERSION_4_5) {
WARN_ON(offset > field_max);
return val;
......@@ -752,8 +752,8 @@ static u32 ipa_metadata_offset_encode(enum ipa_version version,
/* IPA v4.5 adds a few more most-significant bits */
offset >>= hweight32(field_max);
WARN_ON(offset > ipa_reg_field_max(reg, HDR_OFST_METADATA_MSB));
val |= ipa_reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
WARN_ON(offset > reg_field_max(reg, HDR_OFST_METADATA_MSB));
val |= reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
return val;
}
......@@ -783,7 +783,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
reg = ipa_reg(ipa, ENDP_INIT_HDR);
......@@ -806,13 +806,13 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
off = offsetof(struct rmnet_map_header, pkt_len);
/* Upper bits are stored in HDR_EXT with IPA v4.5 */
if (version >= IPA_VERSION_4_5)
off &= ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);
off &= reg_field_max(reg, HDR_OFST_PKT_SIZE);
val |= ipa_reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);
val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE, off);
val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);
val |= reg_encode(reg, HDR_OFST_PKT_SIZE, off);
}
/* For QMAP TX, metadata offset is 0 (modem assumes this) */
val |= ipa_reg_bit(reg, HDR_OFST_METADATA_VALID);
val |= reg_bit(reg, HDR_OFST_METADATA_VALID);
/* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */
/* HDR_A5_MUX is 0 */
......@@ -820,7 +820,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
/* HDR_METADATA_REG_VALID is 0 (TX only, version < v4.5) */
}
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
......@@ -828,13 +828,13 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
u32 pad_align = endpoint->config.rx.pad_align;
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT);
if (endpoint->config.qmap) {
/* We have a header, so we must specify its endianness */
val |= ipa_reg_bit(reg, HDR_ENDIANNESS); /* big endian */
val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */
/* A QMAP header contains a 6 bit pad field at offset 0.
* The RMNet driver assumes this field is meaningful in
......@@ -844,16 +844,16 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
* (although 0) should be ignored.
*/
if (!endpoint->toward_ipa) {
val |= ipa_reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);
val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);
/* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
val |= ipa_reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);
val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
}
}
/* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
if (!endpoint->toward_ipa)
val |= ipa_reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
val |= reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
/* IPA v4.5 adds some most-significant bits to a few fields,
* two of which are defined in the HDR (not HDR_EXT) register.
......@@ -861,25 +861,25 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
if (ipa->version >= IPA_VERSION_4_5) {
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
if (endpoint->config.qmap && !endpoint->toward_ipa) {
u32 mask = ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);
u32 mask = reg_field_max(reg, HDR_OFST_PKT_SIZE);
u32 off; /* Field offset within header */
off = offsetof(struct rmnet_map_header, pkt_len);
/* Low bits are in the ENDP_INIT_HDR register */
off >>= hweight32(mask);
val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
val |= reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
/* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */
}
}
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
u32 offset;
......@@ -887,7 +887,7 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
return; /* Register not valid for TX endpoints */
reg = ipa_reg(ipa, ENDP_INIT_HDR_METADATA_MASK);
offset = ipa_reg_n_offset(reg, endpoint_id);
offset = reg_n_offset(reg, endpoint_id);
/* Note that HDR_ENDIANNESS indicates big endian header fields */
if (endpoint->config.qmap)
......@@ -899,7 +899,7 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
{
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
......@@ -911,14 +911,14 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
enum ipa_endpoint_name name = endpoint->config.dma_endpoint;
u32 dma_endpoint_id = ipa->name_map[name]->endpoint_id;
val = ipa_reg_encode(reg, ENDP_MODE, IPA_DMA);
val |= ipa_reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id);
val = reg_encode(reg, ENDP_MODE, IPA_DMA);
val |= reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id);
} else {
val = ipa_reg_encode(reg, ENDP_MODE, IPA_BASIC);
val = reg_encode(reg, ENDP_MODE, IPA_BASIC);
}
/* All other bits unspecified (and 0) */
offset = ipa_reg_n_offset(reg, endpoint->endpoint_id);
offset = reg_n_offset(reg, endpoint->endpoint_id);
iowrite32(val, ipa->reg_virt + offset);
}
......@@ -963,7 +963,7 @@ ipa_qtime_val(struct ipa *ipa, u32 microseconds, u32 max, u32 *select)
}
/* Encode the aggregation timer limit (microseconds) based on IPA version */
static u32 aggr_time_limit_encode(struct ipa *ipa, const struct ipa_reg *reg,
static u32 aggr_time_limit_encode(struct ipa *ipa, const struct reg *reg,
u32 microseconds)
{
u32 ticks;
......@@ -972,14 +972,14 @@ static u32 aggr_time_limit_encode(struct ipa *ipa, const struct ipa_reg *reg,
if (!microseconds)
return 0; /* Nothing to compute if time limit is 0 */
max = ipa_reg_field_max(reg, TIME_LIMIT);
max = reg_field_max(reg, TIME_LIMIT);
if (ipa->version >= IPA_VERSION_4_5) {
u32 select;
ticks = ipa_qtime_val(ipa, microseconds, max, &select);
return ipa_reg_encode(reg, AGGR_GRAN_SEL, select) |
ipa_reg_encode(reg, TIME_LIMIT, ticks);
return reg_encode(reg, AGGR_GRAN_SEL, select) |
reg_encode(reg, TIME_LIMIT, ticks);
}
/* We program aggregation granularity in ipa_hardware_config() */
......@@ -987,14 +987,14 @@ static u32 aggr_time_limit_encode(struct ipa *ipa, const struct ipa_reg *reg,
WARN(ticks > max, "aggr_time_limit too large (%u > %u usec)\n",
microseconds, max * IPA_AGGR_GRANULARITY);
return ipa_reg_encode(reg, TIME_LIMIT, ticks);
return reg_encode(reg, TIME_LIMIT, ticks);
}
static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
reg = ipa_reg(ipa, ENDP_INIT_AGGR);
......@@ -1005,13 +1005,13 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
u32 limit;
rx_config = &endpoint->config.rx;
val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR);
val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_GENERIC);
val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR);
val |= reg_encode(reg, AGGR_TYPE, IPA_GENERIC);
buffer_size = rx_config->buffer_size;
limit = ipa_aggr_size_kb(buffer_size - NET_SKB_PAD,
rx_config->aggr_hard_limit);
val |= ipa_reg_encode(reg, BYTE_LIMIT, limit);
val |= reg_encode(reg, BYTE_LIMIT, limit);
limit = rx_config->aggr_time_limit;
val |= aggr_time_limit_encode(ipa, reg, limit);
......@@ -1019,20 +1019,20 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
/* AGGR_PKT_LIMIT is 0 (unlimited) */
if (rx_config->aggr_close_eof)
val |= ipa_reg_bit(reg, SW_EOF_ACTIVE);
val |= reg_bit(reg, SW_EOF_ACTIVE);
} else {
val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR);
val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_QCMAP);
val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR);
val |= reg_encode(reg, AGGR_TYPE, IPA_QCMAP);
/* other fields ignored */
}
/* AGGR_FORCE_CLOSE is 0 */
/* AGGR_GRAN_SEL is 0 for IPA v4.5 */
} else {
val |= ipa_reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR);
val |= reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR);
/* other fields ignored */
}
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
/* The head-of-line blocking timer is defined as a tick count. For
......@@ -1043,7 +1043,7 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
* Return the encoded value representing the timeout period provided
* that should be written to the ENDP_INIT_HOL_BLOCK_TIMER register.
*/
static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg,
static u32 hol_block_timer_encode(struct ipa *ipa, const struct reg *reg,
u32 microseconds)
{
u32 width;
......@@ -1057,14 +1057,14 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg,
return 0; /* Nothing to compute if timer period is 0 */
if (ipa->version >= IPA_VERSION_4_5) {
u32 max = ipa_reg_field_max(reg, TIMER_LIMIT);
u32 max = reg_field_max(reg, TIMER_LIMIT);
u32 select;
u32 ticks;
ticks = ipa_qtime_val(ipa, microseconds, max, &select);
return ipa_reg_encode(reg, TIMER_GRAN_SEL, 1) |
ipa_reg_encode(reg, TIMER_LIMIT, ticks);
return reg_encode(reg, TIMER_GRAN_SEL, 1) |
reg_encode(reg, TIMER_LIMIT, ticks);
}
/* Use 64 bit arithmetic to avoid overflow */
......@@ -1072,11 +1072,11 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg,
ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC);
/* We still need the result to fit into the field */
WARN_ON(ticks > ipa_reg_field_max(reg, TIMER_BASE_VALUE));
WARN_ON(ticks > reg_field_max(reg, TIMER_BASE_VALUE));
/* IPA v3.5.1 through v4.1 just record the tick count */
if (ipa->version < IPA_VERSION_4_2)
return ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks);
return reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks);
/* For IPA v4.2, the tick count is represented by base and
* scale fields within the 32-bit timer register, where:
......@@ -1087,7 +1087,7 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg,
* such that high bit is included.
*/
high = fls(ticks); /* 1..32 (or warning above) */
width = hweight32(ipa_reg_fmask(reg, TIMER_BASE_VALUE));
width = hweight32(reg_fmask(reg, TIMER_BASE_VALUE));
scale = high > width ? high - width : 0;
if (scale) {
/* If we're scaling, round up to get a closer result */
......@@ -1097,8 +1097,8 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg,
scale++;
}
val = ipa_reg_encode(reg, TIMER_SCALE, scale);
val |= ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale);
val = reg_encode(reg, TIMER_SCALE, scale);
val |= reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale);
return val;
}
......@@ -1109,14 +1109,14 @@ static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint,
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
/* This should only be changed when HOL_BLOCK_EN is disabled */
reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_TIMER);
val = hol_block_timer_encode(ipa, reg, microseconds);
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void
......@@ -1124,13 +1124,13 @@ ipa_endpoint_init_hol_block_en(struct ipa_endpoint *endpoint, bool enable)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_EN);
offset = ipa_reg_n_offset(reg, endpoint_id);
val = enable ? ipa_reg_bit(reg, HOL_BLOCK_EN) : 0;
offset = reg_n_offset(reg, endpoint_id);
val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0;
iowrite32(val, ipa->reg_virt + offset);
......@@ -1171,7 +1171,7 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
if (!endpoint->toward_ipa)
......@@ -1183,7 +1183,7 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
/* PACKET_OFFSET_LOCATION is ignored (not valid) */
/* MAX_PACKET_LEN is 0 (not enforced) */
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
......@@ -1191,20 +1191,20 @@ static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
u32 resource_group = endpoint->config.resource_group;
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
reg = ipa_reg(ipa, ENDP_INIT_RSRC_GRP);
val = ipa_reg_encode(reg, ENDP_RSRC_GRP, resource_group);
val = reg_encode(reg, ENDP_RSRC_GRP, resource_group);
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
if (!endpoint->toward_ipa)
......@@ -1213,14 +1213,14 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
reg = ipa_reg(ipa, ENDP_INIT_SEQ);
/* Low-order byte configures primary packet processing */
val = ipa_reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type);
val = reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type);
/* Second byte (if supported) configures replicated packet processing */
if (ipa->version < IPA_VERSION_4_5)
val |= ipa_reg_encode(reg, SEQ_REP_TYPE,
endpoint->config.tx.seq_rep_type);
val |= reg_encode(reg, SEQ_REP_TYPE,
endpoint->config.tx.seq_rep_type);
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
/**
......@@ -1270,12 +1270,12 @@ static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val = 0;
reg = ipa_reg(ipa, ENDP_STATUS);
if (endpoint->config.status_enable) {
val |= ipa_reg_bit(reg, STATUS_EN);
val |= reg_bit(reg, STATUS_EN);
if (endpoint->toward_ipa) {
enum ipa_endpoint_name name;
u32 status_endpoint_id;
......@@ -1283,8 +1283,7 @@ static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
name = endpoint->config.tx.status_endpoint;
status_endpoint_id = ipa->name_map[name]->endpoint_id;
val |= ipa_reg_encode(reg, STATUS_ENDP,
status_endpoint_id);
val |= reg_encode(reg, STATUS_ENDP, status_endpoint_id);
}
/* STATUS_LOCATION is 0, meaning IPA packet status
* precedes the packet (not present for IPA v4.5+)
......@@ -1292,7 +1291,7 @@ static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
/* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v4.0+) */
}
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
}
static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint,
......@@ -1636,18 +1635,18 @@ void ipa_endpoint_trans_release(struct ipa_endpoint *endpoint,
void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
reg = ipa_reg(ipa, ROUTE);
/* ROUTE_DIS is 0 */
val = ipa_reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id);
val |= ipa_reg_bit(reg, ROUTE_DEF_HDR_TABLE);
val = reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id);
val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE);
/* ROUTE_DEF_HDR_OFST is 0 */
val |= ipa_reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id);
val |= ipa_reg_bit(reg, ROUTE_DEF_RETAIN_HDR);
val |= reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id);
val |= reg_bit(reg, ROUTE_DEF_RETAIN_HDR);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
void ipa_endpoint_default_route_clear(struct ipa *ipa)
......@@ -1985,7 +1984,7 @@ void ipa_endpoint_deconfig(struct ipa *ipa)
int ipa_endpoint_config(struct ipa *ipa)
{
struct device *dev = &ipa->pdev->dev;
const struct ipa_reg *reg;
const struct reg *reg;
u32 endpoint_id;
u32 hw_limit;
u32 tx_count;
......@@ -2019,12 +2018,12 @@ int ipa_endpoint_config(struct ipa *ipa)
* the highest one doesn't exceed the number supported by software.
*/
reg = ipa_reg(ipa, FLAVOR_0);
val = ioread32(ipa->reg_virt + ipa_reg_offset(reg));
val = ioread32(ipa->reg_virt + reg_offset(reg));
/* Our RX is an IPA producer; our TX is an IPA consumer. */
tx_count = ipa_reg_decode(reg, MAX_CONS_PIPES, val);
rx_count = ipa_reg_decode(reg, MAX_PROD_PIPES, val);
rx_base = ipa_reg_decode(reg, PROD_LOWEST, val);
tx_count = reg_decode(reg, MAX_CONS_PIPES, val);
rx_count = reg_decode(reg, MAX_PROD_PIPES, val);
rx_base = reg_decode(reg, PROD_LOWEST, val);
limit = rx_base + rx_count;
if (limit > IPA_ENDPOINT_MAX) {
......
drivers/net/ipa/ipa_interrupt.c
View file @ 01a7ee36
......@@ -47,12 +47,12 @@ struct ipa_interrupt {
static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
{
struct ipa *ipa = interrupt->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 mask = BIT(irq_id);
u32 offset;
reg = ipa_reg(ipa, IPA_IRQ_CLR);
offset = ipa_reg_offset(reg);
offset = reg_offset(reg);
switch (irq_id) {
case IPA_IRQ_UC_0:
......@@ -85,7 +85,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
struct ipa_interrupt *interrupt = dev_id;
struct ipa *ipa = interrupt->ipa;
u32 enabled = interrupt->enabled;
const struct ipa_reg *reg;
const struct reg *reg;
struct device *dev;
u32 pending;
u32 offset;
......@@ -102,7 +102,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
* only the enabled ones.
*/
reg = ipa_reg(ipa, IPA_IRQ_STTS);
offset = ipa_reg_offset(reg);
offset = reg_offset(reg);
pending = ioread32(ipa->reg_virt + offset);
while ((mask = pending & enabled)) {
do {
......@@ -120,8 +120,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n",
pending);
reg = ipa_reg(ipa, IPA_IRQ_CLR);
offset = ipa_reg_offset(reg);
iowrite32(pending, ipa->reg_virt + offset);
iowrite32(pending, ipa->reg_virt + reg_offset(reg));
}
out_power_put:
pm_runtime_mark_last_busy(dev);
......@@ -132,9 +131,9 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
static void ipa_interrupt_enabled_update(struct ipa *ipa)
{
const struct ipa_reg *reg = ipa_reg(ipa, IPA_IRQ_EN);
const struct reg *reg = ipa_reg(ipa, IPA_IRQ_EN);
iowrite32(ipa->interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg));
}
/* Enable an IPA interrupt type */
......@@ -170,7 +169,7 @@ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
struct ipa *ipa = interrupt->ipa;
u32 mask = BIT(endpoint_id % 32);
u32 unit = endpoint_id / 32;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
......@@ -181,7 +180,7 @@ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
return;
reg = ipa_reg(ipa, IRQ_SUSPEND_EN);
offset = ipa_reg_n_offset(reg, unit);
offset = reg_n_offset(reg, unit);
val = ioread32(ipa->reg_virt + offset);
if (enable)
......@@ -215,18 +214,18 @@ void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
unit_count = roundup(ipa->endpoint_count, 32);
for (unit = 0; unit < unit_count; unit++) {
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
reg = ipa_reg(ipa, IRQ_SUSPEND_INFO);
val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit));
val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
/* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
if (ipa->version == IPA_VERSION_3_0)
continue;
reg = ipa_reg(ipa, IRQ_SUSPEND_CLR);
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, unit));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit));
}
}
......@@ -241,7 +240,7 @@ struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
{
struct device *dev = &ipa->pdev->dev;
struct ipa_interrupt *interrupt;
const struct ipa_reg *reg;
const struct reg *reg;
unsigned int irq;
int ret;
......@@ -261,7 +260,7 @@ struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
/* Start with all IPA interrupts disabled */
reg = ipa_reg(ipa, IPA_IRQ_EN);
iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(0, ipa->reg_virt + reg_offset(reg));
ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT,
"ipa", interrupt);
......
drivers/net/ipa/ipa_main.c
View file @ 01a7ee36
......@@ -203,7 +203,7 @@ static void ipa_teardown(struct ipa *ipa)
static void
ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
/* IPA v4.5+ has no backward compatibility register */
......@@ -212,13 +212,13 @@ ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data)
reg = ipa_reg(ipa, IPA_BCR);
val = data->backward_compat;
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
static void ipa_hardware_config_tx(struct ipa *ipa)
{
enum ipa_version version = ipa->version;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
......@@ -227,11 +227,11 @@ static void ipa_hardware_config_tx(struct ipa *ipa)
/* Disable PA mask to allow HOLB drop */
reg = ipa_reg(ipa, IPA_TX_CFG);
offset = ipa_reg_offset(reg);
offset = reg_offset(reg);
val = ioread32(ipa->reg_virt + offset);
val &= ~ipa_reg_bit(reg, PA_MASK_EN);
val &= ~reg_bit(reg, PA_MASK_EN);
iowrite32(val, ipa->reg_virt + offset);
}
......@@ -239,7 +239,7 @@ static void ipa_hardware_config_tx(struct ipa *ipa)
static void ipa_hardware_config_clkon(struct ipa *ipa)
{
enum ipa_version version = ipa->version;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
if (version >= IPA_VERSION_4_5)
......@@ -252,20 +252,20 @@ static void ipa_hardware_config_clkon(struct ipa *ipa)
reg = ipa_reg(ipa, CLKON_CFG);
if (version == IPA_VERSION_3_1) {
/* Disable MISC clock gating */
val = ipa_reg_bit(reg, CLKON_MISC);
val = reg_bit(reg, CLKON_MISC);
} else { /* IPA v4.0+ */
/* Enable open global clocks in the CLKON configuration */
val = ipa_reg_bit(reg, CLKON_GLOBAL);
val |= ipa_reg_bit(reg, GLOBAL_2X_CLK);
val = reg_bit(reg, CLKON_GLOBAL);
val |= reg_bit(reg, GLOBAL_2X_CLK);
}
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
/* Configure bus access behavior for IPA components */
static void ipa_hardware_config_comp(struct ipa *ipa)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
......@@ -274,21 +274,22 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
return;
reg = ipa_reg(ipa, COMP_CFG);
offset = ipa_reg_offset(reg);
offset = reg_offset(reg);
val = ioread32(ipa->reg_virt + offset);
if (ipa->version == IPA_VERSION_4_0) {
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_CONS_EN);
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_PROD_EN);
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN);
val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN);
val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN);
val &= ~reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN);
} else if (ipa->version < IPA_VERSION_4_5) {
val |= ipa_reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);
val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);
} else {
/* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
}
val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);
val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_WR_DIS);
val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);
val |= reg_bit(reg, GSI_MULTI_INORDER_WR_DIS);
iowrite32(val, ipa->reg_virt + offset);
}
......@@ -299,7 +300,7 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
{
const struct ipa_qsb_data *data0;
const struct ipa_qsb_data *data1;
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
/* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */
......@@ -310,29 +311,27 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
/* Max outstanding write accesses for QSB masters */
reg = ipa_reg(ipa, QSB_MAX_WRITES);
val = ipa_reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes);
val = reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes);
if (data->qsb_count > 1)
val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_WRITES,
data1->max_writes);
val |= reg_encode(reg, GEN_QMB_1_MAX_WRITES, data1->max_writes);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
/* Max outstanding read accesses for QSB masters */
reg = ipa_reg(ipa, QSB_MAX_READS);
val = ipa_reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads);
val = reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads);
if (ipa->version >= IPA_VERSION_4_0)
val |= ipa_reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS,
data0->max_reads_beats);
val |= reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS,
data0->max_reads_beats);
if (data->qsb_count > 1) {
val = ipa_reg_encode(reg, GEN_QMB_1_MAX_READS,
data1->max_reads);
val = reg_encode(reg, GEN_QMB_1_MAX_READS, data1->max_reads);
if (ipa->version >= IPA_VERSION_4_0)
val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS,
data1->max_reads_beats);
val |= reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS,
data1->max_reads_beats);
}
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
/* The internal inactivity timer clock is used for the aggregation timer */
......@@ -368,46 +367,47 @@ static __always_inline u32 ipa_aggr_granularity_val(u32 usec)
*/
static void ipa_qtime_config(struct ipa *ipa)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
/* Timer clock divider must be disabled when we change the rate */
reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG);
iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(0, ipa->reg_virt + reg_offset(reg));
reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG);
/* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */
val = ipa_reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);
val |= ipa_reg_bit(reg, DPL_TIMESTAMP_SEL);
val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);
val |= reg_bit(reg, DPL_TIMESTAMP_SEL);
/* Configure tag and NAT Qtime timestamp resolution as well */
val = ipa_reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);
val = ipa_reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);
val = reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);
val = reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
/* Set granularity of pulse generators used for other timers */
reg = ipa_reg(ipa, TIMERS_PULSE_GRAN_CFG);
val = ipa_reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US);
val |= ipa_reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS);
val = reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US);
val |= reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS);
if (ipa->version >= IPA_VERSION_5_0) {
val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_10_MS);
val |= ipa_reg_encode(reg, PULSE_GRAN_3, IPA_GRAN_10_MS);
val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_10_MS);
val |= reg_encode(reg, PULSE_GRAN_3, IPA_GRAN_10_MS);
} else {
val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS);
val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS);
}
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
/* Actual divider is 1 more than value supplied here */
reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG);
offset = ipa_reg_offset(reg);
val = ipa_reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1);
offset = reg_offset(reg);
val = reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1);
iowrite32(val, ipa->reg_virt + offset);
/* Divider value is set; re-enable the common timer clock divider */
val |= ipa_reg_bit(reg, DIV_ENABLE);
val |= reg_bit(reg, DIV_ENABLE);
iowrite32(val, ipa->reg_virt + offset);
}
......@@ -416,13 +416,13 @@ static void ipa_qtime_config(struct ipa *ipa)
static void ipa_hardware_config_counter(struct ipa *ipa)
{
u32 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY);
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
reg = ipa_reg(ipa, COUNTER_CFG);
/* If defined, EOT_COAL_GRANULARITY is 0 */
val = ipa_reg_encode(reg, AGGR_GRANULARITY, granularity);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
val = reg_encode(reg, AGGR_GRANULARITY, granularity);
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
static void ipa_hardware_config_timing(struct ipa *ipa)
......@@ -435,7 +435,7 @@ static void ipa_hardware_config_timing(struct ipa *ipa)
static void ipa_hardware_config_hashing(struct ipa *ipa)
{
const struct ipa_reg *reg;
const struct reg *reg;
/* Other than IPA v4.2, all versions enable "hashing". Starting
* with IPA v5.0, the filter and router tables are implemented
......@@ -451,26 +451,26 @@ static void ipa_hardware_config_hashing(struct ipa *ipa)
/* IPV6_ROUTER_HASH, IPV6_FILTER_HASH, IPV4_ROUTER_HASH,
* IPV4_FILTER_HASH are all zero.
*/
iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(0, ipa->reg_virt + reg_offset(reg));
}
static void ipa_idle_indication_cfg(struct ipa *ipa,
u32 enter_idle_debounce_thresh,
bool const_non_idle_enable)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
if (ipa->version < IPA_VERSION_3_5_1)
return;
reg = ipa_reg(ipa, IDLE_INDICATION_CFG);
val = ipa_reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH,
enter_idle_debounce_thresh);
val = reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH,
enter_idle_debounce_thresh);
if (const_non_idle_enable)
val |= ipa_reg_bit(reg, CONST_NON_IDLE_ENABLE);
val |= reg_bit(reg, CONST_NON_IDLE_ENABLE);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
/**
......
drivers/net/ipa/ipa_mem.c
View file @ 01a7ee36
......@@ -75,7 +75,7 @@ ipa_mem_zero_region_add(struct gsi_trans *trans, enum ipa_mem_id mem_id)
int ipa_mem_setup(struct ipa *ipa)
{
dma_addr_t addr = ipa->zero_addr;
const struct ipa_reg *reg;
const struct reg *reg;
const struct ipa_mem *mem;
struct gsi_trans *trans;
u32 offset;
......@@ -115,8 +115,8 @@ int ipa_mem_setup(struct ipa *ipa)
offset = ipa->mem_offset + mem->offset;
reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT);
val = ipa_reg_encode(reg, IPA_BASE_ADDR, offset);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
val = reg_encode(reg, IPA_BASE_ADDR, offset);
iowrite32(val, ipa->reg_virt + reg_offset(reg));
return 0;
}
......@@ -318,8 +318,8 @@ static bool ipa_mem_size_valid(struct ipa *ipa)
int ipa_mem_config(struct ipa *ipa)
{
struct device *dev = &ipa->pdev->dev;
const struct ipa_reg *reg;
const struct ipa_mem *mem;
const struct reg *reg;
dma_addr_t addr;
u32 mem_size;
void *virt;
......@@ -328,13 +328,13 @@ int ipa_mem_config(struct ipa *ipa)
/* Check the advertised location and size of the shared memory area */
reg = ipa_reg(ipa, SHARED_MEM_SIZE);
val = ioread32(ipa->reg_virt + ipa_reg_offset(reg));
val = ioread32(ipa->reg_virt + reg_offset(reg));
/* The fields in the register are in 8 byte units */
ipa->mem_offset = 8 * ipa_reg_decode(reg, MEM_BADDR, val);
ipa->mem_offset = 8 * reg_decode(reg, MEM_BADDR, val);
/* Make sure the end is within the region's mapped space */
mem_size = 8 * ipa_reg_decode(reg, MEM_SIZE, val);
mem_size = 8 * reg_decode(reg, MEM_SIZE, val);
/* If the sizes don't match, issue a warning */
if (ipa->mem_offset + mem_size < ipa->mem_size) {
......
drivers/net/ipa/ipa_reg.c
View file @ 01a7ee36
......@@ -9,73 +9,96 @@
#include "ipa.h"
#include "ipa_reg.h"
/* Is this register valid and defined for the current IPA version? */
static bool ipa_reg_valid(struct ipa *ipa, enum ipa_reg_id reg_id)
/* Is this register ID valid for the current IPA version? */
static bool ipa_reg_id_valid(struct ipa *ipa, enum ipa_reg_id reg_id)
{
enum ipa_version version = ipa->version;
bool valid;
/* Check for bogus (out of range) register IDs */
if ((u32)reg_id >= ipa->regs->reg_count)
return false;
switch (reg_id) {
case IPA_BCR:
case COUNTER_CFG:
valid = version < IPA_VERSION_4_5;
break;
return version < IPA_VERSION_4_5;
case IPA_TX_CFG:
case FLAVOR_0:
case IDLE_INDICATION_CFG:
valid = version >= IPA_VERSION_3_5;
break;
return version >= IPA_VERSION_3_5;
case QTIME_TIMESTAMP_CFG:
case TIMERS_XO_CLK_DIV_CFG:
case TIMERS_PULSE_GRAN_CFG:
valid = version >= IPA_VERSION_4_5;
break;
return version >= IPA_VERSION_4_5;
case SRC_RSRC_GRP_45_RSRC_TYPE:
case DST_RSRC_GRP_45_RSRC_TYPE:
valid = version <= IPA_VERSION_3_1 ||
version == IPA_VERSION_4_5;
break;
return version <= IPA_VERSION_3_1 ||
version == IPA_VERSION_4_5;
case SRC_RSRC_GRP_67_RSRC_TYPE:
case DST_RSRC_GRP_67_RSRC_TYPE:
valid = version <= IPA_VERSION_3_1;
break;
return version <= IPA_VERSION_3_1;
case ENDP_FILTER_ROUTER_HSH_CFG:
valid = version != IPA_VERSION_4_2;
break;
return version != IPA_VERSION_4_2;
case IRQ_SUSPEND_EN:
case IRQ_SUSPEND_CLR:
valid = version >= IPA_VERSION_3_1;
break;
return version >= IPA_VERSION_3_1;
case COMP_CFG:
case CLKON_CFG:
case ROUTE:
case SHARED_MEM_SIZE:
case QSB_MAX_WRITES:
case QSB_MAX_READS:
case FILT_ROUT_HASH_EN:
case FILT_ROUT_CACHE_CFG:
case FILT_ROUT_HASH_FLUSH:
case FILT_ROUT_CACHE_FLUSH:
case STATE_AGGR_ACTIVE:
case LOCAL_PKT_PROC_CNTXT:
case AGGR_FORCE_CLOSE:
case SRC_RSRC_GRP_01_RSRC_TYPE:
case SRC_RSRC_GRP_23_RSRC_TYPE:
case DST_RSRC_GRP_01_RSRC_TYPE:
case DST_RSRC_GRP_23_RSRC_TYPE:
case ENDP_INIT_CTRL:
case ENDP_INIT_CFG:
case ENDP_INIT_NAT:
case ENDP_INIT_HDR:
case ENDP_INIT_HDR_EXT:
case ENDP_INIT_HDR_METADATA_MASK:
case ENDP_INIT_MODE:
case ENDP_INIT_AGGR:
case ENDP_INIT_HOL_BLOCK_EN:
case ENDP_INIT_HOL_BLOCK_TIMER:
case ENDP_INIT_DEAGGR:
case ENDP_INIT_RSRC_GRP:
case ENDP_INIT_SEQ:
case ENDP_STATUS:
case ENDP_FILTER_CACHE_CFG:
case ENDP_ROUTER_CACHE_CFG:
case IPA_IRQ_STTS:
case IPA_IRQ_EN:
case IPA_IRQ_CLR:
case IPA_IRQ_UC:
case IRQ_SUSPEND_INFO:
return true; /* These should be defined for all versions */
default:
valid = true; /* Others should be defined for all versions */
break;
return false;
}
/* To be valid, it must be defined */
return valid && ipa->regs->reg[reg_id];
}
const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id)
const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id)
{
if (WARN_ON(!ipa_reg_valid(ipa, reg_id)))
if (WARN(!ipa_reg_id_valid(ipa, reg_id), "invalid reg %u\n", reg_id))
return NULL;
return ipa->regs->reg[reg_id];
return reg(ipa->regs, reg_id);
}
static const struct ipa_regs *ipa_regs(enum ipa_version version)
static const struct regs *ipa_regs(enum ipa_version version)
{
switch (version) {
case IPA_VERSION_3_1:
......@@ -100,7 +123,7 @@ static const struct ipa_regs *ipa_regs(enum ipa_version version)
int ipa_reg_init(struct ipa *ipa)
{
struct device *dev = &ipa->pdev->dev;
const struct ipa_regs *regs;
const struct regs *regs;
struct resource *res;
regs = ipa_regs(ipa->version);
......@@ -123,7 +146,6 @@ int ipa_reg_init(struct ipa *ipa)
dev_err(dev, "unable to remap \"ipa-reg\" memory\n");
return -ENOMEM;
}
ipa->reg_addr = res->start;
ipa->regs = regs;
return 0;
......
drivers/net/ipa/ipa_reg.h
View file @ 01a7ee36
......@@ -10,6 +10,7 @@
#include <linux/bug.h>
#include "ipa_version.h"
#include "reg.h"
struct ipa;
......@@ -35,7 +36,7 @@ struct ipa;
* by register ID. Each entry in the array specifies the base offset and
* (for parameterized registers) a non-zero stride value. Not all versions
* of IPA define all registers. The offset for a register is returned by
* ipa_reg_offset() when the register's ipa_reg structure is supplied;
* reg_offset() when the register's ipa_reg structure is supplied;
* zero is returned for an undefined register (this should never happen).
*
* Some registers encode multiple fields within them. Each field in
......@@ -44,9 +45,9 @@ struct ipa;
* an array of field masks, indexed by field ID. Two functions are
* used to access register fields; both take an ipa_reg structure as
* argument. To encode a value to be represented in a register field,
* the value and field ID are passed to ipa_reg_encode(). To extract
* the value and field ID are passed to reg_encode(). To extract
* a value encoded in a register field, the field ID is passed to
* ipa_reg_decode(). In addition, for single-bit fields, ipa_reg_bit()
* reg_decode(). In addition, for single-bit fields, reg_bit()
* can be used to either encode the bit value, or to generate a mask
* used to extract the bit value.
*/
......@@ -110,56 +111,6 @@ enum ipa_reg_id {
IPA_REG_ID_COUNT, /* Last; not an ID */
};
/**
* struct ipa_reg - An IPA register descriptor
* @offset: Register offset relative to base of the "ipa-reg" memory
* @stride: Distance between two instances, if parameterized
* @fcount: Number of entries in the @fmask array
* @fmask: Array of mask values defining position and width of fields
* @name: Upper-case name of the IPA register
*/
struct ipa_reg {
u32 offset;
u32 stride;
u32 fcount;
const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */
const char *name;
};
/* Helper macro for defining "simple" (non-parameterized) registers */
#define IPA_REG(__NAME, __reg_id, __offset) \
IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0)
/* Helper macro for defining parameterized registers, specifying stride */
#define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \
static const struct ipa_reg ipa_reg_ ## __reg_id = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
}
#define IPA_REG_FIELDS(__NAME, __name, __offset) \
IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0)
#define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \
static const struct ipa_reg ipa_reg_ ## __name = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
.fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \
.fmask = ipa_reg_ ## __name ## _fmask, \
}
/**
* struct ipa_regs - Description of registers supported by hardware
* @reg_count: Number of registers in the @reg[] array
* @reg: Array of register descriptors
*/
struct ipa_regs {
u32 reg_count;
const struct ipa_reg **reg;
};
/* COMP_CFG register */
enum ipa_reg_comp_cfg_field_id {
COMP_CFG_ENABLE, /* Not IPA v4.0+ */
......@@ -687,79 +638,15 @@ enum ipa_reg_ipa_irq_uc_field_id {
UC_INTR,
};
extern const struct ipa_regs ipa_regs_v3_1;
extern const struct ipa_regs ipa_regs_v3_5_1;
extern const struct ipa_regs ipa_regs_v4_2;
extern const struct ipa_regs ipa_regs_v4_5;
extern const struct ipa_regs ipa_regs_v4_7;
extern const struct ipa_regs ipa_regs_v4_9;
extern const struct ipa_regs ipa_regs_v4_11;
/* Return the field mask for a field in a register */
static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id)
{
if (!reg || WARN_ON(field_id >= reg->fcount))
return 0;
return reg->fmask[field_id];
}
/* Return the mask for a single-bit field in a register */
static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id)
{
u32 fmask = ipa_reg_fmask(reg, field_id);
WARN_ON(!is_power_of_2(fmask));
return fmask;
}
/* Encode a value into the given field of a register */
static inline u32
ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val)
{
u32 fmask = ipa_reg_fmask(reg, field_id);
if (!fmask)
return 0;
val <<= __ffs(fmask);
if (WARN_ON(val & ~fmask))
return 0;
return val;
}
/* Given a register value, decode (extract) the value in the given field */
static inline u32
ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val)
{
u32 fmask = ipa_reg_fmask(reg, field_id);
return fmask ? (val & fmask) >> __ffs(fmask) : 0;
}
/* Return the maximum value representable by the given field; always 2^n - 1 */
static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id)
{
u32 fmask = ipa_reg_fmask(reg, field_id);
return fmask ? fmask >> __ffs(fmask) : 0;
}
const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
/* Returns 0 for NULL reg; warning will have already been issued */
static inline u32 ipa_reg_offset(const struct ipa_reg *reg)
{
return reg ? reg->offset : 0;
}
extern const struct regs ipa_regs_v3_1;
extern const struct regs ipa_regs_v3_5_1;
extern const struct regs ipa_regs_v4_2;
extern const struct regs ipa_regs_v4_5;
extern const struct regs ipa_regs_v4_7;
extern const struct regs ipa_regs_v4_9;
extern const struct regs ipa_regs_v4_11;
/* Returns 0 for NULL reg; warning will have already been issued */
static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n)
{
return reg ? reg->offset + n * reg->stride : 0;
}
const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
int ipa_reg_init(struct ipa *ipa);
void ipa_reg_exit(struct ipa *ipa);
......
drivers/net/ipa/ipa_resource.c
View file @ 01a7ee36
......@@ -70,20 +70,20 @@ static bool ipa_resource_limits_valid(struct ipa *ipa,
static void
ipa_resource_config_common(struct ipa *ipa, u32 resource_type,
const struct ipa_reg *reg,
const struct reg *reg,
const struct ipa_resource_limits *xlimits,
const struct ipa_resource_limits *ylimits)
{
u32 val;
val = ipa_reg_encode(reg, X_MIN_LIM, xlimits->min);
val |= ipa_reg_encode(reg, X_MAX_LIM, xlimits->max);
val = reg_encode(reg, X_MIN_LIM, xlimits->min);
val |= reg_encode(reg, X_MAX_LIM, xlimits->max);
if (ylimits) {
val |= ipa_reg_encode(reg, Y_MIN_LIM, ylimits->min);
val |= ipa_reg_encode(reg, Y_MAX_LIM, ylimits->max);
val |= reg_encode(reg, Y_MIN_LIM, ylimits->min);
val |= reg_encode(reg, Y_MAX_LIM, ylimits->max);
}
iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, resource_type));
iowrite32(val, ipa->reg_virt + reg_n_offset(reg, resource_type));
}
static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type,
......@@ -92,7 +92,7 @@ static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type,
u32 group_count = data->rsrc_group_src_count;
const struct ipa_resource_limits *ylimits;
const struct ipa_resource *resource;
const struct ipa_reg *reg;
const struct reg *reg;
resource = &data->resource_src[resource_type];
......@@ -129,7 +129,7 @@ static void ipa_resource_config_dst(struct ipa *ipa, u32 resource_type,
u32 group_count = data->rsrc_group_dst_count;
const struct ipa_resource_limits *ylimits;
const struct ipa_resource *resource;
const struct ipa_reg *reg;
const struct reg *reg;
resource = &data->resource_dst[resource_type];
......
drivers/net/ipa/ipa_table.c
View file @ 01a7ee36
......@@ -345,9 +345,8 @@ void ipa_table_reset(struct ipa *ipa, bool modem)
int ipa_table_hash_flush(struct ipa *ipa)
{
const struct ipa_reg *reg;
struct gsi_trans *trans;
u32 offset;
const struct reg *reg;
u32 val;
if (!ipa_table_hash_support(ipa))
......@@ -361,22 +360,20 @@ int ipa_table_hash_flush(struct ipa *ipa)
if (ipa->version < IPA_VERSION_5_0) {
reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH);
offset = ipa_reg_offset(reg);
val = ipa_reg_bit(reg, IPV6_ROUTER_HASH);
val |= ipa_reg_bit(reg, IPV6_FILTER_HASH);
val |= ipa_reg_bit(reg, IPV4_ROUTER_HASH);
val |= ipa_reg_bit(reg, IPV4_FILTER_HASH);
val = reg_bit(reg, IPV6_ROUTER_HASH);
val |= reg_bit(reg, IPV6_FILTER_HASH);
val |= reg_bit(reg, IPV4_ROUTER_HASH);
val |= reg_bit(reg, IPV4_FILTER_HASH);
} else {
reg = ipa_reg(ipa, FILT_ROUT_CACHE_FLUSH);
offset = ipa_reg_offset(reg);
/* IPA v5.0+ uses a unified cache (both IPv4 and IPv6) */
val = ipa_reg_bit(reg, ROUTER_CACHE);
val |= ipa_reg_bit(reg, FILTER_CACHE);
val = reg_bit(reg, ROUTER_CACHE);
val |= reg_bit(reg, FILTER_CACHE);
}
ipa_cmd_register_write_add(trans, offset, val, val, false);
ipa_cmd_register_write_add(trans, reg_offset(reg), val, val, false);
gsi_trans_commit_wait(trans);
......@@ -495,22 +492,22 @@ static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint)
{
u32 endpoint_id = endpoint->endpoint_id;
struct ipa *ipa = endpoint->ipa;
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
if (ipa->version < IPA_VERSION_5_0) {
reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG);
offset = ipa_reg_n_offset(reg, endpoint_id);
offset = reg_n_offset(reg, endpoint_id);
val = ioread32(endpoint->ipa->reg_virt + offset);
/* Zero all filter-related fields, preserving the rest */
val &= ~ipa_reg_fmask(reg, FILTER_HASH_MSK_ALL);
val &= ~reg_fmask(reg, FILTER_HASH_MSK_ALL);
} else {
/* IPA v5.0 separates filter and router cache configuration */
reg = ipa_reg(ipa, ENDP_FILTER_CACHE_CFG);
offset = ipa_reg_n_offset(reg, endpoint_id);
offset = reg_n_offset(reg, endpoint_id);
/* Zero all filter-related fields */
val = 0;
......@@ -554,22 +551,22 @@ static bool ipa_route_id_modem(struct ipa *ipa, u32 route_id)
*/
static void ipa_route_tuple_zero(struct ipa *ipa, u32 route_id)
{
const struct ipa_reg *reg;
const struct reg *reg;
u32 offset;
u32 val;
if (ipa->version < IPA_VERSION_5_0) {
reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG);
offset = ipa_reg_n_offset(reg, route_id);
offset = reg_n_offset(reg, route_id);
val = ioread32(ipa->reg_virt + offset);
/* Zero all route-related fields, preserving the rest */
val &= ~ipa_reg_fmask(reg, ROUTER_HASH_MSK_ALL);
val &= ~reg_fmask(reg, ROUTER_HASH_MSK_ALL);
} else {
/* IPA v5.0 separates filter and router cache configuration */
reg = ipa_reg(ipa, ENDP_ROUTER_CACHE_CFG);
offset = ipa_reg_n_offset(reg, route_id);
offset = reg_n_offset(reg, route_id);
/* Zero all route-related fields */
val = 0;
......
drivers/net/ipa/ipa_uc.c
View file @ 01a7ee36
......@@ -231,7 +231,7 @@ void ipa_uc_power(struct ipa *ipa)
static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
{
struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
const struct ipa_reg *reg;
const struct reg *reg;
u32 val;
/* Fill in the command data */
......@@ -243,9 +243,9 @@ static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
/* Use an interrupt to tell the microcontroller the command is ready */
reg = ipa_reg(ipa, IPA_IRQ_UC);
val = ipa_reg_bit(reg, UC_INTR);
val = reg_bit(reg, UC_INTR);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
iowrite32(val, ipa->reg_virt + reg_offset(reg));
}
/* Tell the microcontroller the AP is shutting down */
......
drivers/net/ipa/ipa_version.h
View file @ 01a7ee36
......@@ -9,7 +9,7 @@
/**
* enum ipa_version
* @IPA_VERSION_3_0: IPA version 3.0/GSI version 1.0
* @IPA_VERSION_3_1: IPA version 3.1/GSI version 1.1
* @IPA_VERSION_3_1: IPA version 3.1/GSI version 1.0
* @IPA_VERSION_3_5: IPA version 3.5/GSI version 1.2
* @IPA_VERSION_3_5_1: IPA version 3.5.1/GSI version 1.3
* @IPA_VERSION_4_0: IPA version 4.0/GSI version 2.0
......@@ -20,6 +20,8 @@
* @IPA_VERSION_4_9: IPA version 4.9/GSI version 2.9
* @IPA_VERSION_4_11: IPA version 4.11/GSI version 2.11 (2.1.1)
* @IPA_VERSION_5_0: IPA version 5.0/GSI version 3.0
* @IPA_VERSION_5_1: IPA version 5.1/GSI version 3.0
* @IPA_VERSION_5_5: IPA version 5.5/GSI version 5.5
* @IPA_VERSION_COUNT: Number of defined IPA versions
*
* Defines the version of IPA (and GSI) hardware present on the platform.
......@@ -38,6 +40,8 @@ enum ipa_version {
IPA_VERSION_4_9,
IPA_VERSION_4_11,
IPA_VERSION_5_0,
IPA_VERSION_5_1,
IPA_VERSION_5_5,
IPA_VERSION_COUNT, /* Last; not a version */
};
......
drivers/net/ipa/reg.h 0 → 100644
View file @ 01a7ee36
/* SPDX-License-Identifier: GPL-2.0 */
/* *Copyright (C) 2022-2023 Linaro Ltd. */
#ifndef _REG_H_
#define _REG_H_
#include <linux/types.h>
#include <linux/bits.h>
/**
* struct reg - A register descriptor
* @offset: Register offset relative to base of register memory
* @stride: Distance between two instances, if parameterized
* @fcount: Number of entries in the @fmask array
* @fmask: Array of mask values defining position and width of fields
* @name: Upper-case name of the register
*/
struct reg {
u32 offset;
u32 stride;
u32 fcount;
const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */
const char *name;
};
/* Helper macro for defining "simple" (non-parameterized) registers */
#define REG(__NAME, __reg_id, __offset) \
REG_STRIDE(__NAME, __reg_id, __offset, 0)
/* Helper macro for defining parameterized registers, specifying stride */
#define REG_STRIDE(__NAME, __reg_id, __offset, __stride) \
static const struct reg reg_ ## __reg_id = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
}
#define REG_FIELDS(__NAME, __name, __offset) \
REG_STRIDE_FIELDS(__NAME, __name, __offset, 0)
#define REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \
static const struct reg reg_ ## __name = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
.fcount = ARRAY_SIZE(reg_ ## __name ## _fmask), \
.fmask = reg_ ## __name ## _fmask, \
}
/**
* struct regs - Description of registers supported by hardware
* @reg_count: Number of registers in the @reg[] array
* @reg: Array of register descriptors
*/
struct regs {
u32 reg_count;
const struct reg **reg;
};
static inline const struct reg *reg(const struct regs *regs, u32 reg_id)
{
if (WARN(reg_id >= regs->reg_count,
"reg out of range (%u > %u)\n", reg_id, regs->reg_count - 1))
return NULL;
return regs->reg[reg_id];
}
/* Return the field mask for a field in a register, or 0 on error */
static inline u32 reg_fmask(const struct reg *reg, u32 field_id)
{
if (!reg || WARN_ON(field_id >= reg->fcount))
return 0;
return reg->fmask[field_id];
}
/* Return the mask for a single-bit field in a register, or 0 on error */
static inline u32 reg_bit(const struct reg *reg, u32 field_id)
{
u32 fmask = reg_fmask(reg, field_id);
if (WARN_ON(!is_power_of_2(fmask)))
return 0;
return fmask;
}
/* Return the maximum value representable by the given field; always 2^n - 1 */
static inline u32 reg_field_max(const struct reg *reg, u32 field_id)
{
u32 fmask = reg_fmask(reg, field_id);
return fmask ? fmask >> __ffs(fmask) : 0;
}
/* Encode a value into the given field of a register */
static inline u32 reg_encode(const struct reg *reg, u32 field_id, u32 val)
{
u32 fmask = reg_fmask(reg, field_id);
if (!fmask)
return 0;
val <<= __ffs(fmask);
if (WARN_ON(val & ~fmask))
return 0;
return val;
}
/* Given a register value, decode (extract) the value in the given field */
static inline u32 reg_decode(const struct reg *reg, u32 field_id, u32 val)
{
u32 fmask = reg_fmask(reg, field_id);
return fmask ? (val & fmask) >> __ffs(fmask) : 0;
}
/* Returns 0 for NULL reg; warning should have already been issued */
static inline u32 reg_offset(const struct reg *reg)
{
return reg ? reg->offset : 0;
}
/* Returns 0 for NULL reg; warning should have already been issued */
static inline u32 reg_n_offset(const struct reg *reg, u32 n)
{
return reg ? reg->offset + n * reg->stride : 0;
}
#endif /* _REG_H_ */
drivers/net/ipa/reg/ipa_reg-v3.1.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -16,9 +16,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -39,9 +39,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -52,31 +52,31 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -87,9 +87,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -100,121 +100,121 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_counter_cfg_fmask[] = {
static const u32 reg_counter_cfg_fmask[] = {
[EOT_COAL_GRANULARITY] = GENMASK(3, 0),
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000040c, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000040c, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(7, 0),
[X_MAX_LIM] = GENMASK(15, 8),
[Y_MIN_LIM] = GENMASK(23, 16),
[Y_MAX_LIM] = GENMASK(31, 24),
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
static const u32 ipa_reg_endp_init_ctrl_fmask[] = {
static const u32 reg_endp_init_ctrl_fmask[] = {
[ENDP_SUSPEND] = BIT(0),
[ENDP_DELAY] = BIT(1),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -223,16 +223,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -245,9 +245,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
/* Bits 29-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -257,12 +257,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 14-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -274,9 +274,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
......@@ -289,25 +289,25 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
/* Entire register is a tick count */
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(31, 0),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -317,25 +317,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
......@@ -343,9 +342,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -366,84 +365,84 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[IPA_BCR] = &ipa_reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[COUNTER_CFG] = &ipa_reg_counter_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v3_1 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CTRL] = &reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v3_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -16,9 +16,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -44,9 +44,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -57,31 +57,31 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -92,9 +92,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -105,42 +105,42 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_counter_cfg_fmask[] = {
static const u32 reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
[TX0_PREFETCH_DISABLE] = BIT(0),
[TX1_PREFETCH_DISABLE] = BIT(1),
[PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -151,17 +151,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -172,10 +172,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -186,10 +186,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -200,10 +200,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -214,18 +214,18 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_endp_init_ctrl_fmask[] = {
static const u32 reg_endp_init_ctrl_fmask[] = {
[ENDP_SUSPEND] = BIT(0),
[ENDP_DELAY] = BIT(1),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -234,16 +234,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -256,9 +256,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
/* Bits 29-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -268,12 +268,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 14-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -285,9 +285,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
......@@ -300,25 +300,25 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
/* Entire register is a tick count */
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(31, 0),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -328,25 +328,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
......@@ -354,9 +353,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -377,83 +376,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[IPA_BCR] = &ipa_reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[COUNTER_CFG] = &ipa_reg_counter_cfg,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v3_5_1 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CTRL] = &reg_endp_init_ctrl,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v3_5_1 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v4.11.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -36,9 +36,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -73,9 +73,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
[DRBIP] = BIT(31),
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -86,24 +86,24 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
......@@ -111,9 +111,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = {
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -124,9 +124,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -137,23 +137,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
......@@ -166,9 +166,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 19-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -179,17 +179,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
......@@ -199,26 +199,26 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = {
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = {
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
/* Bits 9-31 reserved */
};
IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -229,10 +229,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -243,10 +243,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -257,10 +257,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -271,10 +271,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -283,16 +283,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -305,9 +305,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -321,12 +321,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -338,9 +338,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
......@@ -355,27 +355,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -385,24 +385,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
......@@ -410,9 +409,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 10-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -433,83 +432,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v4_11 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_11 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v4.2.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -29,9 +29,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -65,9 +65,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -78,24 +78,24 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
......@@ -103,9 +103,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = {
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -116,9 +116,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -129,33 +129,33 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_counter_cfg_fmask[] = {
static const u32 reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 9-31 reserved */
};
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
......@@ -169,9 +169,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 20-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -182,17 +182,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -203,10 +203,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -217,10 +217,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -231,10 +231,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -245,10 +245,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -257,16 +257,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -279,9 +279,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
/* Bits 29-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -291,12 +291,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 14-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
/* Bit 3 reserved */
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -308,9 +308,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(9, 5),
......@@ -323,27 +323,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_BASE_VALUE] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_SCALE] = GENMASK(12, 8),
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -353,25 +353,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
[SEQ_REP_TYPE] = GENMASK(15, 8),
/* Bits 16-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-7 reserved */
......@@ -380,80 +379,80 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 10-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[IPA_BCR] = &ipa_reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[COUNTER_CFG] = &ipa_reg_counter_cfg,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v4_2 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[IPA_BCR] = &reg_ipa_bcr,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[COUNTER_CFG] = &reg_counter_cfg,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_2 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v4.5.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -30,9 +30,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -67,9 +67,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -80,24 +80,24 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
......@@ -105,9 +105,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = {
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -118,9 +118,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -131,23 +131,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
......@@ -159,9 +159,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 18-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -172,17 +172,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
......@@ -192,25 +192,25 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = {
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = {
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -221,10 +221,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -235,10 +235,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -249,10 +249,10 @@ static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -263,10 +263,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -277,10 +277,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -291,10 +291,10 @@ static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -303,16 +303,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -325,9 +325,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -341,12 +341,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -357,9 +357,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
......@@ -374,27 +374,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -404,24 +404,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
......@@ -429,9 +428,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 10-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -452,85 +451,85 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v4_5 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_5 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v4.7.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -30,9 +30,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -67,9 +67,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
[DRBIP] = BIT(31),
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -80,24 +80,24 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
......@@ -105,9 +105,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = {
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -118,9 +118,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -131,23 +131,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
......@@ -160,9 +160,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 19-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -173,17 +173,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
......@@ -193,25 +193,25 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = {
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = {
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -222,10 +222,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -236,10 +236,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -250,10 +250,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -264,10 +264,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -276,16 +276,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -298,9 +298,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -314,12 +314,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -330,9 +330,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
......@@ -347,27 +347,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -377,24 +377,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
......@@ -402,9 +401,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 10-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -425,83 +424,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v4_7 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_7 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
drivers/net/ipa/reg/ipa_reg-v4.9.c
View file @ 01a7ee36
......@@ -7,7 +7,7 @@
#include "../ipa.h"
#include "../ipa_reg.h"
static const u32 ipa_reg_comp_cfg_fmask[] = {
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
......@@ -35,9 +35,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = {
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_fmask[] = {
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
......@@ -72,9 +72,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = {
[DRBIP] = BIT(31),
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_fmask[] = {
static const u32 reg_route_fmask[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
......@@ -85,24 +85,24 @@ static const u32 ipa_reg_route_fmask[] = {
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_fmask[] = {
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_fmask[] = {
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_fmask[] = {
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
......@@ -110,9 +110,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = {
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
static const u32 reg_filt_rout_hash_en_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -123,9 +123,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
static const u32 reg_filt_rout_hash_flush_fmask[] = {
[IPV6_ROUTER_HASH] = BIT(0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = BIT(4),
......@@ -136,23 +136,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = {
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
......@@ -165,9 +165,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 19-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_flavor_0_fmask[] = {
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(3, 0),
/* Bits 4-7 reserved */
[MAX_CONS_PIPES] = GENMASK(12, 8),
......@@ -178,17 +178,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
static const u32 ipa_reg_idle_indication_cfg_fmask[] = {
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
/* Bits 5-6 reserved */
[DPL_TIMESTAMP_SEL] = BIT(7),
......@@ -198,25 +198,25 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = {
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = {
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
};
IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -227,10 +227,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -241,10 +241,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -255,10 +255,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
......@@ -269,10 +269,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
......@@ -281,16 +281,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = {
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
static const u32 ipa_reg_endp_init_nat_fmask[] = {
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
......@@ -302,9 +302,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = {
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
......@@ -318,12 +318,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
/* Bits 22-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00000818, 0x0070);
static const u32 ipa_reg_endp_init_mode_fmask[] = {
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(8, 4),
......@@ -335,9 +335,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = {
/* Bit 31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
static const u32 ipa_reg_endp_init_aggr_fmask[] = {
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
......@@ -352,27 +352,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = {
/* Bits 28-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = {
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000082c, 0x0070);
static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = {
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = BIT(8),
/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00000830, 0x0070);
static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
......@@ -382,24 +382,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = {
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = {
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp,
0x00000838, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
static const u32 ipa_reg_endp_init_seq_fmask[] = {
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
static const u32 ipa_reg_endp_status_fmask[] = {
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(5, 1),
/* Bits 6-8 reserved */
......@@ -407,9 +406,9 @@ static const u32 ipa_reg_endp_status_fmask[] = {
/* Bits 10-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
[FILTER_HASH_MSK_SRC_ID] = BIT(0),
[FILTER_HASH_MSK_SRC_IP] = BIT(1),
[FILTER_HASH_MSK_DST_IP] = BIT(2),
......@@ -430,83 +429,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = {
/* Bits 23-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
0x0000085c, 0x0070);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
static const u32 ipa_reg_ipa_irq_uc_fmask[] = {
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct ipa_reg *ipa_reg_array[] = {
[COMP_CFG] = &ipa_reg_comp_cfg,
[CLKON_CFG] = &ipa_reg_clkon_cfg,
[ROUTE] = &ipa_reg_route,
[SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg,
[FLAVOR_0] = &ipa_reg_flavor_0,
[IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg,
[ENDP_INIT_NAT] = &ipa_reg_endp_init_nat,
[ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &ipa_reg_endp_init_mode,
[ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq,
[ENDP_STATUS] = &ipa_reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts,
[IPA_IRQ_EN] = &ipa_reg_ipa_irq_en,
[IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr,
[IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr,
};
const struct ipa_regs ipa_regs_v4_9 = {
.reg_count = ARRAY_SIZE(ipa_reg_array),
.reg = ipa_reg_array,
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
[FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v4_9 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7