Commit 01b887c3 authored by Dave Airlie's avatar Dave Airlie

drm/i915: add some registers need for displayport MST support.

These are just from the Haswell spec.
Reviewed-by: default avatarTodd Previte <tprevite@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent e7c36347
...@@ -5815,6 +5815,7 @@ enum punit_power_well { ...@@ -5815,6 +5815,7 @@ enum punit_power_well {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
#define TRANS_DDI_BFI_ENABLE (1<<4) #define TRANS_DDI_BFI_ENABLE (1<<4)
/* DisplayPort Transport Control */ /* DisplayPort Transport Control */
...@@ -5824,6 +5825,7 @@ enum punit_power_well { ...@@ -5824,6 +5825,7 @@ enum punit_power_well {
#define DP_TP_CTL_ENABLE (1<<31) #define DP_TP_CTL_ENABLE (1<<31)
#define DP_TP_CTL_MODE_SST (0<<27) #define DP_TP_CTL_MODE_SST (0<<27)
#define DP_TP_CTL_MODE_MST (1<<27) #define DP_TP_CTL_MODE_MST (1<<27)
#define DP_TP_CTL_FORCE_ACT (1<<25)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
...@@ -5838,8 +5840,13 @@ enum punit_power_well { ...@@ -5838,8 +5840,13 @@ enum punit_power_well {
#define DP_TP_STATUS_A 0x64044 #define DP_TP_STATUS_A 0x64044
#define DP_TP_STATUS_B 0x64144 #define DP_TP_STATUS_B 0x64144
#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
#define DP_TP_STATUS_IDLE_DONE (1<<25) #define DP_TP_STATUS_IDLE_DONE (1<<25)
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) #define DP_TP_STATUS_ACT_SENT (1<<24)
#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
/* DDI Buffer Control */ /* DDI Buffer Control */
#define DDI_BUF_CTL_A 0x64000 #define DDI_BUF_CTL_A 0x64000
......
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