Commit 01eb5698 authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Nicolas Pitre

plat-orion: share IRQ handling code

Split off Orion IRQ handling code into plat-orion/, and add
support for multiple sets of (32) interrupts.
Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Reviewed-by: default avatarTzachi Perelstein <tzachi@marvell.com>
Acked-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent 69b02f6a
......@@ -15,6 +15,7 @@
#include <linux/irq.h>
#include <asm/gpio.h>
#include <asm/arch/orion.h>
#include <asm/plat-orion/irq.h>
#include "common.h"
/*****************************************************************************
......@@ -197,41 +198,9 @@ static void __init orion_init_gpio_irq(void)
/*****************************************************************************
* Orion Main IRQ
****************************************************************************/
static void orion_main_irq_mask(u32 irq)
{
orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
}
static void orion_main_irq_unmask(u32 irq)
{
orion_setbits(MAIN_IRQ_MASK, 1 << irq);
}
static struct irq_chip orion_main_irq_chip = {
.name = "Orion-IRQ-Main",
.ack = orion_main_irq_mask,
.mask = orion_main_irq_mask,
.unmask = orion_main_irq_unmask,
};
static void __init orion_init_main_irq(void)
{
int i;
/*
* Mask and clear Main IRQ interrupts
*/
orion_write(MAIN_IRQ_MASK, 0x0);
orion_write(MAIN_IRQ_CAUSE, 0x0);
/*
* Register level handler for Main IRQs
*/
for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
set_irq_chip(i, &orion_main_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
}
void __init orion_init_irq(void)
......
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y :=
obj-y := irq.o
obj-m :=
obj-n :=
obj- :=
/*
* arch/arm/plat-orion/irq.c
*
* Marvell Orion SoC IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/plat-orion/irq.h>
static void orion_irq_mask(u32 irq)
{
void __iomem *maskaddr = get_irq_chip_data(irq);
u32 mask;
mask = readl(maskaddr);
mask &= ~(1 << (irq & 31));
writel(mask, maskaddr);
}
static void orion_irq_unmask(u32 irq)
{
void __iomem *maskaddr = get_irq_chip_data(irq);
u32 mask;
mask = readl(maskaddr);
mask |= 1 << (irq & 31);
writel(mask, maskaddr);
}
static struct irq_chip orion_irq_chip = {
.name = "orion_irq",
.ack = orion_irq_mask,
.mask = orion_irq_mask,
.unmask = orion_irq_unmask,
};
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
unsigned int i;
/*
* Mask all interrupts initially.
*/
writel(0, maskaddr);
/*
* Register IRQ sources.
*/
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
set_irq_chip(irq, &orion_irq_chip);
set_irq_chip_data(irq, maskaddr);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
/*
* include/asm-arm/plat-orion/irq.h
*
* Marvell Orion SoC IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_IRQ_H
#define __ASM_PLAT_ORION_IRQ_H
void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
#endif
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