Commit 020cefac authored by Anthony Koo's avatar Anthony Koo Committed by Alex Deucher

drm/amd/display: [FW Promotion] Release 0.0.220.0

 - Change ordering of structs to put enums together
 - Add new define DMUB_TRACE_ENTRY_DEFINED to guard
   the trace code enum
Acked-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: default avatarAnthony Koo <anthony.koo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1a90ec2e
...@@ -558,6 +558,7 @@ union dmub_fw_meta { ...@@ -558,6 +558,7 @@ union dmub_fw_meta {
//============================================================================== //==============================================================================
//< DMUB Trace Buffer>================================================================ //< DMUB Trace Buffer>================================================================
//============================================================================== //==============================================================================
#if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
/** /**
* dmub_trace_code_t - firmware trace code, 32-bits * dmub_trace_code_t - firmware trace code, 32-bits
*/ */
...@@ -572,6 +573,7 @@ struct dmcub_trace_buf_entry { ...@@ -572,6 +573,7 @@ struct dmcub_trace_buf_entry {
uint32_t param0; /**< trace defined parameter 0 */ uint32_t param0; /**< trace defined parameter 0 */
uint32_t param1; /**< trace defined parameter 1 */ uint32_t param1; /**< trace defined parameter 1 */
}; };
#endif
//============================================================================== //==============================================================================
//< DMUB_STATUS>================================================================ //< DMUB_STATUS>================================================================
...@@ -2538,6 +2540,18 @@ enum dmub_cmd_psr_type { ...@@ -2538,6 +2540,18 @@ enum dmub_cmd_psr_type {
DMUB_CMD__SET_PSR_POWER_OPT = 7, DMUB_CMD__SET_PSR_POWER_OPT = 7,
}; };
/**
* Different PSR residency modes.
* Different modes change the definition of PSR residency.
*/
enum psr_residency_mode {
PSR_RESIDENCY_MODE_PHY = 0,
PSR_RESIDENCY_MODE_ALPM,
PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
/* Do not add below. */
PSR_RESIDENCY_MODE_LAST_ELEMENT,
};
enum dmub_cmd_fams_type { enum dmub_cmd_fams_type {
DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
DMUB_CMD__FAMS_DRR_UPDATE = 1, DMUB_CMD__FAMS_DRR_UPDATE = 1,
...@@ -3259,18 +3273,6 @@ struct dmub_rb_cmd_psr_set_power_opt { ...@@ -3259,18 +3273,6 @@ struct dmub_rb_cmd_psr_set_power_opt {
struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
}; };
/**
* Different PSR residency modes.
* Different modes change the definition of PSR residency.
*/
enum psr_residency_mode {
PSR_RESIDENCY_MODE_PHY = 0,
PSR_RESIDENCY_MODE_ALPM,
PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
/* Do not add below. */
PSR_RESIDENCY_MODE_LAST_ELEMENT,
};
/** /**
* Definition of Replay Residency GPINT command. * Definition of Replay Residency GPINT command.
* Bit[0] - Residency mode for Revision 0 * Bit[0] - Residency mode for Revision 0
......
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